thunder2-99xx.dtsi

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10

    1 // SPDX-License-Identifier: GPL-2.0-or-later
    2 /*
    3  * dtsi file for Cavium ThunderX2 CN99XX processor
    4  *
    5  * Copyright (c) 2017 Cavium Inc.
    6  * Copyright (c) 2013-2016 Broadcom
    7  * Author: Zi Shen Lim <zlim@broadcom.com>
    8  */
    9 
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 
   12 / {
   13         model = "Cavium ThunderX2 CN99XX";
   14         compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc";
   15         interrupt-parent = <&gic>;
   16         #address-cells = <2>;
   17         #size-cells = <2>;
   18 
   19         /* just 4 cpus now, 128 needed in full config */
   20         cpus {
   21                 #address-cells = <0x2>;
   22                 #size-cells = <0x0>;
   23 
   24                 cpu@0 {
   25                         device_type = "cpu";
   26                         compatible = "cavium,thunder2", "brcm,vulcan";
   27                         reg = <0x0 0x0>;
   28                         enable-method = "psci";
   29                 };
   30 
   31                 cpu@1 {
   32                         device_type = "cpu";
   33                         compatible = "cavium,thunder2", "brcm,vulcan";
   34                         reg = <0x0 0x1>;
   35                         enable-method = "psci";
   36                 };
   37 
   38                 cpu@2 {
   39                         device_type = "cpu";
   40                         compatible = "cavium,thunder2", "brcm,vulcan";
   41                         reg = <0x0 0x2>;
   42                         enable-method = "psci";
   43                 };
   44 
   45                 cpu@3 {
   46                         device_type = "cpu";
   47                         compatible = "cavium,thunder2", "brcm,vulcan";
   48                         reg = <0x0 0x3>;
   49                         enable-method = "psci";
   50                 };
   51         };
   52 
   53         psci {
   54                 compatible = "arm,psci-0.2";
   55                 method = "smc";
   56         };
   57 
   58         gic: interrupt-controller@400080000 {
   59                 compatible = "arm,gic-v3";
   60                 #interrupt-cells = <3>;
   61                 #address-cells = <2>;
   62                 #size-cells = <2>;
   63                 ranges;
   64                 interrupt-controller;
   65                 #redistributor-regions = <1>;
   66                 reg = <0x04 0x00080000 0x0 0x20000>,    /* GICD */
   67                       <0x04 0x01000000 0x0 0x1000000>;  /* GICR */
   68                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
   69 
   70                 gicits: gic-its@40010000 {
   71                         compatible = "arm,gic-v3-its";
   72                         msi-controller;
   73                         reg = <0x04 0x00100000 0x0 0x20000>;    /* GIC ITS */
   74                 };
   75         };
   76 
   77         timer {
   78                 compatible = "arm,armv8-timer";
   79                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
   80                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
   81                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
   82                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
   83         };
   84 
   85         pmu {
   86                 compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3";
   87                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
   88         };
   89 
   90         clk125mhz: uart_clk125mhz {
   91                 compatible = "fixed-clock";
   92                 #clock-cells = <0>;
   93                 clock-frequency = <125000000>;
   94                 clock-output-names = "clk125mhz";
   95         };
   96 
   97         pcie@30000000 {
   98                 compatible = "pci-host-ecam-generic";
   99                 device_type = "pci";
  100                 #interrupt-cells = <1>;
  101                 #address-cells = <3>;
  102                 #size-cells = <2>;
  103 
  104                 /* ECAM at 0x3000_0000 - 0x4000_0000 */
  105                 reg = <0x0 0x30000000  0x0 0x10000000>;
  106                 reg-names = "PCI ECAM";
  107 
  108                 /*
  109                  * PCI ranges:
  110                  *   IO         no supported
  111                  *   MEM        0x4000_0000 - 0x6000_0000
  112                  *   MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
  113                  */
  114                 ranges =
  115                   <0x02000000    0 0x40000000    0 0x40000000    0 0x20000000
  116                    0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
  117                 bus-range = <0 0xff>;
  118                 interrupt-map-mask = <0 0 0 7>;
  119                 interrupt-map =
  120                       /* addr  pin  ic   icaddr  icintr */
  121                         <0 0 0  1  &gic   0 0    GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
  122                          0 0 0  2  &gic   0 0    GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
  123                          0 0 0  3  &gic   0 0    GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
  124                          0 0 0  4  &gic   0 0    GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  125                 msi-parent = <&gicits>;
  126                 dma-coherent;
  127         };
  128 
  129         soc {
  130                 compatible = "simple-bus";
  131                 #address-cells = <2>;
  132                 #size-cells = <2>;
  133                 ranges;
  134 
  135                 uart0: serial@402020000 {
  136                         compatible = "arm,pl011", "arm,primecell";
  137                         reg = <0x04 0x02020000 0x0 0x1000>;
  138                         interrupt-parent = <&gic>;
  139                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
  140                         clocks = <&clk125mhz>;
  141                         clock-names = "apb_pclk";
  142                 };
  143         };
  144 
  145 };

Cache object: 1c6c2fdf87c0128c0ff0cb14d90f8bad

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.

FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/cavium/thunder2-99xx.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/cavium/thunder2-99xx.dtsi