exynos7885.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Samsung Exynos7885 SoC device tree source
    4  *
    5  * Copyright (c) 2021 Samsung Electronics Co., Ltd.
    6  * Copyright (c) 2021 Dávid Virág
    7  */
    8 
    9 #include <dt-bindings/clock/exynos7885.h>
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 
   12 / {
   13         compatible = "samsung,exynos7885";
   14         #address-cells = <2>;
   15         #size-cells = <1>;
   16 
   17         interrupt-parent = <&gic>;
   18 
   19         aliases {
   20                 pinctrl0 = &pinctrl_alive;
   21                 pinctrl1 = &pinctrl_dispaud;
   22                 pinctrl2 = &pinctrl_fsys;
   23                 pinctrl3 = &pinctrl_top;
   24         };
   25 
   26         arm-a53-pmu {
   27                 compatible = "arm,cortex-a53-pmu";
   28                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
   29                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
   30                              <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
   31                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
   32                              <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
   33                              <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
   34                 interrupt-affinity = <&cpu0>,
   35                                      <&cpu1>,
   36                                      <&cpu2>,
   37                                      <&cpu3>,
   38                                      <&cpu4>,
   39                                      <&cpu5>;
   40         };
   41 
   42         arm-a73-pmu {
   43                 compatible = "arm,cortex-a73-pmu";
   44                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
   45                              <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
   46                 interrupt-affinity = <&cpu6>,
   47                                      <&cpu7>;
   48         };
   49 
   50         cpus {
   51                 #address-cells = <1>;
   52                 #size-cells = <0>;
   53 
   54                 cpu-map {
   55                         cluster0 {
   56                                 core0 {
   57                                         cpu = <&cpu0>;
   58                                 };
   59                                 core1 {
   60                                         cpu = <&cpu1>;
   61                                 };
   62                                 core2 {
   63                                         cpu = <&cpu2>;
   64                                 };
   65                                 core3 {
   66                                         cpu = <&cpu3>;
   67                                 };
   68                                 core4 {
   69                                         cpu = <&cpu4>;
   70                                 };
   71                                 core5 {
   72                                         cpu = <&cpu5>;
   73                                 };
   74                         };
   75 
   76                         cluster1 {
   77                                 core0 {
   78                                         cpu = <&cpu6>;
   79                                 };
   80                                 core1 {
   81                                         cpu = <&cpu7>;
   82                                 };
   83                         };
   84                 };
   85 
   86                 cpu0: cpu@100 {
   87                         device_type = "cpu";
   88                         compatible = "arm,cortex-a53";
   89                         reg = <0x100>;
   90                         enable-method = "psci";
   91                 };
   92 
   93                 cpu1: cpu@101 {
   94                         device_type = "cpu";
   95                         compatible = "arm,cortex-a53";
   96                         reg = <0x101>;
   97                         enable-method = "psci";
   98                 };
   99 
  100                 cpu2: cpu@102 {
  101                         device_type = "cpu";
  102                         compatible = "arm,cortex-a53";
  103                         reg = <0x102>;
  104                         enable-method = "psci";
  105                 };
  106 
  107                 cpu3: cpu@103 {
  108                         device_type = "cpu";
  109                         compatible = "arm,cortex-a53";
  110                         reg = <0x103>;
  111                         enable-method = "psci";
  112                 };
  113 
  114                 cpu4: cpu@200 {
  115                         device_type = "cpu";
  116                         compatible = "arm,cortex-a53";
  117                         reg = <0x200>;
  118                         enable-method = "psci";
  119                 };
  120 
  121                 cpu5: cpu@201 {
  122                         device_type = "cpu";
  123                         compatible = "arm,cortex-a53";
  124                         reg = <0x201>;
  125                         enable-method = "psci";
  126                 };
  127 
  128                 cpu6: cpu@0 {
  129                         device_type = "cpu";
  130                         compatible = "arm,cortex-a73";
  131                         reg = <0x0>;
  132                         enable-method = "psci";
  133                 };
  134 
  135                 cpu7: cpu@1 {
  136                         device_type = "cpu";
  137                         compatible = "arm,cortex-a73";
  138                         reg = <0x1>;
  139                         enable-method = "psci";
  140                 };
  141         };
  142 
  143         psci {
  144                 compatible = "arm,psci";
  145                 method = "smc";
  146                 cpu_suspend = <0xc4000001>;
  147                 cpu_off = <0x84000002>;
  148                 cpu_on = <0xc4000003>;
  149         };
  150 
  151         timer {
  152                 compatible = "arm,armv8-timer";
  153                 /* Hypervisor Virtual Timer interrupt is not wired to GIC */
  154                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  155                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  156                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  157                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
  158         };
  159 
  160         fixed-rate-clocks {
  161                 oscclk: osc-clock {
  162                         compatible = "fixed-clock";
  163                         #clock-cells = <0>;
  164                         clock-output-names = "oscclk";
  165                 };
  166         };
  167 
  168         soc: soc@0 {
  169                 compatible = "simple-bus";
  170                 #address-cells = <1>;
  171                 #size-cells = <1>;
  172                 ranges = <0x0 0x0 0x0 0x20000000>;
  173 
  174                 chipid@10000000 {
  175                         compatible = "samsung,exynos850-chipid";
  176                         reg = <0x10000000 0x24>;
  177                 };
  178 
  179                 gic: interrupt-controller@12301000 {
  180                         compatible = "arm,gic-400";
  181                         #interrupt-cells = <3>;
  182                         #address-cells = <0>;
  183                         interrupt-controller;
  184                         reg = <0x12301000 0x1000>,
  185                               <0x12302000 0x2000>,
  186                               <0x12304000 0x2000>,
  187                               <0x12306000 0x2000>;
  188                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
  189                                                  IRQ_TYPE_LEVEL_HIGH)>;
  190                 };
  191 
  192                 cmu_peri: clock-controller@10010000 {
  193                         compatible = "samsung,exynos7885-cmu-peri";
  194                         reg = <0x10010000 0x8000>;
  195                         #clock-cells = <1>;
  196 
  197                         clocks = <&oscclk>,
  198                                  <&cmu_top CLK_DOUT_PERI_BUS>,
  199                                  <&cmu_top CLK_DOUT_PERI_SPI0>,
  200                                  <&cmu_top CLK_DOUT_PERI_SPI1>,
  201                                  <&cmu_top CLK_DOUT_PERI_UART0>,
  202                                  <&cmu_top CLK_DOUT_PERI_UART1>,
  203                                  <&cmu_top CLK_DOUT_PERI_UART2>,
  204                                  <&cmu_top CLK_DOUT_PERI_USI0>,
  205                                  <&cmu_top CLK_DOUT_PERI_USI1>,
  206                                  <&cmu_top CLK_DOUT_PERI_USI2>;
  207                         clock-names = "oscclk",
  208                                       "dout_peri_bus",
  209                                       "dout_peri_spi0",
  210                                       "dout_peri_spi1",
  211                                       "dout_peri_uart0",
  212                                       "dout_peri_uart1",
  213                                       "dout_peri_uart2",
  214                                       "dout_peri_usi0",
  215                                       "dout_peri_usi1",
  216                                       "dout_peri_usi2";
  217                 };
  218 
  219                 cmu_core: clock-controller@12000000 {
  220                         compatible = "samsung,exynos7885-cmu-core";
  221                         reg = <0x12000000 0x8000>;
  222                         #clock-cells = <1>;
  223 
  224                         clocks = <&oscclk>,
  225                                  <&cmu_top CLK_DOUT_CORE_BUS>,
  226                                  <&cmu_top CLK_DOUT_CORE_CCI>,
  227                                  <&cmu_top CLK_DOUT_CORE_G3D>;
  228                         clock-names = "oscclk",
  229                                       "dout_core_bus",
  230                                       "dout_core_cci",
  231                                       "dout_core_g3d";
  232                 };
  233 
  234                 cmu_top: clock-controller@12060000 {
  235                         compatible = "samsung,exynos7885-cmu-top";
  236                         reg = <0x12060000 0x8000>;
  237                         #clock-cells = <1>;
  238 
  239                         clocks = <&oscclk>;
  240                         clock-names = "oscclk";
  241                 };
  242 
  243                 cmu_fsys: clock-controller@13400000 {
  244                         compatible = "samsung,exynos7885-cmu-fsys";
  245                         reg = <0x13400000 0x8000>;
  246                         #clock-cells = <1>;
  247 
  248                         clocks = <&oscclk>,
  249                                  <&cmu_top CLK_DOUT_FSYS_BUS>,
  250                                  <&cmu_top CLK_DOUT_FSYS_MMC_CARD>,
  251                                  <&cmu_top CLK_DOUT_FSYS_MMC_EMBD>,
  252                                  <&cmu_top CLK_DOUT_FSYS_MMC_SDIO>,
  253                                  <&cmu_top CLK_DOUT_FSYS_USB30DRD>;
  254                         clock-names = "oscclk",
  255                                       "dout_fsys_bus",
  256                                       "dout_fsys_mmc_card",
  257                                       "dout_fsys_mmc_embd",
  258                                       "dout_fsys_mmc_sdio",
  259                                       "dout_fsys_usb30drd";
  260                 };
  261 
  262                 pinctrl_alive: pinctrl@11cb0000 {
  263                         compatible = "samsung,exynos7885-pinctrl";
  264                         reg = <0x11cb0000 0x1000>;
  265 
  266                         wakeup-interrupt-controller {
  267                                 compatible = "samsung,exynos7-wakeup-eint";
  268                                 interrupt-parent = <&gic>;
  269                                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  270                         };
  271                 };
  272 
  273                 pinctrl_fsys: pinctrl@13430000 {
  274                         compatible = "samsung,exynos7885-pinctrl";
  275                         reg = <0x13430000 0x1000>;
  276                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
  277                 };
  278 
  279                 pinctrl_top: pinctrl@139b0000 {
  280                         compatible = "samsung,exynos7885-pinctrl";
  281                         reg = <0x139b0000 0x1000>;
  282                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
  283                 };
  284 
  285                 pinctrl_dispaud: pinctrl@148f0000 {
  286                         compatible = "samsung,exynos7885-pinctrl";
  287                         reg = <0x148f0000 0x1000>;
  288                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  289                 };
  290 
  291                 pmu_system_controller: system-controller@11c80000 {
  292                         compatible = "samsung,exynos7-pmu", "syscon";
  293                         reg = <0x11c80000 0x10000>;
  294                 };
  295 
  296                 mmc_0: mmc@13500000 {
  297                         compatible = "samsung,exynos7-dw-mshc-smu";
  298                         reg = <0x13500000 0x2000>;
  299                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  300                         #address-cells = <1>;
  301                         #size-cells = <0>;
  302                         clocks = <&cmu_fsys CLK_GOUT_MMC_EMBD_ACLK>,
  303                                  <&cmu_fsys CLK_GOUT_MMC_EMBD_SDCLKIN>;
  304                         clock-names = "biu", "ciu";
  305                         fifo-depth = <0x40>;
  306                         status = "disabled";
  307                 };
  308 
  309                 serial_0: serial@13800000 {
  310                         compatible = "samsung,exynos5433-uart";
  311                         reg = <0x13800000 0x100>;
  312                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
  313                         pinctrl-names = "default";
  314                         pinctrl-0 = <&uart0_bus>;
  315                         clocks = <&cmu_peri CLK_GOUT_UART0_PCLK>,
  316                                  <&cmu_peri CLK_GOUT_UART0_EXT_UCLK>;
  317                         clock-names = "uart", "clk_uart_baud0";
  318                         samsung,uart-fifosize = <64>;
  319                         status = "disabled";
  320                 };
  321 
  322                 serial_1: serial@13810000 {
  323                         compatible = "samsung,exynos5433-uart";
  324                         reg = <0x13810000 0x100>;
  325                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
  326                         pinctrl-names = "default";
  327                         pinctrl-0 = <&uart1_bus>;
  328                         clocks = <&cmu_peri CLK_GOUT_UART1_PCLK>,
  329                                  <&cmu_peri CLK_GOUT_UART1_EXT_UCLK>;
  330                         clock-names = "uart", "clk_uart_baud0";
  331                         samsung,uart-fifosize = <256>;
  332                         status = "disabled";
  333                 };
  334 
  335                 serial_2: serial@13820000 {
  336                         compatible = "samsung,exynos5433-uart";
  337                         reg = <0x13820000 0x100>;
  338                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
  339                         pinctrl-names = "default";
  340                         pinctrl-0 = <&uart2_bus>;
  341                         clocks = <&cmu_peri CLK_GOUT_UART2_PCLK>,
  342                                  <&cmu_peri CLK_GOUT_UART2_EXT_UCLK>;
  343                         clock-names = "uart", "clk_uart_baud0";
  344                         samsung,uart-fifosize = <256>;
  345                         status = "disabled";
  346                 };
  347 
  348                 i2c_0: i2c@13830000 {
  349                         compatible = "samsung,s3c2440-i2c";
  350                         reg = <0x13830000 0x100>;
  351                         interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
  352                         #address-cells = <1>;
  353                         #size-cells = <0>;
  354                         pinctrl-names = "default";
  355                         pinctrl-0 = <&i2c0_bus>;
  356                         clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>;
  357                         clock-names = "i2c";
  358                         status = "disabled";
  359                 };
  360 
  361                 i2c_1: i2c@13840000 {
  362                         compatible = "samsung,s3c2440-i2c";
  363                         reg = <0x13840000 0x100>;
  364                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
  365                         #address-cells = <1>;
  366                         #size-cells = <0>;
  367                         pinctrl-names = "default";
  368                         pinctrl-0 = <&i2c1_bus>;
  369                         clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>;
  370                         clock-names = "i2c";
  371                         status = "disabled";
  372                 };
  373 
  374                 i2c_2: i2c@13850000 {
  375                         compatible = "samsung,s3c2440-i2c";
  376                         reg = <0x13850000 0x100>;
  377                         interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
  378                         #address-cells = <1>;
  379                         #size-cells = <0>;
  380                         pinctrl-names = "default";
  381                         pinctrl-0 = <&i2c2_bus>;
  382                         clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>;
  383                         clock-names = "i2c";
  384                         status = "disabled";
  385                 };
  386 
  387                 i2c_3: i2c@13860000 {
  388                         compatible = "samsung,s3c2440-i2c";
  389                         reg = <0x13860000 0x100>;
  390                         interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
  391                         #address-cells = <1>;
  392                         #size-cells = <0>;
  393                         pinctrl-names = "default";
  394                         pinctrl-0 = <&i2c3_bus>;
  395                         clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>;
  396                         clock-names = "i2c";
  397                         status = "disabled";
  398                 };
  399 
  400                 i2c_4: i2c@13870000 {
  401                         compatible = "samsung,s3c2440-i2c";
  402                         reg = <0x13870000 0x100>;
  403                         interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
  404                         #address-cells = <1>;
  405                         #size-cells = <0>;
  406                         pinctrl-names = "default";
  407                         pinctrl-0 = <&i2c4_bus>;
  408                         clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>;
  409                         clock-names = "i2c";
  410                         status = "disabled";
  411                 };
  412 
  413                 i2c_5: i2c@13880000 {
  414                         compatible = "samsung,s3c2440-i2c";
  415                         reg = <0x13880000 0x100>;
  416                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
  417                         #address-cells = <1>;
  418                         #size-cells = <0>;
  419                         pinctrl-names = "default";
  420                         pinctrl-0 = <&i2c5_bus>;
  421                         clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>;
  422                         clock-names = "i2c";
  423                         status = "disabled";
  424                 };
  425 
  426                 i2c_6: i2c@13890000 {
  427                         compatible = "samsung,s3c2440-i2c";
  428                         reg = <0x13890000 0x100>;
  429                         interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
  430                         #address-cells = <1>;
  431                         #size-cells = <0>;
  432                         pinctrl-names = "default";
  433                         pinctrl-0 = <&i2c6_bus>;
  434                         clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>;
  435                         clock-names = "i2c";
  436                         status = "disabled";
  437                 };
  438 
  439                 i2c_7: i2c@11cd0000 {
  440                         compatible = "samsung,s3c2440-i2c";
  441                         reg = <0x11cd0000 0x100>;
  442                         interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
  443                         #address-cells = <1>;
  444                         #size-cells = <0>;
  445                         pinctrl-names = "default";
  446                         pinctrl-0 = <&i2c7_bus>;
  447                         clocks = <&cmu_peri CLK_GOUT_I2C7_PCLK>;
  448                         clock-names = "i2c";
  449                         status = "disabled";
  450                 };
  451         };
  452 };
  453 
  454 #include "exynos7885-pinctrl.dtsi"
  455 #include "arm/exynos-syscon-restart.dtsi"
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/exynos/exynos7885.dtsi

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sys/contrib/device-tree/src/arm64/exynos/exynos7885.dtsi
