fsl-ls1043a-rdb.dts

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
    4  *
    5  * Copyright 2014-2015 Freescale Semiconductor, Inc.
    6  * Copyright 2018 NXP
    7  *
    8  * Mingkai Hu <Mingkai.hu@freescale.com>
    9  */
   10 
   11 /dts-v1/;
   12 #include "fsl-ls1043a.dtsi"
   13 
   14 / {
   15         model = "LS1043A RDB Board";
   16         compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
   17 
   18         aliases {
   19                 serial0 = &duart0;
   20                 serial1 = &duart1;
   21                 serial2 = &duart2;
   22                 serial3 = &duart3;
   23         };
   24 
   25         chosen {
   26                 stdout-path = "serial0:115200n8";
   27         };
   28 };
   29 
   30 &i2c0 {
   31         status = "okay";
   32         ina220@40 {
   33                 compatible = "ti,ina220";
   34                 reg = <0x40>;
   35                 shunt-resistor = <1000>;
   36         };
   37         adt7461a@4c {
   38                 compatible = "adi,adt7461";
   39                 reg = <0x4c>;
   40         };
   41         eeprom@52 {
   42                 compatible = "atmel,24c512";
   43                 reg = <0x52>;
   44         };
   45         eeprom@53 {
   46                 compatible = "atmel,24c512";
   47                 reg = <0x53>;
   48         };
   49         rtc@68 {
   50                 compatible = "pericom,pt7c4338";
   51                 reg = <0x68>;
   52         };
   53 };
   54 
   55 &ifc {
   56         status = "okay";
   57         #address-cells = <2>;
   58         #size-cells = <1>;
   59         /* NOR, NAND Flashes and FPGA on board */
   60         ranges = <0x0 0x0 0x0 0x60000000 0x08000000
   61                   0x1 0x0 0x0 0x7e800000 0x00010000
   62                   0x2 0x0 0x0 0x7fb00000 0x00000100>;
   63 
   64                 nor@0,0 {
   65                         compatible = "cfi-flash";
   66                         #address-cells = <1>;
   67                         #size-cells = <1>;
   68                         reg = <0x0 0x0 0x8000000>;
   69                         big-endian;
   70                         bank-width = <2>;
   71                         device-width = <1>;
   72                 };
   73 
   74                 nand@1,0 {
   75                         compatible = "fsl,ifc-nand";
   76                         #address-cells = <1>;
   77                         #size-cells = <1>;
   78                         reg = <0x1 0x0 0x10000>;
   79                 };
   80 
   81                 cpld: board-control@2,0 {
   82                         compatible = "fsl,ls1043ardb-cpld";
   83                         reg = <0x2 0x0 0x0000100>;
   84                 };
   85 };
   86 
   87 &dspi0 {
   88         bus-num = <0>;
   89         status = "okay";
   90 
   91         flash@0 {
   92                 #address-cells = <1>;
   93                 #size-cells = <1>;
   94                 compatible = "n25q128a13", "jedec,spi-nor";  /* 16MB */
   95                 reg = <0>;
   96                 spi-max-frequency = <1000000>; /* input clock */
   97                 fsl,spi-cs-sck-delay = <100>;
   98                 fsl,spi-sck-cs-delay = <100>;
   99         };
  100 
  101         slic@2 {
  102                 compatible = "maxim,ds26522";
  103                 reg = <2>;
  104                 spi-max-frequency = <2000000>;
  105                 fsl,spi-cs-sck-delay = <100>;
  106                 fsl,spi-sck-cs-delay = <50>;
  107         };
  108 
  109         slic@3 {
  110                 compatible = "maxim,ds26522";
  111                 reg = <3>;
  112                 spi-max-frequency = <2000000>;
  113                 fsl,spi-cs-sck-delay = <100>;
  114                 fsl,spi-sck-cs-delay = <50>;
  115         };
  116 };
  117 
  118 &duart0 {
  119         status = "okay";
  120 };
  121 
  122 &duart1 {
  123         status = "okay";
  124 };
  125 
  126 #include "fsl-ls1043-post.dtsi"
  127 
  128 &fman0 {
  129         ethernet@e0000 {
  130                 phy-handle = <&qsgmii_phy1>;
  131                 phy-connection-type = "qsgmii";
  132         };
  133 
  134         ethernet@e2000 {
  135                 phy-handle = <&qsgmii_phy2>;
  136                 phy-connection-type = "qsgmii";
  137         };
  138 
  139         ethernet@e4000 {
  140                 phy-handle = <&rgmii_phy1>;
  141                 phy-connection-type = "rgmii-id";
  142         };
  143 
  144         ethernet@e6000 {
  145                 phy-handle = <&rgmii_phy2>;
  146                 phy-connection-type = "rgmii-id";
  147         };
  148 
  149         ethernet@e8000 {
  150                 phy-handle = <&qsgmii_phy3>;
  151                 phy-connection-type = "qsgmii";
  152         };
  153 
  154         ethernet@ea000 {
  155                 phy-handle = <&qsgmii_phy4>;
  156                 phy-connection-type = "qsgmii";
  157         };
  158 
  159         ethernet@f0000 { /* 10GEC1 */
  160                 phy-handle = <&aqr105_phy>;
  161                 phy-connection-type = "xgmii";
  162         };
  163 
  164         mdio@fc000 {
  165                 rgmii_phy1: ethernet-phy@1 {
  166                         reg = <0x1>;
  167                 };
  168 
  169                 rgmii_phy2: ethernet-phy@2 {
  170                         reg = <0x2>;
  171                 };
  172 
  173                 qsgmii_phy1: ethernet-phy@4 {
  174                         reg = <0x4>;
  175                 };
  176 
  177                 qsgmii_phy2: ethernet-phy@5 {
  178                         reg = <0x5>;
  179                 };
  180 
  181                 qsgmii_phy3: ethernet-phy@6 {
  182                         reg = <0x6>;
  183                 };
  184 
  185                 qsgmii_phy4: ethernet-phy@7 {
  186                         reg = <0x7>;
  187                 };
  188         };
  189 
  190         mdio@fd000 {
  191                 aqr105_phy: ethernet-phy@1 {
  192                         compatible = "ethernet-phy-ieee802.3-c45";
  193                         interrupts = <0 132 4>;
  194                         reg = <0x1>;
  195                 };
  196         };
  197 };
  198 
  199 &uqe {
  200         ucc_hdlc: ucc@2000 {
  201                 compatible = "fsl,ucc-hdlc";
  202                 rx-clock-name = "clk8";
  203                 tx-clock-name = "clk9";
  204                 fsl,rx-sync-clock = "rsync_pin";
  205                 fsl,tx-sync-clock = "tsync_pin";
  206                 fsl,tx-timeslot-mask = <0xfffffffe>;
  207                 fsl,rx-timeslot-mask = <0xfffffffe>;
  208                 fsl,tdm-framer-type = "e1";
  209                 fsl,tdm-id = <0>;
  210                 fsl,siram-entry-id = <0>;
  211                 fsl,tdm-interface;
  212         };
  213 };
  214 
  215 &usb0 {
  216         status = "okay";
  217 };
  218 
  219 &usb1 {
  220         status = "okay";
  221 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/freescale/fsl-ls1043a-rdb.dts

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sys/contrib/device-tree/src/arm64/freescale/fsl-ls1043a-rdb.dts