Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mm-icore-mx8mm.dtsi
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (c) 2018 NXP 4 * Copyright (c) 2019 Engicam srl 5 * Copyright (c) 2020 Amarula Solutons(India) 6 */ 7 8 / { 9 compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; 10 }; 11 12 &A53_0 { 13 cpu-supply = <®_buck4>; 14 }; 15 16 &A53_1 { 17 cpu-supply = <®_buck4>; 18 }; 19 20 &A53_2 { 21 cpu-supply = <®_buck4>; 22 }; 23 24 &A53_3 { 25 cpu-supply = <®_buck4>; 26 }; 27 28 &fec1 { 29 pinctrl-names = "default"; 30 pinctrl-0 = <&pinctrl_fec1>; 31 phy-mode = "rgmii-id"; 32 phy-handle = <ðphy>; 33 34 mdio { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 ethphy: ethernet-phy@3 { 39 compatible = "ethernet-phy-ieee802.3-c22"; 40 reg = <3>; 41 reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>; 42 reset-assert-us = <10000>; 43 }; 44 }; 45 }; 46 47 &i2c1 { 48 clock-frequency = <400000>; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_i2c1>; 51 status = "okay"; 52 53 pmic@8 { 54 compatible = "nxp,pf8121a"; 55 reg = <0x08>; 56 57 regulators { 58 reg_ldo1: ldo1 { 59 regulator-min-microvolt = <1500000>; 60 regulator-max-microvolt = <5000000>; 61 regulator-always-on; 62 regulator-boot-on; 63 }; 64 65 reg_ldo2: ldo2 { 66 regulator-min-microvolt = <1500000>; 67 regulator-max-microvolt = <5000000>; 68 regulator-always-on; 69 regulator-boot-on; 70 }; 71 72 reg_ldo3: ldo3 { 73 regulator-min-microvolt = <1500000>; 74 regulator-max-microvolt = <5000000>; 75 regulator-always-on; 76 regulator-boot-on; 77 }; 78 79 reg_ldo4: ldo4 { 80 regulator-min-microvolt = <1500000>; 81 regulator-max-microvolt = <5000000>; 82 regulator-always-on; 83 regulator-boot-on; 84 }; 85 86 reg_buck1: buck1 { 87 regulator-min-microvolt = <400000>; 88 regulator-max-microvolt = <1800000>; 89 regulator-always-on; 90 regulator-boot-on; 91 }; 92 93 reg_buck2: buck2 { 94 regulator-min-microvolt = <400000>; 95 regulator-max-microvolt = <1800000>; 96 regulator-always-on; 97 regulator-boot-on; 98 }; 99 100 reg_buck3: buck3 { 101 regulator-min-microvolt = <400000>; 102 regulator-max-microvolt = <1800000>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 reg_buck4: buck4 { 108 regulator-min-microvolt = <400000>; 109 regulator-max-microvolt = <1800000>; 110 regulator-always-on; 111 regulator-boot-on; 112 }; 113 114 reg_buck5: buck5 { 115 regulator-min-microvolt = <400000>; 116 regulator-max-microvolt = <1800000>; 117 regulator-always-on; 118 regulator-boot-on; 119 }; 120 121 reg_buck6: buck6 { 122 regulator-min-microvolt = <400000>; 123 regulator-max-microvolt = <1800000>; 124 regulator-always-on; 125 regulator-boot-on; 126 }; 127 128 reg_buck7: buck7 { 129 regulator-min-microvolt = <3300000>; 130 regulator-max-microvolt = <3300000>; 131 regulator-always-on; 132 regulator-boot-on; 133 }; 134 135 reg_vsnvs: vsnvs { 136 regulator-min-microvolt = <1800000>; 137 regulator-max-microvolt = <3300000>; 138 regulator-always-on; 139 regulator-boot-on; 140 }; 141 }; 142 }; 143 }; 144 145 &iomuxc { 146 pinctrl_fec1: fec1grp { 147 fsl,pins = < 148 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 149 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 150 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 151 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 152 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 153 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 154 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 155 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 156 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 157 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 158 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 159 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 160 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 161 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 162 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 163 >; 164 }; 165 166 pinctrl_i2c1: i2c1grp { 167 fsl,pins = < 168 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 169 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 170 >; 171 }; 172 173 pinctrl_usdhc3: usdhc3grp { 174 fsl,pins = < 175 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 176 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 177 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 178 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 179 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 180 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 181 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 182 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 183 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 184 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 185 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 186 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 187 >; 188 }; 189 190 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 191 fsl,pins = < 192 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 193 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 194 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 195 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 196 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 197 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 198 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 199 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 200 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 201 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 202 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 203 >; 204 }; 205 206 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 207 fsl,pins = < 208 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 209 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 210 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 211 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 212 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 213 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 214 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 215 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 216 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 217 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 218 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 219 >; 220 }; 221 }; 222 223 /* eMMC */ 224 &usdhc3 { 225 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 226 pinctrl-0 = <&pinctrl_usdhc3>; 227 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 228 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 229 bus-width = <8>; 230 non-removable; 231 status = "okay"; 232 };
Cache object: 49963a796250a59fab1ac92da7d700e2
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]