Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 PHYTEC Messtechnik GmbH 4 * Author: Teresa Remmet <t.remmet@phytec.de> 5 */ 6 7 /dts-v1/; 8 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 #include "imx8mm-phycore-som.dtsi" 13 14 / { 15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK"; 16 compatible = "phytec,imx8mm-phyboard-polis-rdk", 17 "phytec,imx8mm-phycore-som", "fsl,imx8mm"; 18 19 chosen { 20 stdout-path = &uart3; 21 }; 22 23 bt_osc_32k: bt-lp-clock { 24 compatible = "fixed-clock"; 25 clock-frequency = <32768>; 26 clock-output-names = "bt_osc_32k"; 27 #clock-cells = <0>; 28 }; 29 30 can_osc_40m: can-clock { 31 compatible = "fixed-clock"; 32 clock-frequency = <40000000>; 33 clock-output-names = "can_osc_40m"; 34 #clock-cells = <0>; 35 }; 36 37 fan { 38 compatible = "gpio-fan"; 39 gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; 40 gpio-fan,speed-map = <0 0 41 13000 1>; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_fan>; 44 #cooling-cells = <2>; 45 }; 46 47 leds { 48 compatible = "gpio-leds"; 49 pinctrl-names = "default"; 50 pinctrl-0 = <&pinctrl_leds>; 51 52 led-0 { 53 color = <LED_COLOR_ID_RED>; 54 function = LED_FUNCTION_DISK; 55 gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; 56 linux,default-trigger = "mmc2"; 57 }; 58 59 led-1 { 60 color = <LED_COLOR_ID_BLUE>; 61 function = LED_FUNCTION_DISK; 62 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 63 linux,default-trigger = "mmc1"; 64 }; 65 66 led-2 { 67 color = <LED_COLOR_ID_GREEN>; 68 function = LED_FUNCTION_CPU; 69 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; 70 linux,default-trigger = "heartbeat"; 71 }; 72 }; 73 74 usdhc1_pwrseq: pwr-seq { 75 compatible = "mmc-pwrseq-simple"; 76 post-power-on-delay-ms = <100>; 77 power-off-delay-us = <60>; 78 reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; 79 }; 80 81 reg_can_en: regulator-can-en { 82 compatible = "regulator-fixed"; 83 gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_can_en>; 86 regulator-max-microvolt = <3300000>; 87 regulator-min-microvolt = <3300000>; 88 regulator-name = "CAN_EN"; 89 startup-delay-us = <20>; 90 }; 91 92 reg_usb_otg1_vbus: regulator-usb-otg1 { 93 compatible = "regulator-fixed"; 94 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 95 enable-active-high; 96 pinctrl-names = "default"; 97 pinctrl-0 = <&pinctrl_usbotg1pwrgrp>; 98 regulator-name = "usb_otg1_vbus"; 99 regulator-max-microvolt = <5000000>; 100 regulator-min-microvolt = <5000000>; 101 }; 102 103 reg_usdhc2_vmmc: regulator-usdhc2 { 104 compatible = "regulator-fixed"; 105 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 106 enable-active-high; 107 off-on-delay-us = <20000>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 110 regulator-max-microvolt = <3300000>; 111 regulator-min-microvolt = <3300000>; 112 regulator-name = "VSD_3V3"; 113 }; 114 115 reg_vcc_3v3: regulator-vcc-3v3 { 116 compatible = "regulator-fixed"; 117 regulator-max-microvolt = <3300000>; 118 regulator-min-microvolt = <3300000>; 119 regulator-name = "VCC_3V3"; 120 }; 121 }; 122 123 /* SPI - CAN MCP251XFD */ 124 &ecspi1 { 125 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_ecspi1>; 128 status = "okay"; 129 130 can0: can@0 { 131 compatible = "microchip,mcp251xfd"; 132 clocks = <&can_osc_40m>; 133 interrupt-parent = <&gpio1>; 134 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_can_int>; 137 reg = <0>; 138 spi-max-frequency = <20000000>; 139 xceiver-supply = <®_can_en>; 140 }; 141 }; 142 143 &gpio1 { 144 gpio-line-names = "nINT_ETHPHY", "LED_RED", "WDOG_INT", "X_RTC_INT", 145 "", "", "", "RESET_ETHPHY", 146 "CAN_nINT", "CAN_EN", "nENABLE_FLATLINK", "", 147 "USB_OTG_VBUS_EN", "", "LED_GREEN", "LED_BLUE"; 148 }; 149 150 &gpio2 { 151 gpio-line-names = "", "", "", "", 152 "", "", "BT_REG_ON", "WL_REG_ON", 153 "BT_DEV_WAKE", "BT_HOST_WAKE", "", "", 154 "X_SD2_CD_B", "", "", "", 155 "", "", "", "SD2_RESET_B"; 156 }; 157 158 &gpio4 { 159 gpio-line-names = "", "", "", "", 160 "", "", "", "", 161 "FAN", "miniPCIe_nPERST", "", "", 162 "COEX1", "COEX2"; 163 }; 164 165 &gpio5 { 166 gpio-line-names = "", "", "", "", 167 "", "", "", "", 168 "", "ECSPI1_SS0"; 169 }; 170 171 /* PCIe */ 172 &pcie0 { 173 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 174 <&clk IMX8MM_CLK_PCIE1_CTRL>; 175 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 176 <&clk IMX8MM_SYS_PLL2_250M>; 177 assigned-clock-rates = <10000000>, <250000000>; 178 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 179 <&clk IMX8MM_CLK_PCIE1_PHY>; 180 clock-names = "pcie", "pcie_aux", "pcie_bus"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_pcie>; 183 reset-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; 184 status = "okay"; 185 }; 186 187 &pcie_phy { 188 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 189 fsl,clkreq-unsupported; 190 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 191 fsl,tx-deemph-gen1 = <0x2d>; 192 fsl,tx-deemph-gen2 = <0xf>; 193 status = "okay"; 194 }; 195 196 &rv3028 { 197 trickle-resistor-ohms = <3000>; 198 }; 199 200 &snvs_pwrkey { 201 status = "okay"; 202 }; 203 204 /* UART - RS232/RS485 */ 205 &uart1 { 206 assigned-clocks = <&clk IMX8MM_CLK_UART1>; 207 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_uart1>; 210 uart-has-rtscts; 211 status = "okay"; 212 }; 213 214 /* UART - Sterling-LWB Bluetooth */ 215 &uart2 { 216 assigned-clocks = <&clk IMX8MM_CLK_UART2>; 217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 218 fsl,dte-mode; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_uart2_bt>; 221 uart-has-rtscts; 222 status = "okay"; 223 224 bluetooth { 225 compatible = "brcm,bcm43438-bt"; 226 clocks = <&bt_osc_32k>; 227 clock-names = "lpo"; 228 device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 229 interrupt-names = "host-wakeup"; 230 interrupt-parent = <&gpio2>; 231 interrupts = <9 IRQ_TYPE_EDGE_BOTH>; 232 max-speed = <2000000>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_bt>; 235 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 236 vddio-supply = <®_vcc_3v3>; 237 }; 238 }; 239 240 /* UART - console */ 241 &uart3 { 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_uart3>; 244 status = "okay"; 245 }; 246 247 /* USB */ 248 &usbotg1 { 249 adp-disable; 250 dr_mode = "otg"; 251 over-current-active-low; 252 samsung,picophy-pre-emp-curr-control = <3>; 253 samsung,picophy-dc-vol-level-adjust = <7>; 254 srp-disable; 255 vbus-supply = <®_usb_otg1_vbus>; 256 status = "okay"; 257 }; 258 259 &usbotg2 { 260 disable-over-current; 261 dr_mode = "host"; 262 samsung,picophy-pre-emp-curr-control = <3>; 263 samsung,picophy-dc-vol-level-adjust = <7>; 264 status = "okay"; 265 }; 266 267 /* SDIO - Sterling-LWB Wifi */ 268 &usdhc1 { 269 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; 270 assigned-clock-rates = <200000000>; 271 bus-width = <4>; 272 mmc-pwrseq = <&usdhc1_pwrseq>; 273 non-removable; 274 no-1-8-v; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wlan>; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 status = "okay"; 280 281 brcmf: wifi@1 { 282 compatible = "brcm,bcm4329-fmac"; 283 reg = <1>; 284 }; 285 }; 286 287 /* SD-Card */ 288 &usdhc2 { 289 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; 290 assigned-clock-rates = <200000000>; 291 bus-width = <4>; 292 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 293 disable-wp; 294 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 295 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 296 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 297 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 298 vmmc-supply = <®_usdhc2_vmmc>; 299 vqmmc-supply = <®_nvcc_sd2>; 300 status = "okay"; 301 }; 302 303 &iomuxc { 304 pinctrl_bt: btgrp { 305 fsl,pins = < 306 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 307 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 308 MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 309 >; 310 }; 311 312 pinctrl_can_en: can-engrp { 313 fsl,pins = < 314 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 315 >; 316 }; 317 318 pinctrl_can_int: can-intgrp { 319 fsl,pins = < 320 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 321 >; 322 }; 323 324 pinctrl_ecspi1: ecspi1grp { 325 fsl,pins = < 326 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x80 327 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x80 328 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x80 329 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 330 >; 331 }; 332 333 pinctrl_fan: fan0grp { 334 fsl,pins = < 335 MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 336 >; 337 }; 338 339 pinctrl_leds: leds1grp { 340 fsl,pins = < 341 MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 342 MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16 343 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 344 >; 345 }; 346 347 pinctrl_pcie: pciegrp { 348 fsl,pins = < 349 MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x00 350 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 351 MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x12 352 >; 353 }; 354 355 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 356 fsl,pins = < 357 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 358 >; 359 }; 360 361 pinctrl_uart1: uart1grp { 362 fsl,pins = < 363 MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 364 MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x00 365 MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x00 366 MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x00 367 >; 368 }; 369 370 pinctrl_uart2_bt: uart2btgrp { 371 fsl,pins = < 372 MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x00 373 MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x00 374 MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x00 375 MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x00 376 >; 377 }; 378 379 pinctrl_uart3: uart3grp { 380 fsl,pins = < 381 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 382 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 383 >; 384 }; 385 386 pinctrl_usbotg1pwrgrp: usbotg1pwrgrp { 387 fsl,pins = < 388 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 389 >; 390 }; 391 392 pinctrl_usdhc1: usdhc1grp { 393 fsl,pins = < 394 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 395 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 396 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 397 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 398 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 399 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 400 >; 401 }; 402 403 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 404 fsl,pins = < 405 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 406 >; 407 }; 408 409 pinctrl_usdhc2: usdhc2grp { 410 fsl,pins = < 411 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 412 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 413 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 414 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 415 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 416 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 417 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 418 >; 419 }; 420 421 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 422 fsl,pins = < 423 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 424 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 425 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 426 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 427 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 428 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 429 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 430 >; 431 }; 432 433 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 434 fsl,pins = < 435 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 436 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 437 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 438 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 439 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 440 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 441 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 442 >; 443 }; 444 445 pinctrl_wlan: wlangrp { 446 fsl,pins = < 447 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00 448 >; 449 }; 450 };
Cache object: 14c237fe3aba317f801b33742efab55f
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