Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mm-var-som-symphony.dts
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> 4 */ 5 6 /dts-v1/; 7 8 #include "imx8mm-var-som.dtsi" 9 10 / { 11 model = "Variscite VAR-SOM-MX8MM Symphony evaluation board"; 12 compatible = "variscite,var-som-mx8mm-symphony", "variscite,var-som-mx8mm", "fsl,imx8mm"; 13 14 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 15 compatible = "regulator-fixed"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 18 regulator-name = "VSD_3V3"; 19 regulator-min-microvolt = <3300000>; 20 regulator-max-microvolt = <3300000>; 21 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 22 enable-active-high; 23 }; 24 25 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 26 compatible = "regulator-fixed"; 27 pinctrl-names = "default"; 28 pinctrl-0 = <&pinctrl_reg_usb_otg2_vbus>; 29 regulator-name = "usb_otg2_vbus"; 30 regulator-min-microvolt = <5000000>; 31 regulator-max-microvolt = <5000000>; 32 gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>; 33 enable-active-high; 34 }; 35 36 gpio-keys { 37 compatible = "gpio-keys"; 38 39 key-back { 40 label = "Back"; 41 gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; 42 linux,code = <KEY_BACK>; 43 }; 44 45 key-home { 46 label = "Home"; 47 gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; 48 linux,code = <KEY_HOME>; 49 }; 50 51 key-menu { 52 label = "Menu"; 53 gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; 54 linux,code = <KEY_MENU>; 55 }; 56 }; 57 58 leds { 59 compatible = "gpio-leds"; 60 61 led { 62 label = "Heartbeat"; 63 gpios = <&pca9534 0 GPIO_ACTIVE_LOW>; 64 linux,default-trigger = "heartbeat"; 65 }; 66 }; 67 }; 68 69 ðphy { 70 reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; 71 }; 72 73 &i2c2 { 74 clock-frequency = <400000>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_i2c2>; 77 status = "okay"; 78 79 pca9534: gpio@20 { 80 compatible = "nxp,pca9534"; 81 reg = <0x20>; 82 gpio-controller; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_pca9534>; 85 interrupt-parent = <&gpio1>; 86 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 87 #gpio-cells = <2>; 88 wakeup-source; 89 90 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ 91 usb3-sata-sel-hog { 92 gpio-hog; 93 gpios = <4 GPIO_ACTIVE_HIGH>; 94 output-low; 95 line-name = "usb3_sata_sel"; 96 }; 97 98 som-vselect-hog { 99 gpio-hog; 100 gpios = <6 GPIO_ACTIVE_HIGH>; 101 output-low; 102 line-name = "som_vselect"; 103 }; 104 105 enet-sel-hog { 106 gpio-hog; 107 gpios = <7 GPIO_ACTIVE_HIGH>; 108 output-low; 109 line-name = "enet_sel"; 110 }; 111 }; 112 113 extcon_usbotg1: typec@3d { 114 compatible = "nxp,ptn5150"; 115 reg = <0x3d>; 116 interrupt-parent = <&gpio1>; 117 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_ptn5150>; 120 status = "okay"; 121 }; 122 }; 123 124 &i2c3 { 125 /* Capacitive touch controller */ 126 ft5x06_ts: touchscreen@38 { 127 compatible = "edt,edt-ft5406"; 128 reg = <0x38>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_captouch>; 131 interrupt-parent = <&gpio5>; 132 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 133 134 touchscreen-size-x = <800>; 135 touchscreen-size-y = <480>; 136 touchscreen-inverted-x; 137 touchscreen-inverted-y; 138 }; 139 140 rtc@68 { 141 compatible = "dallas,ds1337"; 142 reg = <0x68>; 143 }; 144 }; 145 146 /* Header */ 147 &uart1 { 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_uart1>; 150 status = "okay"; 151 }; 152 153 /* Header */ 154 &uart3 { 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_uart3>; 157 status = "okay"; 158 }; 159 160 &usbotg1 { 161 disable-over-current; 162 extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; 163 }; 164 165 &usbotg2 { 166 dr_mode = "host"; 167 vbus-supply = <®_usb_otg2_vbus>; 168 srp-disable; 169 hnp-disable; 170 adp-disable; 171 disable-over-current; 172 /delete-property/ usb-role-switch; 173 /* 174 * FIXME: having USB2 enabled hangs the boot just after: 175 * [ 1.943365] ci_hdrc ci_hdrc.1: EHCI Host Controller 176 * [ 1.948287] ci_hdrc ci_hdrc.1: new USB bus registered, assigned bus number 1 177 * [ 1.971006] ci_hdrc ci_hdrc.1: USB 2.0 started, EHCI 1.00 178 * [ 1.977203] hub 1-0:1.0: USB hub found 179 * [ 1.980987] hub 1-0:1.0: 1 port detected 180 */ 181 status = "disabled"; 182 }; 183 184 &pinctrl_fec1 { 185 fsl,pins = < 186 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 187 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 188 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 189 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 190 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 191 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 192 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 193 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 194 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 195 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 196 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 197 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 198 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 199 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 200 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */ 201 >; 202 }; 203 204 &iomuxc { 205 pinctrl_captouch: captouchgrp { 206 fsl,pins = < 207 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x16 208 >; 209 }; 210 211 pinctrl_i2c2: i2c2grp { 212 fsl,pins = < 213 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 214 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 215 >; 216 }; 217 218 pinctrl_pca9534: pca9534grp { 219 fsl,pins = < 220 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 221 >; 222 }; 223 224 pinctrl_ptn5150: ptn5150grp { 225 fsl,pins = < 226 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 227 >; 228 }; 229 230 pinctrl_reg_usb_otg2_vbus: regusbotg2vbusgrp { 231 fsl,pins = < 232 MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x16 233 >; 234 }; 235 236 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 237 fsl,pins = < 238 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 239 >; 240 }; 241 242 pinctrl_uart1: uart1grp { 243 fsl,pins = < 244 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 245 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 246 >; 247 }; 248 249 pinctrl_uart3: uart3grp { 250 fsl,pins = < 251 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 252 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 253 >; 254 }; 255 };
Cache object: 8a7fc670e81baf841cc2dcbe8ae0b93d
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