Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw72xx.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright 2020 Gateworks Corporation 4 */ 5 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 9 10 / { 11 aliases { 12 ethernet1 = ð1; 13 usb0 = &usbotg1; 14 usb1 = &usbotg2; 15 }; 16 17 led-controller { 18 compatible = "gpio-leds"; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&pinctrl_gpio_leds>; 21 22 led-0 { 23 function = LED_FUNCTION_STATUS; 24 color = <LED_COLOR_ID_GREEN>; 25 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; 26 default-state = "on"; 27 linux,default-trigger = "heartbeat"; 28 }; 29 30 led-1 { 31 function = LED_FUNCTION_STATUS; 32 color = <LED_COLOR_ID_RED>; 33 gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; 34 default-state = "off"; 35 }; 36 }; 37 38 pcie0_refclk: pcie0-refclk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <100000000>; 42 }; 43 44 pps { 45 compatible = "pps-gpio"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_pps>; 48 gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; 49 status = "okay"; 50 }; 51 52 reg_3p3v: regulator-3p3v { 53 compatible = "regulator-fixed"; 54 regulator-name = "3P3V"; 55 regulator-min-microvolt = <3300000>; 56 regulator-max-microvolt = <3300000>; 57 regulator-always-on; 58 }; 59 60 reg_usb_otg1_vbus: regulator-usb-otg1 { 61 pinctrl-names = "default"; 62 pinctrl-0 = <&pinctrl_reg_usb1_en>; 63 compatible = "regulator-fixed"; 64 regulator-name = "usb_otg1_vbus"; 65 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 }; 70 71 reg_usb_otg2_vbus: regulator-usb-otg2 { 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_reg_usb2_en>; 74 compatible = "regulator-fixed"; 75 regulator-name = "usb_otg2_vbus"; 76 gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; 77 enable-active-high; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 }; 81 }; 82 83 /* off-board header */ 84 &ecspi2 { 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_spi2>; 87 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 88 status = "okay"; 89 }; 90 91 &gpio1 { 92 gpio-line-names = "rs485_term", "mipi_gpio4", "", "", 93 "", "", "pci_usb_sel", "dio0", 94 "", "dio1", "", "", "", "", "", "", 95 "", "", "", "", "", "", "", "", 96 "", "", "", "", "", "", "", ""; 97 }; 98 99 &gpio4 { 100 gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2", 101 "mipi_gpio1", "", "", "pci_wdis#", 102 "", "", "", "", "", "", "", "", 103 "", "", "", "", "", "", "", "", 104 "", "", "", "", "", "", "", ""; 105 }; 106 107 &i2c2 { 108 clock-frequency = <400000>; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_i2c2>; 111 status = "okay"; 112 113 accelerometer@19 { 114 pinctrl-names = "default"; 115 pinctrl-0 = <&pinctrl_accel>; 116 compatible = "st,lis2de12"; 117 reg = <0x19>; 118 st,drdy-int-pin = <1>; 119 interrupt-parent = <&gpio4>; 120 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 121 interrupt-names = "INT1"; 122 }; 123 }; 124 125 /* off-board header */ 126 &i2c3 { 127 clock-frequency = <400000>; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&pinctrl_i2c3>; 130 status = "okay"; 131 }; 132 133 &pcie_phy { 134 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 135 fsl,clkreq-unsupported; 136 clocks = <&pcie0_refclk>; 137 clock-names = "ref"; 138 status = "okay"; 139 }; 140 141 &pcie0 { 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_pcie0>; 144 reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; 145 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 146 <&pcie0_refclk>; 147 clock-names = "pcie", "pcie_aux", "pcie_bus"; 148 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 149 <&clk IMX8MM_CLK_PCIE1_CTRL>; 150 assigned-clock-rates = <10000000>, <250000000>; 151 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 152 <&clk IMX8MM_SYS_PLL2_250M>; 153 status = "okay"; 154 155 pcie@0,0 { 156 reg = <0x0000 0 0 0 0>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 160 pcie@1,0 { 161 reg = <0x0000 0 0 0 0>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 pcie@2,3 { 166 reg = <0x1800 0 0 0 0>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 eth1: pcie@5,0 { 171 reg = <0x0000 0 0 0 0>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 175 local-mac-address = [00 00 00 00 00 00]; 176 }; 177 }; 178 }; 179 }; 180 }; 181 182 /* off-board header */ 183 &sai3 { 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_sai3>; 186 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 187 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 188 assigned-clock-rates = <24576000>; 189 status = "okay"; 190 }; 191 192 /* GPS */ 193 &uart1 { 194 pinctrl-names = "default"; 195 pinctrl-0 = <&pinctrl_uart1>; 196 status = "okay"; 197 }; 198 199 /* off-board header */ 200 &uart3 { 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_uart3>; 203 status = "okay"; 204 }; 205 206 /* RS232 */ 207 &uart4 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_uart4>; 210 status = "okay"; 211 }; 212 213 &usbotg1 { 214 dr_mode = "otg"; 215 over-current-active-low; 216 vbus-supply = <®_usb_otg1_vbus>; 217 status = "okay"; 218 }; 219 220 &usbotg2 { 221 dr_mode = "host"; 222 disable-over-current; 223 vbus-supply = <®_usb_otg2_vbus>; 224 status = "okay"; 225 }; 226 227 /* microSD */ 228 &usdhc2 { 229 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 230 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 231 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 232 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 233 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 234 bus-width = <4>; 235 vmmc-supply = <®_3p3v>; 236 status = "okay"; 237 }; 238 239 &iomuxc { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_hog>; 242 243 pinctrl_hog: hoggrp { 244 fsl,pins = < 245 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ 246 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ 247 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ 248 MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ 249 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ 250 MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000104 /* RS485_TERM */ 251 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x40000104 /* RS485 */ 252 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000104 /* RS485_HALF */ 253 >; 254 }; 255 256 pinctrl_accel: accelgrp { 257 fsl,pins = < 258 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 259 >; 260 }; 261 262 pinctrl_gpio_leds: gpioledgrp { 263 fsl,pins = < 264 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 265 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 266 >; 267 }; 268 269 pinctrl_i2c3: i2c3grp { 270 fsl,pins = < 271 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 272 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 273 >; 274 }; 275 276 pinctrl_pcie0: pcie0grp { 277 fsl,pins = < 278 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41 279 >; 280 }; 281 282 pinctrl_pps: ppsgrp { 283 fsl,pins = < 284 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 285 >; 286 }; 287 288 pinctrl_reg_usb1_en: regusb1grp { 289 fsl,pins = < 290 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 291 MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 292 >; 293 }; 294 295 pinctrl_reg_usb2_en: regusb2grp { 296 fsl,pins = < 297 MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x41 298 >; 299 }; 300 301 pinctrl_sai3: sai3grp { 302 fsl,pins = < 303 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 304 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 305 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 306 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 307 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 308 >; 309 }; 310 311 pinctrl_spi2: spi2grp { 312 fsl,pins = < 313 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 314 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 315 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 316 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 317 >; 318 }; 319 320 pinctrl_uart1: uart1grp { 321 fsl,pins = < 322 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 323 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 324 >; 325 }; 326 327 pinctrl_uart3: uart3grp { 328 fsl,pins = < 329 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 330 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 331 >; 332 }; 333 334 pinctrl_uart4: uart4grp { 335 fsl,pins = < 336 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 337 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 338 >; 339 }; 340 341 pinctrl_usdhc1: usdhc1grp { 342 fsl,pins = < 343 MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 344 MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 345 MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 346 MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 347 MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 348 MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 349 >; 350 }; 351 352 pinctrl_usdhc2: usdhc2grp { 353 fsl,pins = < 354 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 355 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 356 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 357 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 358 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 359 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 360 >; 361 }; 362 363 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 364 fsl,pins = < 365 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 366 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 367 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 368 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 369 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 370 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 371 >; 372 }; 373 374 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 375 fsl,pins = < 376 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 377 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 378 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 379 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 380 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 381 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 382 >; 383 }; 384 385 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 386 fsl,pins = < 387 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 388 MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x1d0 389 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 390 >; 391 }; 392 };
Cache object: 65b64cb012139701f86b9c8a17fc133c
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