Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm64/freescale/imx8mm-venice-gw7902.dts
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6 /dts-v1/; 7 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/linux-event-codes.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/net/ti-dp83867.h> 12 #include <dt-bindings/phy/phy-imx8-pcie.h> 13 14 #include "imx8mm.dtsi" 15 16 / { 17 model = "Gateworks Venice GW7902 i.MX8MM board"; 18 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm"; 19 20 aliases { 21 ethernet1 = ð1; 22 usb0 = &usbotg1; 23 usb1 = &usbotg2; 24 }; 25 26 chosen { 27 stdout-path = &uart2; 28 }; 29 30 memory@40000000 { 31 device_type = "memory"; 32 reg = <0x0 0x40000000 0 0x80000000>; 33 }; 34 35 can20m: can20m { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <20000000>; 39 clock-output-names = "can20m"; 40 }; 41 42 gpio-keys { 43 compatible = "gpio-keys"; 44 45 key-user-pb { 46 label = "user_pb"; 47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 48 linux,code = <BTN_0>; 49 }; 50 51 key-user-pb1x { 52 label = "user_pb1x"; 53 linux,code = <BTN_1>; 54 interrupt-parent = <&gsc>; 55 interrupts = <0>; 56 }; 57 58 key-erased { 59 label = "key_erased"; 60 linux,code = <BTN_2>; 61 interrupt-parent = <&gsc>; 62 interrupts = <1>; 63 }; 64 65 key-eeprom-wp { 66 label = "eeprom_wp"; 67 linux,code = <BTN_3>; 68 interrupt-parent = <&gsc>; 69 interrupts = <2>; 70 }; 71 72 key-tamper { 73 label = "tamper"; 74 linux,code = <BTN_4>; 75 interrupt-parent = <&gsc>; 76 interrupts = <5>; 77 }; 78 79 switch-hold { 80 label = "switch_hold"; 81 linux,code = <BTN_5>; 82 interrupt-parent = <&gsc>; 83 interrupts = <7>; 84 }; 85 }; 86 87 led-controller { 88 compatible = "gpio-leds"; 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_gpio_leds>; 91 92 led-0 { 93 function = LED_FUNCTION_STATUS; 94 color = <LED_COLOR_ID_GREEN>; 95 label = "panel1"; 96 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 97 default-state = "off"; 98 }; 99 100 led-1 { 101 function = LED_FUNCTION_STATUS; 102 color = <LED_COLOR_ID_GREEN>; 103 label = "panel2"; 104 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 105 default-state = "off"; 106 }; 107 108 led-2 { 109 function = LED_FUNCTION_STATUS; 110 color = <LED_COLOR_ID_GREEN>; 111 label = "panel3"; 112 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 113 default-state = "off"; 114 }; 115 116 led-3 { 117 function = LED_FUNCTION_STATUS; 118 color = <LED_COLOR_ID_GREEN>; 119 label = "panel4"; 120 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 121 default-state = "off"; 122 }; 123 124 led-4 { 125 function = LED_FUNCTION_STATUS; 126 color = <LED_COLOR_ID_GREEN>; 127 label = "panel5"; 128 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 129 default-state = "off"; 130 }; 131 }; 132 133 pcie0_refclk: pcie0-refclk { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <100000000>; 137 }; 138 139 pps { 140 compatible = "pps-gpio"; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_pps>; 143 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 144 status = "okay"; 145 }; 146 147 reg_3p3v: regulator-3p3v { 148 compatible = "regulator-fixed"; 149 regulator-name = "3P3V"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 regulator-always-on; 153 }; 154 155 reg_usb1_vbus: regulator-usb1 { 156 compatible = "regulator-fixed"; 157 pinctrl-names = "default"; 158 pinctrl-0 = <&pinctrl_reg_usb1>; 159 regulator-name = "usb_usb1_vbus"; 160 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; 161 enable-active-high; 162 regulator-min-microvolt = <5000000>; 163 regulator-max-microvolt = <5000000>; 164 }; 165 166 reg_wifi: regulator-wifi { 167 compatible = "regulator-fixed"; 168 pinctrl-names = "default"; 169 pinctrl-0 = <&pinctrl_reg_wl>; 170 regulator-name = "wifi"; 171 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 172 enable-active-high; 173 startup-delay-us = <100>; 174 regulator-min-microvolt = <3300000>; 175 regulator-max-microvolt = <3300000>; 176 }; 177 }; 178 179 &A53_0 { 180 cpu-supply = <&buck2>; 181 }; 182 183 &A53_1 { 184 cpu-supply = <&buck2>; 185 }; 186 187 &A53_2 { 188 cpu-supply = <&buck2>; 189 }; 190 191 &A53_3 { 192 cpu-supply = <&buck2>; 193 }; 194 195 &ddrc { 196 operating-points-v2 = <&ddrc_opp_table>; 197 198 ddrc_opp_table: opp-table { 199 compatible = "operating-points-v2"; 200 201 opp-25M { 202 opp-hz = /bits/ 64 <25000000>; 203 }; 204 205 opp-100M { 206 opp-hz = /bits/ 64 <100000000>; 207 }; 208 209 opp-750M { 210 opp-hz = /bits/ 64 <750000000>; 211 }; 212 }; 213 }; 214 215 &ecspi1 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_spi1>; 218 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 219 status = "okay"; 220 221 can@0 { 222 compatible = "microchip,mcp2515"; 223 reg = <0>; 224 clocks = <&can20m>; 225 oscillator-frequency = <20000000>; 226 interrupt-parent = <&gpio2>; 227 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 228 spi-max-frequency = <10000000>; 229 }; 230 }; 231 232 /* off-board header */ 233 &ecspi2 { 234 pinctrl-names = "default"; 235 pinctrl-0 = <&pinctrl_spi2>; 236 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 237 status = "okay"; 238 }; 239 240 &fec1 { 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_fec1>; 243 phy-mode = "rgmii-id"; 244 phy-handle = <ðphy0>; 245 local-mac-address = [00 00 00 00 00 00]; 246 status = "okay"; 247 248 mdio { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 252 ethphy0: ethernet-phy@0 { 253 compatible = "ethernet-phy-ieee802.3-c22"; 254 reg = <0>; 255 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 256 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 257 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 258 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 259 }; 260 }; 261 }; 262 263 &gpio1 { 264 gpio-line-names = "", "", "", "", "", "", "", "", 265 "", "", "", "", "", "m2_reset", "", "m2_wdis#", 266 "", "", "", "", "", "", "", "", 267 "", "", "", "", "", "", "", ""; 268 }; 269 270 &gpio2 { 271 gpio-line-names = "", "", "", "", "", "", "", "", 272 "uart2_en#", "", "", "", "", "", "", "", 273 "", "", "", "", "", "", "", "", 274 "", "", "", "", "", "", "", ""; 275 }; 276 277 &gpio3 { 278 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", 279 "", "", "", "", "", "", "", "", 280 "", "", "", "", "", "", "", "", 281 "", "", "", "", "", "", "", ""; 282 }; 283 284 &gpio4 { 285 gpio-line-names = "", "", "", "", "", "", "", "", 286 "", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "", 287 "", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485", 288 "", "uart1_term", "uart1_half", "app_gpio2", 289 "mipi_gpio1", "", "", ""; 290 }; 291 292 &gpio5 { 293 gpio-line-names = "", "", "", "mipi_gpio4", 294 "mipi_gpio3", "mipi_gpio2", "", "", 295 "", "", "", "", "", "", "", "", 296 "", "", "", "", "", "", "", "", 297 "", "", "", "", "", "", "", ""; 298 }; 299 300 &i2c1 { 301 clock-frequency = <100000>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_i2c1>; 304 status = "okay"; 305 306 gsc: gsc@20 { 307 compatible = "gw,gsc"; 308 reg = <0x20>; 309 pinctrl-0 = <&pinctrl_gsc>; 310 interrupt-parent = <&gpio2>; 311 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 312 interrupt-controller; 313 #interrupt-cells = <1>; 314 315 adc { 316 compatible = "gw,gsc-adc"; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 channel@6 { 321 gw,mode = <0>; 322 reg = <0x06>; 323 label = "temp"; 324 }; 325 326 channel@8 { 327 gw,mode = <1>; 328 reg = <0x08>; 329 label = "vdd_bat"; 330 }; 331 332 channel@82 { 333 gw,mode = <2>; 334 reg = <0x82>; 335 label = "vin"; 336 gw,voltage-divider-ohms = <22100 1000>; 337 gw,voltage-offset-microvolt = <700000>; 338 }; 339 340 channel@84 { 341 gw,mode = <2>; 342 reg = <0x84>; 343 label = "vin_4p0"; 344 gw,voltage-divider-ohms = <10000 10000>; 345 }; 346 347 channel@86 { 348 gw,mode = <2>; 349 reg = <0x86>; 350 label = "vdd_3p3"; 351 gw,voltage-divider-ohms = <10000 10000>; 352 }; 353 354 channel@88 { 355 gw,mode = <2>; 356 reg = <0x88>; 357 label = "vdd_0p9"; 358 }; 359 360 channel@8c { 361 gw,mode = <2>; 362 reg = <0x8c>; 363 label = "vdd_soc"; 364 }; 365 366 channel@8e { 367 gw,mode = <2>; 368 reg = <0x8e>; 369 label = "vdd_arm"; 370 }; 371 372 channel@90 { 373 gw,mode = <2>; 374 reg = <0x90>; 375 label = "vdd_1p8"; 376 }; 377 378 channel@92 { 379 gw,mode = <2>; 380 reg = <0x92>; 381 label = "vdd_dram"; 382 }; 383 384 channel@98 { 385 gw,mode = <2>; 386 reg = <0x98>; 387 label = "vdd_1p0"; 388 }; 389 390 channel@9a { 391 gw,mode = <2>; 392 reg = <0x9a>; 393 label = "vdd_2p5"; 394 gw,voltage-divider-ohms = <10000 10000>; 395 }; 396 397 channel@9c { 398 gw,mode = <2>; 399 reg = <0x9c>; 400 label = "vdd_5p0"; 401 gw,voltage-divider-ohms = <10000 10000>; 402 }; 403 404 channel@a2 { 405 gw,mode = <2>; 406 reg = <0xa2>; 407 label = "vdd_gsc"; 408 gw,voltage-divider-ohms = <10000 10000>; 409 }; 410 }; 411 }; 412 413 gpio: gpio@23 { 414 compatible = "nxp,pca9555"; 415 reg = <0x23>; 416 gpio-controller; 417 #gpio-cells = <2>; 418 interrupt-parent = <&gsc>; 419 interrupts = <4>; 420 }; 421 422 pmic@4b { 423 compatible = "rohm,bd71847"; 424 reg = <0x4b>; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&pinctrl_pmic>; 427 interrupt-parent = <&gpio3>; 428 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 429 rohm,reset-snvs-powered; 430 #clock-cells = <0>; 431 clocks = <&osc_32k 0>; 432 clock-output-names = "clk-32k-out"; 433 434 regulators { 435 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 436 BUCK1 { 437 regulator-name = "buck1"; 438 regulator-min-microvolt = <700000>; 439 regulator-max-microvolt = <1300000>; 440 regulator-boot-on; 441 regulator-always-on; 442 regulator-ramp-delay = <1250>; 443 }; 444 445 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 446 buck2: BUCK2 { 447 regulator-name = "buck2"; 448 regulator-min-microvolt = <700000>; 449 regulator-max-microvolt = <1300000>; 450 regulator-boot-on; 451 regulator-always-on; 452 regulator-ramp-delay = <1250>; 453 rohm,dvs-run-voltage = <1000000>; 454 rohm,dvs-idle-voltage = <900000>; 455 }; 456 457 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 458 BUCK3 { 459 regulator-name = "buck3"; 460 regulator-min-microvolt = <700000>; 461 regulator-max-microvolt = <1350000>; 462 regulator-boot-on; 463 regulator-always-on; 464 }; 465 466 /* vdd_3p3 */ 467 BUCK4 { 468 regulator-name = "buck4"; 469 regulator-min-microvolt = <3000000>; 470 regulator-max-microvolt = <3300000>; 471 regulator-boot-on; 472 regulator-always-on; 473 }; 474 475 /* vdd_1p8 */ 476 BUCK5 { 477 regulator-name = "buck5"; 478 regulator-min-microvolt = <1605000>; 479 regulator-max-microvolt = <1995000>; 480 regulator-boot-on; 481 regulator-always-on; 482 }; 483 484 /* vdd_dram */ 485 BUCK6 { 486 regulator-name = "buck6"; 487 regulator-min-microvolt = <800000>; 488 regulator-max-microvolt = <1400000>; 489 regulator-boot-on; 490 regulator-always-on; 491 }; 492 493 /* nvcc_snvs_1p8 */ 494 LDO1 { 495 regulator-name = "ldo1"; 496 regulator-min-microvolt = <1600000>; 497 regulator-max-microvolt = <1900000>; 498 regulator-boot-on; 499 regulator-always-on; 500 }; 501 502 /* vdd_snvs_0p8 */ 503 LDO2 { 504 regulator-name = "ldo2"; 505 regulator-min-microvolt = <800000>; 506 regulator-max-microvolt = <900000>; 507 regulator-boot-on; 508 regulator-always-on; 509 }; 510 511 /* vdda_1p8 */ 512 LDO3 { 513 regulator-name = "ldo3"; 514 regulator-min-microvolt = <1800000>; 515 regulator-max-microvolt = <3300000>; 516 regulator-boot-on; 517 regulator-always-on; 518 }; 519 520 LDO4 { 521 regulator-name = "ldo4"; 522 regulator-min-microvolt = <900000>; 523 regulator-max-microvolt = <1800000>; 524 regulator-boot-on; 525 regulator-always-on; 526 }; 527 528 LDO6 { 529 regulator-name = "ldo6"; 530 regulator-min-microvolt = <900000>; 531 regulator-max-microvolt = <1800000>; 532 regulator-boot-on; 533 regulator-always-on; 534 }; 535 }; 536 }; 537 538 eeprom@50 { 539 compatible = "atmel,24c02"; 540 reg = <0x50>; 541 pagesize = <16>; 542 }; 543 544 eeprom@51 { 545 compatible = "atmel,24c02"; 546 reg = <0x51>; 547 pagesize = <16>; 548 }; 549 550 eeprom@52 { 551 compatible = "atmel,24c02"; 552 reg = <0x52>; 553 pagesize = <16>; 554 }; 555 556 eeprom@53 { 557 compatible = "atmel,24c02"; 558 reg = <0x53>; 559 pagesize = <16>; 560 }; 561 562 rtc@68 { 563 compatible = "dallas,ds1672"; 564 reg = <0x68>; 565 }; 566 }; 567 568 &i2c2 { 569 clock-frequency = <400000>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_i2c2>; 572 status = "okay"; 573 574 accelerometer@19 { 575 compatible = "st,lis2de12"; 576 pinctrl-names = "default"; 577 pinctrl-0 = <&pinctrl_accel>; 578 reg = <0x19>; 579 st,drdy-int-pin = <1>; 580 interrupt-parent = <&gpio1>; 581 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 582 interrupt-names = "INT1"; 583 }; 584 }; 585 586 /* off-board header */ 587 &i2c3 { 588 clock-frequency = <400000>; 589 pinctrl-names = "default"; 590 pinctrl-0 = <&pinctrl_i2c3>; 591 status = "okay"; 592 }; 593 594 /* off-board header */ 595 &i2c4 { 596 clock-frequency = <400000>; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&pinctrl_i2c4>; 599 status = "okay"; 600 }; 601 602 &pcie_phy { 603 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 604 fsl,clkreq-unsupported; 605 clocks = <&pcie0_refclk>; 606 clock-names = "ref"; 607 status = "okay"; 608 }; 609 610 &pcie0 { 611 pinctrl-names = "default"; 612 pinctrl-0 = <&pinctrl_pcie0>; 613 reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; 614 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, 615 <&pcie0_refclk>; 616 clock-names = "pcie", "pcie_aux", "pcie_bus"; 617 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, 618 <&clk IMX8MM_CLK_PCIE1_CTRL>; 619 assigned-clock-rates = <10000000>, <250000000>; 620 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, 621 <&clk IMX8MM_SYS_PLL2_250M>; 622 status = "okay"; 623 624 pcie@0,0 { 625 reg = <0x0000 0 0 0 0>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 629 eth1: pcie@1,0 { 630 reg = <0x0000 0 0 0 0>; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 634 local-mac-address = [00 00 00 00 00 00]; 635 }; 636 }; 637 }; 638 639 /* off-board header */ 640 &sai3 { 641 pinctrl-names = "default"; 642 pinctrl-0 = <&pinctrl_sai3>; 643 assigned-clocks = <&clk IMX8MM_CLK_SAI3>; 644 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 645 assigned-clock-rates = <24576000>; 646 status = "okay"; 647 }; 648 649 /* RS232/RS485/RS422 selectable */ 650 &uart1 { 651 pinctrl-names = "default"; 652 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 653 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; 654 cts-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 655 uart-has-rtscts; 656 status = "okay"; 657 }; 658 659 /* RS232 console */ 660 &uart2 { 661 pinctrl-names = "default"; 662 pinctrl-0 = <&pinctrl_uart2>; 663 status = "okay"; 664 }; 665 666 /* bluetooth HCI */ 667 &uart3 { 668 pinctrl-names = "default"; 669 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 670 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 671 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 672 uart-has-rtscts; 673 status = "okay"; 674 675 bluetooth { 676 compatible = "brcm,bcm4330-bt"; 677 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 678 }; 679 }; 680 681 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ 682 &uart4 { 683 pinctrl-names = "default"; 684 pinctrl-0 = <&pinctrl_uart4>; 685 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 686 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; 687 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; 688 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; 689 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; 690 uart-has-rtscts; 691 status = "okay"; 692 }; 693 694 &usbotg1 { 695 dr_mode = "host"; 696 vbus-supply = <®_usb1_vbus>; 697 disable-over-current; 698 status = "okay"; 699 }; 700 701 &usbotg2 { 702 dr_mode = "host"; 703 disable-over-current; 704 status = "okay"; 705 }; 706 707 /* SDIO WiFi */ 708 &usdhc2 { 709 pinctrl-names = "default"; 710 pinctrl-0 = <&pinctrl_usdhc2>; 711 bus-width = <4>; 712 non-removable; 713 vmmc-supply = <®_wifi>; 714 status = "okay"; 715 }; 716 717 /* eMMC */ 718 &usdhc3 { 719 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 720 pinctrl-0 = <&pinctrl_usdhc3>; 721 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 722 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 723 bus-width = <8>; 724 non-removable; 725 status = "okay"; 726 }; 727 728 &wdog1 { 729 pinctrl-names = "default"; 730 pinctrl-0 = <&pinctrl_wdog>; 731 fsl,ext-reset-output; 732 status = "okay"; 733 }; 734 735 &iomuxc { 736 pinctrl-names = "default"; 737 pinctrl-0 = <&pinctrl_hog>; 738 739 pinctrl_hog: hoggrp { 740 fsl,pins = < 741 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 742 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ 743 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 744 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 745 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */ 746 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */ 747 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */ 748 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */ 749 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ 750 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ 751 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ 752 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ 753 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ 754 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ 755 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ 756 >; 757 }; 758 759 pinctrl_accel: accelgrp { 760 fsl,pins = < 761 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 762 >; 763 }; 764 765 pinctrl_fec1: fec1grp { 766 fsl,pins = < 767 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 768 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 769 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 770 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 771 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 772 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 773 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 774 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 775 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 776 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 777 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 778 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 779 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 780 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 781 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ 782 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ 783 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 784 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 785 >; 786 }; 787 788 pinctrl_gsc: gscgrp { 789 fsl,pins = < 790 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 791 >; 792 }; 793 794 pinctrl_i2c1: i2c1grp { 795 fsl,pins = < 796 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 797 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 798 >; 799 }; 800 801 pinctrl_i2c2: i2c2grp { 802 fsl,pins = < 803 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 804 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 805 >; 806 }; 807 808 pinctrl_i2c3: i2c3grp { 809 fsl,pins = < 810 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 811 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 812 >; 813 }; 814 815 pinctrl_i2c4: i2c4grp { 816 fsl,pins = < 817 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 818 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 819 >; 820 }; 821 822 pinctrl_gpio_leds: gpioledgrp { 823 fsl,pins = < 824 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 825 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 826 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 827 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 828 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 829 >; 830 }; 831 832 pinctrl_pcie0: pciegrp { 833 fsl,pins = < 834 MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41 835 >; 836 }; 837 838 pinctrl_pmic: pmicgrp { 839 fsl,pins = < 840 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 841 >; 842 }; 843 844 pinctrl_pps: ppsgrp { 845 fsl,pins = < 846 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ 847 >; 848 }; 849 850 pinctrl_reg_wl: regwlgrp { 851 fsl,pins = < 852 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ 853 >; 854 }; 855 856 pinctrl_reg_usb1: regusb1grp { 857 fsl,pins = < 858 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 859 >; 860 }; 861 862 pinctrl_sai3: sai3grp { 863 fsl,pins = < 864 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 865 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 866 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 867 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 868 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 869 >; 870 }; 871 872 pinctrl_spi1: spi1grp { 873 fsl,pins = < 874 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 875 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 876 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 877 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 878 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ 879 >; 880 }; 881 882 pinctrl_spi2: spi2grp { 883 fsl,pins = < 884 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 885 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 886 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 887 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ 888 >; 889 }; 890 891 pinctrl_uart1: uart1grp { 892 fsl,pins = < 893 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 894 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 895 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */ 896 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */ 897 >; 898 }; 899 900 pinctrl_uart1_gpio: uart1gpiogrp { 901 fsl,pins = < 902 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ 903 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ 904 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ 905 >; 906 }; 907 908 pinctrl_uart2: uart2grp { 909 fsl,pins = < 910 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 911 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 912 >; 913 }; 914 915 pinctrl_uart3_gpio: uart3_gpiogrp { 916 fsl,pins = < 917 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ 918 >; 919 }; 920 921 pinctrl_uart3: uart3grp { 922 fsl,pins = < 923 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 924 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 925 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ 926 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ 927 >; 928 }; 929 930 pinctrl_uart4: uart4grp { 931 fsl,pins = < 932 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 933 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 934 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */ 935 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */ 936 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */ 937 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */ 938 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */ 939 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */ 940 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */ 941 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ 942 >; 943 }; 944 945 pinctrl_usdhc2: usdhc2grp { 946 fsl,pins = < 947 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 948 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 949 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 950 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 951 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 952 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 953 >; 954 }; 955 956 pinctrl_usdhc3: usdhc3grp { 957 fsl,pins = < 958 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 959 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 960 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 961 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 962 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 963 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 964 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 965 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 966 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 967 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 968 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 969 >; 970 }; 971 972 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 973 fsl,pins = < 974 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 975 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 976 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 977 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 978 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 979 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 980 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 981 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 982 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 983 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 984 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 985 >; 986 }; 987 988 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 989 fsl,pins = < 990 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 991 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 992 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 993 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 994 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 995 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 996 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 997 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 998 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 999 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 1000 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 1001 >; 1002 }; 1003 1004 pinctrl_wdog: wdoggrp { 1005 fsl,pins = < 1006 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 1007 >; 1008 }; 1009 };
Cache object: 47b74988369e303c189282b5cf46b945
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