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sys/contrib/device-tree/src/arm64/freescale/imx8mm.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright 2019 NXP 4 */ 5 6 #include <dt-bindings/clock/imx8mm-clock.h> 7 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/power/imx8mm-power.h> 11 #include <dt-bindings/reset/imx8mq-reset.h> 12 #include <dt-bindings/thermal/thermal.h> 13 14 #include "imx8mm-pinfunc.h" 15 16 / { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &fec1; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 i2c2 = &i2c3; 31 i2c3 = &i2c4; 32 mmc0 = &usdhc1; 33 mmc1 = &usdhc2; 34 mmc2 = &usdhc3; 35 serial0 = &uart1; 36 serial1 = &uart2; 37 serial2 = &uart3; 38 serial3 = &uart4; 39 spi0 = &ecspi1; 40 spi1 = &ecspi2; 41 spi2 = &ecspi3; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 idle-states { 49 entry-method = "psci"; 50 51 cpu_pd_wait: cpu-pd-wait { 52 compatible = "arm,idle-state"; 53 arm,psci-suspend-param = <0x0010033>; 54 local-timer-stop; 55 entry-latency-us = <1000>; 56 exit-latency-us = <700>; 57 min-residency-us = <2700>; 58 }; 59 }; 60 61 A53_0: cpu@0 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <0x0>; 65 clock-latency = <61036>; /* two CLK32 periods */ 66 clocks = <&clk IMX8MM_CLK_ARM>; 67 enable-method = "psci"; 68 i-cache-size = <0x8000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <128>; 74 next-level-cache = <&A53_L2>; 75 operating-points-v2 = <&a53_opp_table>; 76 nvmem-cells = <&cpu_speed_grade>; 77 nvmem-cell-names = "speed_grade"; 78 cpu-idle-states = <&cpu_pd_wait>; 79 #cooling-cells = <2>; 80 }; 81 82 A53_1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x1>; 86 clock-latency = <61036>; /* two CLK32 periods */ 87 clocks = <&clk IMX8MM_CLK_ARM>; 88 enable-method = "psci"; 89 i-cache-size = <0x8000>; 90 i-cache-line-size = <64>; 91 i-cache-sets = <256>; 92 d-cache-size = <0x8000>; 93 d-cache-line-size = <64>; 94 d-cache-sets = <128>; 95 next-level-cache = <&A53_L2>; 96 operating-points-v2 = <&a53_opp_table>; 97 cpu-idle-states = <&cpu_pd_wait>; 98 #cooling-cells = <2>; 99 }; 100 101 A53_2: cpu@2 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a53"; 104 reg = <0x2>; 105 clock-latency = <61036>; /* two CLK32 periods */ 106 clocks = <&clk IMX8MM_CLK_ARM>; 107 enable-method = "psci"; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&A53_L2>; 115 operating-points-v2 = <&a53_opp_table>; 116 cpu-idle-states = <&cpu_pd_wait>; 117 #cooling-cells = <2>; 118 }; 119 120 A53_3: cpu@3 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a53"; 123 reg = <0x3>; 124 clock-latency = <61036>; /* two CLK32 periods */ 125 clocks = <&clk IMX8MM_CLK_ARM>; 126 enable-method = "psci"; 127 i-cache-size = <0x8000>; 128 i-cache-line-size = <64>; 129 i-cache-sets = <256>; 130 d-cache-size = <0x8000>; 131 d-cache-line-size = <64>; 132 d-cache-sets = <128>; 133 next-level-cache = <&A53_L2>; 134 operating-points-v2 = <&a53_opp_table>; 135 cpu-idle-states = <&cpu_pd_wait>; 136 #cooling-cells = <2>; 137 }; 138 139 A53_L2: l2-cache0 { 140 compatible = "cache"; 141 cache-level = <2>; 142 cache-size = <0x80000>; 143 cache-line-size = <64>; 144 cache-sets = <512>; 145 }; 146 }; 147 148 a53_opp_table: opp-table { 149 compatible = "operating-points-v2"; 150 opp-shared; 151 152 opp-1200000000 { 153 opp-hz = /bits/ 64 <1200000000>; 154 opp-microvolt = <850000>; 155 opp-supported-hw = <0xe>, <0x7>; 156 clock-latency-ns = <150000>; 157 opp-suspend; 158 }; 159 160 opp-1600000000 { 161 opp-hz = /bits/ 64 <1600000000>; 162 opp-microvolt = <950000>; 163 opp-supported-hw = <0xc>, <0x7>; 164 clock-latency-ns = <150000>; 165 opp-suspend; 166 }; 167 168 opp-1800000000 { 169 opp-hz = /bits/ 64 <1800000000>; 170 opp-microvolt = <1000000>; 171 opp-supported-hw = <0x8>, <0x3>; 172 clock-latency-ns = <150000>; 173 opp-suspend; 174 }; 175 }; 176 177 osc_32k: clock-osc-32k { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <32768>; 181 clock-output-names = "osc_32k"; 182 }; 183 184 osc_24m: clock-osc-24m { 185 compatible = "fixed-clock"; 186 #clock-cells = <0>; 187 clock-frequency = <24000000>; 188 clock-output-names = "osc_24m"; 189 }; 190 191 clk_ext1: clock-ext1 { 192 compatible = "fixed-clock"; 193 #clock-cells = <0>; 194 clock-frequency = <133000000>; 195 clock-output-names = "clk_ext1"; 196 }; 197 198 clk_ext2: clock-ext2 { 199 compatible = "fixed-clock"; 200 #clock-cells = <0>; 201 clock-frequency = <133000000>; 202 clock-output-names = "clk_ext2"; 203 }; 204 205 clk_ext3: clock-ext3 { 206 compatible = "fixed-clock"; 207 #clock-cells = <0>; 208 clock-frequency = <133000000>; 209 clock-output-names = "clk_ext3"; 210 }; 211 212 clk_ext4: clock-ext4 { 213 compatible = "fixed-clock"; 214 #clock-cells = <0>; 215 clock-frequency = <133000000>; 216 clock-output-names = "clk_ext4"; 217 }; 218 219 psci { 220 compatible = "arm,psci-1.0"; 221 method = "smc"; 222 }; 223 224 pmu { 225 compatible = "arm,cortex-a53-pmu"; 226 interrupts = <GIC_PPI 7 227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 228 }; 229 230 timer { 231 compatible = "arm,armv8-timer"; 232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 236 clock-frequency = <8000000>; 237 arm,no-tick-in-suspend; 238 }; 239 240 thermal-zones { 241 cpu-thermal { 242 polling-delay-passive = <250>; 243 polling-delay = <2000>; 244 thermal-sensors = <&tmu>; 245 trips { 246 cpu_alert0: trip0 { 247 temperature = <85000>; 248 hysteresis = <2000>; 249 type = "passive"; 250 }; 251 252 cpu_crit0: trip1 { 253 temperature = <95000>; 254 hysteresis = <2000>; 255 type = "critical"; 256 }; 257 }; 258 259 cooling-maps { 260 map0 { 261 trip = <&cpu_alert0>; 262 cooling-device = 263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 267 }; 268 }; 269 }; 270 }; 271 272 usbphynop1: usbphynop1 { 273 #phy-cells = <0>; 274 compatible = "usb-nop-xceiv"; 275 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 278 clock-names = "main_clk"; 279 }; 280 281 usbphynop2: usbphynop2 { 282 #phy-cells = <0>; 283 compatible = "usb-nop-xceiv"; 284 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 285 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>; 286 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>; 287 clock-names = "main_clk"; 288 }; 289 290 soc: soc@0 { 291 compatible = "fsl,imx8mm-soc", "simple-bus"; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 ranges = <0x0 0x0 0x0 0x3e000000>; 295 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 296 nvmem-cells = <&imx8mm_uid>; 297 nvmem-cell-names = "soc_unique_id"; 298 299 aips1: bus@30000000 { 300 compatible = "fsl,aips-bus", "simple-bus"; 301 reg = <0x30000000 0x400000>; 302 #address-cells = <1>; 303 #size-cells = <1>; 304 ranges = <0x30000000 0x30000000 0x400000>; 305 306 spba2: spba-bus@30000000 { 307 compatible = "fsl,spba-bus", "simple-bus"; 308 #address-cells = <1>; 309 #size-cells = <1>; 310 reg = <0x30000000 0x100000>; 311 ranges; 312 313 sai1: sai@30010000 { 314 #sound-dai-cells = <0>; 315 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 316 reg = <0x30010000 0x10000>; 317 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 318 clocks = <&clk IMX8MM_CLK_SAI1_IPG>, 319 <&clk IMX8MM_CLK_SAI1_ROOT>, 320 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 321 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 322 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 323 dma-names = "rx", "tx"; 324 status = "disabled"; 325 }; 326 327 sai2: sai@30020000 { 328 #sound-dai-cells = <0>; 329 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 330 reg = <0x30020000 0x10000>; 331 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clk IMX8MM_CLK_SAI2_IPG>, 333 <&clk IMX8MM_CLK_SAI2_ROOT>, 334 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 335 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 336 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 337 dma-names = "rx", "tx"; 338 status = "disabled"; 339 }; 340 341 sai3: sai@30030000 { 342 #sound-dai-cells = <0>; 343 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 344 reg = <0x30030000 0x10000>; 345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clk IMX8MM_CLK_SAI3_IPG>, 347 <&clk IMX8MM_CLK_SAI3_ROOT>, 348 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 349 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 350 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 351 dma-names = "rx", "tx"; 352 status = "disabled"; 353 }; 354 355 sai5: sai@30050000 { 356 #sound-dai-cells = <0>; 357 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 358 reg = <0x30050000 0x10000>; 359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&clk IMX8MM_CLK_SAI5_IPG>, 361 <&clk IMX8MM_CLK_SAI5_ROOT>, 362 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 363 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 364 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 365 dma-names = "rx", "tx"; 366 status = "disabled"; 367 }; 368 369 sai6: sai@30060000 { 370 #sound-dai-cells = <0>; 371 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; 372 reg = <0x30060000 0x10000>; 373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 374 clocks = <&clk IMX8MM_CLK_SAI6_IPG>, 375 <&clk IMX8MM_CLK_SAI6_ROOT>, 376 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; 377 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 378 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 379 dma-names = "rx", "tx"; 380 status = "disabled"; 381 }; 382 383 micfil: audio-controller@30080000 { 384 compatible = "fsl,imx8mm-micfil"; 385 reg = <0x30080000 0x10000>; 386 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clk IMX8MM_CLK_PDM_IPG>, 391 <&clk IMX8MM_CLK_PDM_ROOT>, 392 <&clk IMX8MM_AUDIO_PLL1_OUT>, 393 <&clk IMX8MM_AUDIO_PLL2_OUT>, 394 <&clk IMX8MM_CLK_EXT3>; 395 clock-names = "ipg_clk", "ipg_clk_app", 396 "pll8k", "pll11k", "clkext3"; 397 dmas = <&sdma2 24 25 0x80000000>; 398 dma-names = "rx"; 399 status = "disabled"; 400 }; 401 402 spdif1: spdif@30090000 { 403 compatible = "fsl,imx35-spdif"; 404 reg = <0x30090000 0x10000>; 405 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ 407 <&clk IMX8MM_CLK_24M>, /* rxtx0 */ 408 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */ 409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */ 410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */ 411 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */ 412 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */ 413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */ 414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */ 415 <&clk IMX8MM_CLK_DUMMY>; /* spba */ 416 clock-names = "core", "rxtx0", 417 "rxtx1", "rxtx2", 418 "rxtx3", "rxtx4", 419 "rxtx5", "rxtx6", 420 "rxtx7", "spba"; 421 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 }; 426 427 gpio1: gpio@30200000 { 428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 429 reg = <0x30200000 0x10000>; 430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>; 433 gpio-controller; 434 #gpio-cells = <2>; 435 interrupt-controller; 436 #interrupt-cells = <2>; 437 gpio-ranges = <&iomuxc 0 10 30>; 438 }; 439 440 gpio2: gpio@30210000 { 441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 442 reg = <0x30210000 0x10000>; 443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>; 446 gpio-controller; 447 #gpio-cells = <2>; 448 interrupt-controller; 449 #interrupt-cells = <2>; 450 gpio-ranges = <&iomuxc 0 40 21>; 451 }; 452 453 gpio3: gpio@30220000 { 454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 455 reg = <0x30220000 0x10000>; 456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>; 459 gpio-controller; 460 #gpio-cells = <2>; 461 interrupt-controller; 462 #interrupt-cells = <2>; 463 gpio-ranges = <&iomuxc 0 61 26>; 464 }; 465 466 gpio4: gpio@30230000 { 467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 468 reg = <0x30230000 0x10000>; 469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>; 472 gpio-controller; 473 #gpio-cells = <2>; 474 interrupt-controller; 475 #interrupt-cells = <2>; 476 gpio-ranges = <&iomuxc 0 87 32>; 477 }; 478 479 gpio5: gpio@30240000 { 480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio"; 481 reg = <0x30240000 0x10000>; 482 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>; 485 gpio-controller; 486 #gpio-cells = <2>; 487 interrupt-controller; 488 #interrupt-cells = <2>; 489 gpio-ranges = <&iomuxc 0 119 30>; 490 }; 491 492 tmu: tmu@30260000 { 493 compatible = "fsl,imx8mm-tmu"; 494 reg = <0x30260000 0x10000>; 495 clocks = <&clk IMX8MM_CLK_TMU_ROOT>; 496 #thermal-sensor-cells = <0>; 497 }; 498 499 wdog1: watchdog@30280000 { 500 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 501 reg = <0x30280000 0x10000>; 502 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>; 504 status = "disabled"; 505 }; 506 507 wdog2: watchdog@30290000 { 508 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 509 reg = <0x30290000 0x10000>; 510 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>; 512 status = "disabled"; 513 }; 514 515 wdog3: watchdog@302a0000 { 516 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt"; 517 reg = <0x302a0000 0x10000>; 518 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>; 520 status = "disabled"; 521 }; 522 523 sdma2: dma-controller@302c0000 { 524 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 525 reg = <0x302c0000 0x10000>; 526 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, 528 <&clk IMX8MM_CLK_SDMA2_ROOT>; 529 clock-names = "ipg", "ahb"; 530 #dma-cells = <3>; 531 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 532 }; 533 534 sdma3: dma-controller@302b0000 { 535 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 536 reg = <0x302b0000 0x10000>; 537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, 539 <&clk IMX8MM_CLK_SDMA3_ROOT>; 540 clock-names = "ipg", "ahb"; 541 #dma-cells = <3>; 542 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 543 }; 544 545 iomuxc: pinctrl@30330000 { 546 compatible = "fsl,imx8mm-iomuxc"; 547 reg = <0x30330000 0x10000>; 548 }; 549 550 gpr: iomuxc-gpr@30340000 { 551 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; 552 reg = <0x30340000 0x10000>; 553 }; 554 555 ocotp: efuse@30350000 { 556 compatible = "fsl,imx8mm-ocotp", "syscon"; 557 reg = <0x30350000 0x10000>; 558 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>; 559 /* For nvmem subnodes */ 560 #address-cells = <1>; 561 #size-cells = <1>; 562 563 imx8mm_uid: unique-id@410 { 564 reg = <0x4 0x8>; 565 }; 566 567 cpu_speed_grade: speed-grade@10 { 568 reg = <0x10 4>; 569 }; 570 571 fec_mac_address: mac-address@90 { 572 reg = <0x90 6>; 573 }; 574 }; 575 576 anatop: anatop@30360000 { 577 compatible = "fsl,imx8mm-anatop", "syscon"; 578 reg = <0x30360000 0x10000>; 579 }; 580 581 snvs: snvs@30370000 { 582 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 583 reg = <0x30370000 0x10000>; 584 585 snvs_rtc: snvs-rtc-lp { 586 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 587 regmap = <&snvs>; 588 offset = <0x34>; 589 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 592 clock-names = "snvs-rtc"; 593 }; 594 595 snvs_pwrkey: snvs-powerkey { 596 compatible = "fsl,sec-v4.0-pwrkey"; 597 regmap = <&snvs>; 598 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; 600 clock-names = "snvs-pwrkey"; 601 linux,keycode = <KEY_POWER>; 602 wakeup-source; 603 status = "disabled"; 604 }; 605 606 snvs_lpgpr: snvs-lpgpr { 607 compatible = "fsl,imx8mm-snvs-lpgpr", 608 "fsl,imx7d-snvs-lpgpr"; 609 }; 610 }; 611 612 clk: clock-controller@30380000 { 613 compatible = "fsl,imx8mm-ccm"; 614 reg = <0x30380000 0x10000>; 615 #clock-cells = <1>; 616 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 617 <&clk_ext3>, <&clk_ext4>; 618 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 619 "clk_ext3", "clk_ext4"; 620 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>, 621 <&clk IMX8MM_CLK_A53_CORE>, 622 <&clk IMX8MM_CLK_NOC>, 623 <&clk IMX8MM_CLK_AUDIO_AHB>, 624 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, 625 <&clk IMX8MM_SYS_PLL3>, 626 <&clk IMX8MM_VIDEO_PLL1>, 627 <&clk IMX8MM_AUDIO_PLL1>; 628 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 629 <&clk IMX8MM_ARM_PLL_OUT>, 630 <&clk IMX8MM_SYS_PLL3_OUT>, 631 <&clk IMX8MM_SYS_PLL1_800M>; 632 assigned-clock-rates = <0>, <0>, <0>, 633 <400000000>, 634 <400000000>, 635 <750000000>, 636 <594000000>, 637 <393216000>; 638 }; 639 640 src: reset-controller@30390000 { 641 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"; 642 reg = <0x30390000 0x10000>; 643 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 644 #reset-cells = <1>; 645 }; 646 647 gpc: gpc@303a0000 { 648 compatible = "fsl,imx8mm-gpc"; 649 reg = <0x303a0000 0x10000>; 650 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-parent = <&gic>; 652 interrupt-controller; 653 #interrupt-cells = <3>; 654 655 pgc { 656 #address-cells = <1>; 657 #size-cells = <0>; 658 659 pgc_hsiomix: power-domain@0 { 660 #power-domain-cells = <0>; 661 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>; 662 clocks = <&clk IMX8MM_CLK_USB_BUS>; 663 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 664 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 665 }; 666 667 pgc_pcie: power-domain@1 { 668 #power-domain-cells = <0>; 669 reg = <IMX8MM_POWER_DOMAIN_PCIE>; 670 power-domains = <&pgc_hsiomix>; 671 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; 672 }; 673 674 pgc_otg1: power-domain@2 { 675 #power-domain-cells = <0>; 676 reg = <IMX8MM_POWER_DOMAIN_OTG1>; 677 power-domains = <&pgc_hsiomix>; 678 }; 679 680 pgc_otg2: power-domain@3 { 681 #power-domain-cells = <0>; 682 reg = <IMX8MM_POWER_DOMAIN_OTG2>; 683 power-domains = <&pgc_hsiomix>; 684 }; 685 686 pgc_gpumix: power-domain@4 { 687 #power-domain-cells = <0>; 688 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>; 689 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 690 <&clk IMX8MM_CLK_GPU_AHB>; 691 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, 692 <&clk IMX8MM_CLK_GPU_AHB>; 693 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, 694 <&clk IMX8MM_SYS_PLL1_800M>; 695 assigned-clock-rates = <800000000>, <400000000>; 696 }; 697 698 pgc_gpu: power-domain@5 { 699 #power-domain-cells = <0>; 700 reg = <IMX8MM_POWER_DOMAIN_GPU>; 701 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 702 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 703 <&clk IMX8MM_CLK_GPU2D_ROOT>, 704 <&clk IMX8MM_CLK_GPU3D_ROOT>; 705 resets = <&src IMX8MQ_RESET_GPU_RESET>; 706 power-domains = <&pgc_gpumix>; 707 }; 708 709 pgc_vpumix: power-domain@6 { 710 #power-domain-cells = <0>; 711 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>; 712 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; 713 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; 714 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; 715 }; 716 717 pgc_vpu_g1: power-domain@7 { 718 #power-domain-cells = <0>; 719 reg = <IMX8MM_POWER_DOMAIN_VPUG1>; 720 }; 721 722 pgc_vpu_g2: power-domain@8 { 723 #power-domain-cells = <0>; 724 reg = <IMX8MM_POWER_DOMAIN_VPUG2>; 725 }; 726 727 pgc_vpu_h1: power-domain@9 { 728 #power-domain-cells = <0>; 729 reg = <IMX8MM_POWER_DOMAIN_VPUH1>; 730 }; 731 732 pgc_dispmix: power-domain@10 { 733 #power-domain-cells = <0>; 734 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>; 735 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 736 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 737 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, 738 <&clk IMX8MM_CLK_DISP_APB>; 739 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 740 <&clk IMX8MM_SYS_PLL1_800M>; 741 assigned-clock-rates = <500000000>, <200000000>; 742 }; 743 744 pgc_mipi: power-domain@11 { 745 #power-domain-cells = <0>; 746 reg = <IMX8MM_POWER_DOMAIN_MIPI>; 747 }; 748 }; 749 }; 750 }; 751 752 aips2: bus@30400000 { 753 compatible = "fsl,aips-bus", "simple-bus"; 754 reg = <0x30400000 0x400000>; 755 #address-cells = <1>; 756 #size-cells = <1>; 757 ranges = <0x30400000 0x30400000 0x400000>; 758 759 pwm1: pwm@30660000 { 760 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 761 reg = <0x30660000 0x10000>; 762 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 763 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, 764 <&clk IMX8MM_CLK_PWM1_ROOT>; 765 clock-names = "ipg", "per"; 766 #pwm-cells = <3>; 767 status = "disabled"; 768 }; 769 770 pwm2: pwm@30670000 { 771 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 772 reg = <0x30670000 0x10000>; 773 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, 775 <&clk IMX8MM_CLK_PWM2_ROOT>; 776 clock-names = "ipg", "per"; 777 #pwm-cells = <3>; 778 status = "disabled"; 779 }; 780 781 pwm3: pwm@30680000 { 782 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 783 reg = <0x30680000 0x10000>; 784 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, 786 <&clk IMX8MM_CLK_PWM3_ROOT>; 787 clock-names = "ipg", "per"; 788 #pwm-cells = <3>; 789 status = "disabled"; 790 }; 791 792 pwm4: pwm@30690000 { 793 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm"; 794 reg = <0x30690000 0x10000>; 795 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, 797 <&clk IMX8MM_CLK_PWM4_ROOT>; 798 clock-names = "ipg", "per"; 799 #pwm-cells = <3>; 800 status = "disabled"; 801 }; 802 803 system_counter: timer@306a0000 { 804 compatible = "nxp,sysctr-timer"; 805 reg = <0x306a0000 0x20000>; 806 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 807 clocks = <&osc_24m>; 808 clock-names = "per"; 809 }; 810 }; 811 812 aips3: bus@30800000 { 813 compatible = "fsl,aips-bus", "simple-bus"; 814 reg = <0x30800000 0x400000>; 815 #address-cells = <1>; 816 #size-cells = <1>; 817 ranges = <0x30800000 0x30800000 0x400000>, 818 <0x8000000 0x8000000 0x10000000>; 819 820 spba1: spba-bus@30800000 { 821 compatible = "fsl,spba-bus", "simple-bus"; 822 #address-cells = <1>; 823 #size-cells = <1>; 824 reg = <0x30800000 0x100000>; 825 ranges; 826 827 ecspi1: spi@30820000 { 828 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 829 #address-cells = <1>; 830 #size-cells = <0>; 831 reg = <0x30820000 0x10000>; 832 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>, 834 <&clk IMX8MM_CLK_ECSPI1_ROOT>; 835 clock-names = "ipg", "per"; 836 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 837 dma-names = "rx", "tx"; 838 status = "disabled"; 839 }; 840 841 ecspi2: spi@30830000 { 842 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 reg = <0x30830000 0x10000>; 846 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 847 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>, 848 <&clk IMX8MM_CLK_ECSPI2_ROOT>; 849 clock-names = "ipg", "per"; 850 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 851 dma-names = "rx", "tx"; 852 status = "disabled"; 853 }; 854 855 ecspi3: spi@30840000 { 856 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi"; 857 #address-cells = <1>; 858 #size-cells = <0>; 859 reg = <0x30840000 0x10000>; 860 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>, 862 <&clk IMX8MM_CLK_ECSPI3_ROOT>; 863 clock-names = "ipg", "per"; 864 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 865 dma-names = "rx", "tx"; 866 status = "disabled"; 867 }; 868 869 uart1: serial@30860000 { 870 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 871 reg = <0x30860000 0x10000>; 872 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 873 clocks = <&clk IMX8MM_CLK_UART1_ROOT>, 874 <&clk IMX8MM_CLK_UART1_ROOT>; 875 clock-names = "ipg", "per"; 876 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 877 dma-names = "rx", "tx"; 878 status = "disabled"; 879 }; 880 881 uart3: serial@30880000 { 882 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 883 reg = <0x30880000 0x10000>; 884 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&clk IMX8MM_CLK_UART3_ROOT>, 886 <&clk IMX8MM_CLK_UART3_ROOT>; 887 clock-names = "ipg", "per"; 888 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 889 dma-names = "rx", "tx"; 890 status = "disabled"; 891 }; 892 893 uart2: serial@30890000 { 894 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 895 reg = <0x30890000 0x10000>; 896 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&clk IMX8MM_CLK_UART2_ROOT>, 898 <&clk IMX8MM_CLK_UART2_ROOT>; 899 clock-names = "ipg", "per"; 900 status = "disabled"; 901 }; 902 }; 903 904 crypto: crypto@30900000 { 905 compatible = "fsl,sec-v4.0"; 906 #address-cells = <1>; 907 #size-cells = <1>; 908 reg = <0x30900000 0x40000>; 909 ranges = <0 0x30900000 0x40000>; 910 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&clk IMX8MM_CLK_AHB>, 912 <&clk IMX8MM_CLK_IPG_ROOT>; 913 clock-names = "aclk", "ipg"; 914 915 sec_jr0: jr@1000 { 916 compatible = "fsl,sec-v4.0-job-ring"; 917 reg = <0x1000 0x1000>; 918 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 919 status = "disabled"; 920 }; 921 922 sec_jr1: jr@2000 { 923 compatible = "fsl,sec-v4.0-job-ring"; 924 reg = <0x2000 0x1000>; 925 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 926 }; 927 928 sec_jr2: jr@3000 { 929 compatible = "fsl,sec-v4.0-job-ring"; 930 reg = <0x3000 0x1000>; 931 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 932 }; 933 }; 934 935 i2c1: i2c@30a20000 { 936 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 937 #address-cells = <1>; 938 #size-cells = <0>; 939 reg = <0x30a20000 0x10000>; 940 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>; 942 status = "disabled"; 943 }; 944 945 i2c2: i2c@30a30000 { 946 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 reg = <0x30a30000 0x10000>; 950 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>; 952 status = "disabled"; 953 }; 954 955 i2c3: i2c@30a40000 { 956 #address-cells = <1>; 957 #size-cells = <0>; 958 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 959 reg = <0x30a40000 0x10000>; 960 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>; 962 status = "disabled"; 963 }; 964 965 i2c4: i2c@30a50000 { 966 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 reg = <0x30a50000 0x10000>; 970 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>; 972 status = "disabled"; 973 }; 974 975 uart4: serial@30a60000 { 976 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart"; 977 reg = <0x30a60000 0x10000>; 978 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&clk IMX8MM_CLK_UART4_ROOT>, 980 <&clk IMX8MM_CLK_UART4_ROOT>; 981 clock-names = "ipg", "per"; 982 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 983 dma-names = "rx", "tx"; 984 status = "disabled"; 985 }; 986 987 mu: mailbox@30aa0000 { 988 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu"; 989 reg = <0x30aa0000 0x10000>; 990 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&clk IMX8MM_CLK_MU_ROOT>; 992 #mbox-cells = <2>; 993 }; 994 995 usdhc1: mmc@30b40000 { 996 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 997 reg = <0x30b40000 0x10000>; 998 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1000 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1001 <&clk IMX8MM_CLK_USDHC1_ROOT>; 1002 clock-names = "ipg", "ahb", "per"; 1003 fsl,tuning-start-tap = <20>; 1004 fsl,tuning-step = <2>; 1005 bus-width = <4>; 1006 status = "disabled"; 1007 }; 1008 1009 usdhc2: mmc@30b50000 { 1010 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1011 reg = <0x30b50000 0x10000>; 1012 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1014 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1015 <&clk IMX8MM_CLK_USDHC2_ROOT>; 1016 clock-names = "ipg", "ahb", "per"; 1017 fsl,tuning-start-tap = <20>; 1018 fsl,tuning-step = <2>; 1019 bus-width = <4>; 1020 status = "disabled"; 1021 }; 1022 1023 usdhc3: mmc@30b60000 { 1024 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1025 reg = <0x30b60000 0x10000>; 1026 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&clk IMX8MM_CLK_IPG_ROOT>, 1028 <&clk IMX8MM_CLK_NAND_USDHC_BUS>, 1029 <&clk IMX8MM_CLK_USDHC3_ROOT>; 1030 clock-names = "ipg", "ahb", "per"; 1031 fsl,tuning-start-tap = <20>; 1032 fsl,tuning-step = <2>; 1033 bus-width = <4>; 1034 status = "disabled"; 1035 }; 1036 1037 flexspi: spi@30bb0000 { 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 compatible = "nxp,imx8mm-fspi"; 1041 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1042 reg-names = "fspi_base", "fspi_mmap"; 1043 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>, 1045 <&clk IMX8MM_CLK_QSPI_ROOT>; 1046 clock-names = "fspi_en", "fspi"; 1047 status = "disabled"; 1048 }; 1049 1050 sdma1: dma-controller@30bd0000 { 1051 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; 1052 reg = <0x30bd0000 0x10000>; 1053 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, 1055 <&clk IMX8MM_CLK_AHB>; 1056 clock-names = "ipg", "ahb"; 1057 #dma-cells = <3>; 1058 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1059 }; 1060 1061 fec1: ethernet@30be0000 { 1062 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1063 reg = <0x30be0000 0x10000>; 1064 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>, 1069 <&clk IMX8MM_CLK_ENET1_ROOT>, 1070 <&clk IMX8MM_CLK_ENET_TIMER>, 1071 <&clk IMX8MM_CLK_ENET_REF>, 1072 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1073 clock-names = "ipg", "ahb", "ptp", 1074 "enet_clk_ref", "enet_out"; 1075 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, 1076 <&clk IMX8MM_CLK_ENET_TIMER>, 1077 <&clk IMX8MM_CLK_ENET_REF>, 1078 <&clk IMX8MM_CLK_ENET_PHY_REF>; 1079 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, 1080 <&clk IMX8MM_SYS_PLL2_100M>, 1081 <&clk IMX8MM_SYS_PLL2_125M>, 1082 <&clk IMX8MM_SYS_PLL2_50M>; 1083 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1084 fsl,num-tx-queues = <3>; 1085 fsl,num-rx-queues = <3>; 1086 nvmem-cells = <&fec_mac_address>; 1087 nvmem-cell-names = "mac-address"; 1088 fsl,stop-mode = <&gpr 0x10 3>; 1089 status = "disabled"; 1090 }; 1091 1092 }; 1093 1094 aips4: bus@32c00000 { 1095 compatible = "fsl,aips-bus", "simple-bus"; 1096 reg = <0x32c00000 0x400000>; 1097 #address-cells = <1>; 1098 #size-cells = <1>; 1099 ranges = <0x32c00000 0x32c00000 0x400000>; 1100 1101 csi: csi@32e20000 { 1102 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; 1103 reg = <0x32e20000 0x1000>; 1104 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; 1106 clock-names = "mclk"; 1107 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; 1108 status = "disabled"; 1109 1110 port { 1111 csi_in: endpoint { 1112 remote-endpoint = <&imx8mm_mipi_csi_out>; 1113 }; 1114 }; 1115 }; 1116 1117 disp_blk_ctrl: blk-ctrl@32e28000 { 1118 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; 1119 reg = <0x32e28000 0x100>; 1120 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 1121 <&pgc_dispmix>, <&pgc_mipi>, 1122 <&pgc_mipi>; 1123 power-domain-names = "bus", "csi-bridge", 1124 "lcdif", "mipi-dsi", 1125 "mipi-csi"; 1126 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1127 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1128 <&clk IMX8MM_CLK_CSI1_ROOT>, 1129 <&clk IMX8MM_CLK_DISP_AXI_ROOT>, 1130 <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1131 <&clk IMX8MM_CLK_DISP_ROOT>, 1132 <&clk IMX8MM_CLK_DSI_CORE>, 1133 <&clk IMX8MM_CLK_DSI_PHY_REF>, 1134 <&clk IMX8MM_CLK_CSI1_CORE>, 1135 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1136 clock-names = "csi-bridge-axi","csi-bridge-apb", 1137 "csi-bridge-core", "lcdif-axi", 1138 "lcdif-apb", "lcdif-pix", 1139 "dsi-pclk", "dsi-ref", 1140 "csi-aclk", "csi-pclk"; 1141 #power-domain-cells = <1>; 1142 }; 1143 1144 mipi_csi: mipi-csi@32e30000 { 1145 compatible = "fsl,imx8mm-mipi-csi2"; 1146 reg = <0x32e30000 0x1000>; 1147 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1148 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, 1149 <&clk IMX8MM_CLK_CSI1_PHY_REF>; 1150 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, 1151 <&clk IMX8MM_SYS_PLL2_1000M>; 1152 clock-frequency = <333000000>; 1153 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, 1154 <&clk IMX8MM_CLK_CSI1_ROOT>, 1155 <&clk IMX8MM_CLK_CSI1_PHY_REF>, 1156 <&clk IMX8MM_CLK_DISP_AXI_ROOT>; 1157 clock-names = "pclk", "wrap", "phy", "axi"; 1158 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; 1159 status = "disabled"; 1160 1161 ports { 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 1165 port@0 { 1166 reg = <0>; 1167 }; 1168 1169 port@1 { 1170 reg = <1>; 1171 1172 imx8mm_mipi_csi_out: endpoint { 1173 remote-endpoint = <&csi_in>; 1174 }; 1175 }; 1176 }; 1177 }; 1178 1179 usbotg1: usb@32e40000 { 1180 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1181 reg = <0x32e40000 0x200>; 1182 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1184 clock-names = "usb1_ctrl_root_clk"; 1185 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1186 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1187 phys = <&usbphynop1>; 1188 fsl,usbmisc = <&usbmisc1 0>; 1189 power-domains = <&pgc_otg1>; 1190 status = "disabled"; 1191 }; 1192 1193 usbmisc1: usbmisc@32e40200 { 1194 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1195 #index-cells = <1>; 1196 reg = <0x32e40200 0x200>; 1197 }; 1198 1199 usbotg2: usb@32e50000 { 1200 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; 1201 reg = <0x32e50000 0x200>; 1202 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; 1204 clock-names = "usb1_ctrl_root_clk"; 1205 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; 1206 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; 1207 phys = <&usbphynop2>; 1208 fsl,usbmisc = <&usbmisc2 0>; 1209 power-domains = <&pgc_otg2>; 1210 status = "disabled"; 1211 }; 1212 1213 usbmisc2: usbmisc@32e50200 { 1214 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc"; 1215 #index-cells = <1>; 1216 reg = <0x32e50200 0x200>; 1217 }; 1218 1219 pcie_phy: pcie-phy@32f00000 { 1220 compatible = "fsl,imx8mm-pcie-phy"; 1221 reg = <0x32f00000 0x10000>; 1222 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1223 clock-names = "ref"; 1224 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 1225 assigned-clock-rates = <100000000>; 1226 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>; 1227 resets = <&src IMX8MQ_RESET_PCIEPHY>; 1228 reset-names = "pciephy"; 1229 #phy-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 dma_apbh: dma-controller@33000000 { 1235 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1236 reg = <0x33000000 0x2000>; 1237 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1241 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1242 #dma-cells = <1>; 1243 dma-channels = <4>; 1244 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1245 }; 1246 1247 gpmi: nand-controller@33002000{ 1248 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand"; 1249 #address-cells = <1>; 1250 #size-cells = <1>; 1251 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1252 reg-names = "gpmi-nand", "bch"; 1253 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1254 interrupt-names = "bch"; 1255 clocks = <&clk IMX8MM_CLK_NAND_ROOT>, 1256 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; 1257 clock-names = "gpmi_io", "gpmi_bch_apb"; 1258 dmas = <&dma_apbh 0>; 1259 dma-names = "rx-tx"; 1260 status = "disabled"; 1261 }; 1262 1263 pcie0: pcie@33800000 { 1264 compatible = "fsl,imx8mm-pcie"; 1265 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 1266 reg-names = "dbi", "config"; 1267 #address-cells = <3>; 1268 #size-cells = <2>; 1269 device_type = "pci"; 1270 bus-range = <0x00 0xff>; 1271 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ 1272 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1273 num-lanes = <1>; 1274 num-viewport = <4>; 1275 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1276 interrupt-names = "msi"; 1277 #interrupt-cells = <1>; 1278 interrupt-map-mask = <0 0 0 0x7>; 1279 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1280 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1281 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1282 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1283 fsl,max-link-speed = <2>; 1284 linux,pci-domain = <0>; 1285 power-domains = <&pgc_pcie>; 1286 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1287 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1288 reset-names = "apps", "turnoff"; 1289 phys = <&pcie_phy>; 1290 phy-names = "pcie-phy"; 1291 status = "disabled"; 1292 }; 1293 1294 gpu_3d: gpu@38000000 { 1295 compatible = "vivante,gc"; 1296 reg = <0x38000000 0x8000>; 1297 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1299 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1300 <&clk IMX8MM_CLK_GPU3D_ROOT>, 1301 <&clk IMX8MM_CLK_GPU3D_ROOT>; 1302 clock-names = "reg", "bus", "core", "shader"; 1303 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, 1304 <&clk IMX8MM_GPU_PLL_OUT>; 1305 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1306 assigned-clock-rates = <0>, <1000000000>; 1307 power-domains = <&pgc_gpu>; 1308 }; 1309 1310 gpu_2d: gpu@38008000 { 1311 compatible = "vivante,gc"; 1312 reg = <0x38008000 0x8000>; 1313 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1314 clocks = <&clk IMX8MM_CLK_GPU_AHB>, 1315 <&clk IMX8MM_CLK_GPU_BUS_ROOT>, 1316 <&clk IMX8MM_CLK_GPU2D_ROOT>; 1317 clock-names = "reg", "bus", "core"; 1318 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, 1319 <&clk IMX8MM_GPU_PLL_OUT>; 1320 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; 1321 assigned-clock-rates = <0>, <1000000000>; 1322 power-domains = <&pgc_gpu>; 1323 }; 1324 1325 vpu_g1: video-codec@38300000 { 1326 compatible = "nxp,imx8mm-vpu-g1"; 1327 reg = <0x38300000 0x10000>; 1328 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1329 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; 1330 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; 1331 }; 1332 1333 vpu_g2: video-codec@38310000 { 1334 compatible = "nxp,imx8mq-vpu-g2"; 1335 reg = <0x38310000 0x10000>; 1336 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1337 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; 1338 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; 1339 }; 1340 1341 vpu_blk_ctrl: blk-ctrl@38330000 { 1342 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; 1343 reg = <0x38330000 0x100>; 1344 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 1345 <&pgc_vpu_g2>, <&pgc_vpu_h1>; 1346 power-domain-names = "bus", "g1", "g2", "h1"; 1347 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, 1348 <&clk IMX8MM_CLK_VPU_G2_ROOT>, 1349 <&clk IMX8MM_CLK_VPU_H1_ROOT>; 1350 clock-names = "g1", "g2", "h1"; 1351 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, 1352 <&clk IMX8MM_CLK_VPU_G2>; 1353 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, 1354 <&clk IMX8MM_VPU_PLL_OUT>; 1355 assigned-clock-rates = <600000000>, 1356 <600000000>; 1357 #power-domain-cells = <1>; 1358 }; 1359 1360 gic: interrupt-controller@38800000 { 1361 compatible = "arm,gic-v3"; 1362 reg = <0x38800000 0x10000>, /* GIC Dist */ 1363 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ 1364 #interrupt-cells = <3>; 1365 interrupt-controller; 1366 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1367 }; 1368 1369 ddrc: memory-controller@3d400000 { 1370 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 1371 reg = <0x3d400000 0x400000>; 1372 clock-names = "core", "pll", "alt", "apb"; 1373 clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 1374 <&clk IMX8MM_DRAM_PLL>, 1375 <&clk IMX8MM_CLK_DRAM_ALT>, 1376 <&clk IMX8MM_CLK_DRAM_APB>; 1377 }; 1378 1379 ddr-pmu@3d800000 { 1380 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1381 reg = <0x3d800000 0x400000>; 1382 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1383 }; 1384 }; 1385 };
Cache object: 622b6660e7c142f85f0ab6851b7bc36c
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