imx8mn-tqma8mqnl-mba8mx.dts

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    1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
    2 /*
    3  * Copyright 2020-2021 TQ-Systems GmbH
    4  */
    5 
    6 /dts-v1/;
    7 
    8 #include "imx8mn-tqma8mqnl.dtsi"
    9 #include "mba8mx.dtsi"
   10 
   11 / {
   12         model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx";
   13         compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
   14 
   15         aliases {
   16                 eeprom0 = &eeprom3;
   17                 mmc0 = &usdhc3;
   18                 mmc1 = &usdhc2;
   19                 mmc2 = &usdhc1;
   20                 rtc0 = &pcf85063;
   21                 rtc1 = &snvs_rtc;
   22         };
   23 
   24         reg_usdhc2_vmmc: regulator-vmmc {
   25                 compatible = "regulator-fixed";
   26                 pinctrl-names = "default";
   27                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
   28                 regulator-name = "VSD_3V3";
   29                 regulator-min-microvolt = <3300000>;
   30                 regulator-max-microvolt = <3300000>;
   31                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
   32                 enable-active-high;
   33                 startup-delay-us = <100>;
   34                 off-on-delay-us = <12000>;
   35         };
   36 };
   37 
   38 /* Located on TQMa8MxML-ADAP */
   39 &gpio2 {
   40         pinctrl-names = "default";
   41         pinctrl-0 = <&pinctrl_usb0hub_sel>;
   42 
   43         sel-usb-hub-hog {
   44                 gpio-hog;
   45                 gpios = <1 GPIO_ACTIVE_HIGH>;
   46                 output-high;
   47         };
   48 };
   49 
   50 &i2c1 {
   51         expander2: gpio@27 {
   52                 compatible = "nxp,pca9555";
   53                 reg = <0x27>;
   54                 gpio-controller;
   55                 #gpio-cells = <2>;
   56                 vcc-supply = <&reg_vcc_3v3>;
   57                 pinctrl-names = "default";
   58                 pinctrl-0 = <&pinctrl_expander2>;
   59                 interrupt-parent = <&gpio1>;
   60                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
   61                 interrupt-controller;
   62                 #interrupt-cells = <2>;
   63         };
   64 };
   65 
   66 &sai3 {
   67         assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
   68         assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
   69         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
   70         clocks = <&clk IMX8MN_CLK_SAI3_IPG>, <&clk IMX8MN_CLK_DUMMY>,
   71                  <&clk IMX8MN_CLK_SAI3_ROOT>, <&clk IMX8MN_CLK_DUMMY>,
   72                  <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_AUDIO_PLL1_OUT>,
   73                  <&clk IMX8MN_AUDIO_PLL2_OUT>;
   74 };
   75 
   76 &tlv320aic3x04 {
   77         clock-names = "mclk";
   78         clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
   79 };
   80 
   81 &usbotg1 {
   82         dr_mode = "host";
   83         disable-over-current;
   84         power-active-high;
   85         status = "okay";
   86 };
   87 
   88 &iomuxc {
   89         pinctrl_ecspi1: ecspi1grp {
   90                 fsl,pins = <MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x00000146>,
   91                            <MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x00000146>,
   92                            <MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x00000146>,
   93                            <MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9           0x00000146>;
   94         };
   95 
   96         pinctrl_ecspi2: ecspi2grp {
   97                 fsl,pins = <MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK        0x00000146>,
   98                            <MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI        0x00000146>,
   99                            <MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO        0x00000146>,
  100                            <MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13          0x00000146>;
  101         };
  102 
  103         pinctrl_expander2: expander2grp {
  104                 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9           0x94>;
  105         };
  106 
  107         pinctrl_fec1: fec1grp {
  108                 fsl,pins = <MX8MN_IOMUXC_ENET_MDC_ENET1_MDC             0x40000002>,
  109                            <MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO           0x40000002>,
  110                            <MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3       0x14>,
  111                            <MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2       0x14>,
  112                            <MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1       0x14>,
  113                            <MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0       0x14>,
  114                            <MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3       0x90>,
  115                            <MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2       0x90>,
  116                            <MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1       0x90>,
  117                            <MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0       0x90>,
  118                            <MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC       0x14>,
  119                            <MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC       0x90>,
  120                            <MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x90>,
  121                            <MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x14>;
  122         };
  123 
  124         pinctrl_gpiobutton: gpiobuttongrp {
  125                 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5           0x84>,
  126                            <MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7           0x84>,
  127                            <MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0              0x84>;
  128         };
  129 
  130         pinctrl_gpioled: gpioledgrp {
  131                 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0           0x84>,
  132                            <MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14            0x84>;
  133         };
  134 
  135         pinctrl_i2c2: i2c2grp {
  136                 fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL              0x400001C4>,
  137                            <MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA              0x400001C4>;
  138         };
  139 
  140         pinctrl_i2c2_gpio: i2c2gpiogrp {
  141                 fsl,pins = <MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16            0x400001C4>,
  142                            <MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17            0x400001C4>;
  143         };
  144 
  145         pinctrl_i2c3: i2c3grp {
  146                 fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL              0x400001C4>,
  147                            <MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA              0x400001C4>;
  148         };
  149 
  150         pinctrl_i2c3_gpio: i2c3gpiogrp {
  151                 fsl,pins = <MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18            0x400001C4>,
  152                            <MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19            0x400001C4>;
  153         };
  154 
  155         pinctrl_pwm3: pwm3grp {
  156                 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT            0x14>;
  157         };
  158 
  159         pinctrl_pwm4: pwm4grp {
  160                 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT            0x14>;
  161         };
  162 
  163         pinctrl_sai3: sai3grp {
  164                 fsl,pins = <MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK            0x94>,
  165                            <MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK          0x94>,
  166                            <MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC         0x94>,
  167                            <MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0         0x94>,
  168                            <MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC         0x94>,
  169                            <MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0         0x94>,
  170                            <MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK          0x94>;
  171         };
  172 
  173         pinctrl_uart1: uart1grp {
  174                 fsl,pins = <MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX         0x16>,
  175                            <MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX         0x16>;
  176         };
  177 
  178         pinctrl_uart2: uart2grp {
  179                 fsl,pins = <MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX         0x16>,
  180                            <MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX         0x16>;
  181         };
  182 
  183         pinctrl_uart3: uart3grp {
  184                 fsl,pins = <MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX         0x16>,
  185                            <MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX         0x16>;
  186         };
  187 
  188         pinctrl_uart4: uart4grp {
  189                 fsl,pins = <MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX         0x16>,
  190                            <MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX         0x16>;
  191         };
  192 
  193         pinctrl_usb0hub_sel: usb0hub-selgrp {
  194                 /* SEL_USB_HUB_B */
  195                 fsl,pins = <MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1              0x84>;
  196         };
  197 
  198         pinctrl_usbotg: usbotggrp {
  199                 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR        0x84>,
  200                            <MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC         0x84>,
  201                            <MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID         0x1C4>;
  202         };
  203 
  204         pinctrl_usdhc2: usdhc2grp {
  205                 fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
  206                            <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
  207                            <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
  208                            <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
  209                            <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
  210                            <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
  211                            <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
  212         };
  213 
  214         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  215                 fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
  216                            <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
  217                            <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
  218                            <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
  219                            <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
  220                            <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
  221                            <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
  222         };
  223 
  224         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  225                 fsl,pins = <MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK             0x1d4>,
  226                            <MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD             0x1d4>,
  227                            <MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0         0x1d4>,
  228                            <MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1         0x1d4>,
  229                            <MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2         0x1d4>,
  230                            <MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3         0x1d4>,
  231                            <MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0x84>;
  232         };
  233 
  234         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
  235                 fsl,pins = <MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12            0x84>;
  236         };
  237 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mn-tqma8mqnl-mba8mx.dts