Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2 /* 3 * Copyright 2020-2021 TQ-Systems GmbH 4 */ 5 6 #include "imx8mn.dtsi" 7 8 / { 9 model = "TQ-Systems i.MX8MN TQMa8MxNL"; 10 compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; 11 12 memory@40000000 { 13 device_type = "memory"; 14 /* our minimum RAM config will be 1024 MiB */ 15 reg = <0x00000000 0x40000000 0 0x40000000>; 16 }; 17 18 /* e-MMC IO, needed for HS modes */ 19 reg_vcc1v8: regulator-vcc1v8 { 20 compatible = "regulator-fixed"; 21 regulator-name = "TQMA8MXNL_VCC1V8"; 22 regulator-min-microvolt = <1800000>; 23 regulator-max-microvolt = <1800000>; 24 }; 25 26 reg_vcc3v3: regulator-vcc3v3 { 27 compatible = "regulator-fixed"; 28 regulator-name = "TQMA8MXNL_VCC3V3"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 }; 32 33 reserved-memory { 34 #address-cells = <2>; 35 #size-cells = <2>; 36 ranges; 37 38 /* global autoconfigured region for contiguous allocations */ 39 linux,cma { 40 compatible = "shared-dma-pool"; 41 reusable; 42 /* 640 MiB */ 43 size = <0 0x28000000>; 44 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */ 45 alloc-ranges = <0 0x40000000 0 0x78000000>; 46 linux,cma-default; 47 }; 48 }; 49 }; 50 51 &A53_0 { 52 cpu-supply = <&buck2_reg>; 53 }; 54 55 &flexspi { 56 pinctrl-names = "default"; 57 pinctrl-0 = <&pinctrl_flexspi>; 58 status = "okay"; 59 60 flash0: flash@0 { 61 compatible = "jedec,spi-nor"; 62 reg = <0>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 spi-max-frequency = <84000000>; 66 spi-tx-bus-width = <1>; 67 spi-rx-bus-width = <4>; 68 }; 69 }; 70 71 &i2c1 { 72 clock-frequency = <100000>; 73 pinctrl-names = "default", "gpio"; 74 pinctrl-0 = <&pinctrl_i2c1>; 75 pinctrl-1 = <&pinctrl_i2c1_gpio>; 76 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 77 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 78 status = "okay"; 79 80 sensor0: temperature-sensor-eeprom@1b { 81 compatible = "nxp,se97", "jedec,jc-42.4-temp"; 82 reg = <0x1b>; 83 }; 84 85 pca9450: pmic@25 { 86 compatible = "nxp,pca9450a"; 87 reg = <0x25>; 88 89 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */ 90 pinctrl-0 = <&pinctrl_pmic>; 91 pinctrl-names = "default"; 92 interrupt-parent = <&gpio1>; 93 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 94 95 regulators { 96 /* V_0V85_SOC: 0.85 .. 0.95 */ 97 buck1_reg: BUCK1 { 98 regulator-name = "BUCK1"; 99 regulator-min-microvolt = <850000>; 100 regulator-max-microvolt = <950000>; 101 regulator-boot-on; 102 regulator-always-on; 103 regulator-ramp-delay = <3125>; 104 }; 105 106 /* VDD_ARM */ 107 buck2_reg: BUCK2 { 108 regulator-name = "BUCK2"; 109 regulator-min-microvolt = <850000>; 110 regulator-max-microvolt = <1000000>; 111 regulator-boot-on; 112 regulator-always-on; 113 nxp,dvs-run-voltage = <950000>; 114 nxp,dvs-standby-voltage = <850000>; 115 regulator-ramp-delay = <3125>; 116 }; 117 118 /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */ 119 buck3_reg: BUCK3 { 120 regulator-name = "BUCK3"; 121 regulator-min-microvolt = <850000>; 122 regulator-max-microvolt = <950000>; 123 regulator-boot-on; 124 regulator-always-on; 125 regulator-ramp-delay = <3125>; 126 }; 127 128 /* VCC3V3 -> VMMC, ... must not be changed */ 129 buck4_reg: BUCK4 { 130 regulator-name = "BUCK4"; 131 regulator-min-microvolt = <3300000>; 132 regulator-max-microvolt = <3300000>; 133 regulator-boot-on; 134 regulator-always-on; 135 }; 136 137 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */ 138 buck5_reg: BUCK5 { 139 regulator-name = "BUCK5"; 140 regulator-min-microvolt = <1800000>; 141 regulator-max-microvolt = <1800000>; 142 regulator-boot-on; 143 regulator-always-on; 144 }; 145 146 /* V_1V1 -> RAM, ... must not be changed */ 147 buck6_reg: BUCK6 { 148 regulator-name = "BUCK6"; 149 regulator-min-microvolt = <1100000>; 150 regulator-max-microvolt = <1100000>; 151 regulator-boot-on; 152 regulator-always-on; 153 }; 154 155 /* V_1V8_SNVS */ 156 ldo1_reg: LDO1 { 157 regulator-name = "LDO1"; 158 regulator-min-microvolt = <1800000>; 159 regulator-max-microvolt = <1800000>; 160 regulator-boot-on; 161 regulator-always-on; 162 }; 163 164 /* V_0V8_SNVS */ 165 ldo2_reg: LDO2 { 166 regulator-name = "LDO2"; 167 regulator-min-microvolt = <800000>; 168 regulator-max-microvolt = <850000>; 169 regulator-boot-on; 170 regulator-always-on; 171 }; 172 173 /* V_1V8_ANA */ 174 ldo3_reg: LDO3 { 175 regulator-name = "LDO3"; 176 regulator-min-microvolt = <1800000>; 177 regulator-max-microvolt = <1800000>; 178 regulator-boot-on; 179 regulator-always-on; 180 }; 181 182 /* V_0V9_MIPI */ 183 ldo4_reg: LDO4 { 184 regulator-name = "LDO4"; 185 regulator-min-microvolt = <900000>; 186 regulator-max-microvolt = <900000>; 187 regulator-boot-on; 188 regulator-always-on; 189 }; 190 191 /* VCC SD IO - switched using SD2 VSELECT */ 192 ldo5_reg: LDO5 { 193 regulator-name = "LDO5"; 194 regulator-min-microvolt = <1800000>; 195 regulator-max-microvolt = <3300000>; 196 }; 197 }; 198 }; 199 200 pcf85063: rtc@51 { 201 compatible = "nxp,pcf85063a"; 202 reg = <0x51>; 203 quartz-load-femtofarads = <7000>; 204 }; 205 206 eeprom1: eeprom@53 { 207 compatible = "nxp,se97b", "atmel,24c02"; 208 read-only; 209 reg = <0x53>; 210 pagesize = <16>; 211 }; 212 213 eeprom0: eeprom@57 { 214 compatible = "atmel,24c64"; 215 reg = <0x57>; 216 pagesize = <32>; 217 }; 218 }; 219 220 &usdhc3 { 221 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 222 pinctrl-0 = <&pinctrl_usdhc3>; 223 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 224 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 225 bus-width = <8>; 226 non-removable; 227 no-sd; 228 no-sdio; 229 vmmc-supply = <®_vcc3v3>; 230 vqmmc-supply = <®_vcc1v8>; 231 status = "okay"; 232 }; 233 234 /* 235 * Attention: 236 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR 237 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO. 238 */ 239 &wdog1 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_wdog>; 242 fsl,ext-reset-output; 243 status = "okay"; 244 }; 245 246 &iomuxc { 247 pinctrl_flexspi: flexspigrp { 248 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>, 249 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>, 250 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>, 251 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>, 252 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>, 253 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>; 254 }; 255 256 pinctrl_i2c1: i2c1grp { 257 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>, 258 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>; 259 }; 260 261 pinctrl_i2c1_gpio: i2c1gpiogrp { 262 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>, 263 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>; 264 }; 265 266 pinctrl_pmic: pmicgrp { 267 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; 268 }; 269 270 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 271 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>; 272 }; 273 274 pinctrl_usdhc3: usdhc3grp { 275 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>, 276 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 277 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 278 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 279 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 280 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 281 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 282 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 283 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 284 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 285 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 286 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 287 }; 288 289 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 290 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>, 291 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 292 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 293 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 294 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 295 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 296 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 297 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 298 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 299 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 300 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 301 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 302 }; 303 304 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 305 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>, 306 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>, 307 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>, 308 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>, 309 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>, 310 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>, 311 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>, 312 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>, 313 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>, 314 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>, 315 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>, 316 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>; 317 }; 318 319 pinctrl_wdog: wdoggrp { 320 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>; 321 }; 322 };
Cache object: 9375cd1c9aefe9c8b3d0c8dcc8277b3b
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