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sys/contrib/device-tree/src/arm64/freescale/imx8mn-venice-gw7902.dts
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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6 /dts-v1/; 7 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/linux-event-codes.h> 10 #include <dt-bindings/leds/common.h> 11 #include <dt-bindings/net/ti-dp83867.h> 12 13 #include "imx8mn.dtsi" 14 15 / { 16 model = "Gateworks Venice GW7902 i.MX8MN board"; 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn"; 18 19 aliases { 20 usb0 = &usbotg1; 21 }; 22 23 chosen { 24 stdout-path = &uart2; 25 }; 26 27 memory@40000000 { 28 device_type = "memory"; 29 reg = <0x0 0x40000000 0 0x80000000>; 30 }; 31 32 can20m: can20m { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <20000000>; 36 clock-output-names = "can20m"; 37 }; 38 39 gpio-keys { 40 compatible = "gpio-keys"; 41 42 key-user-pb { 43 label = "user_pb"; 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 45 linux,code = <BTN_0>; 46 }; 47 48 key-user-pb1x { 49 label = "user_pb1x"; 50 linux,code = <BTN_1>; 51 interrupt-parent = <&gsc>; 52 interrupts = <0>; 53 }; 54 55 key-erased { 56 label = "key_erased"; 57 linux,code = <BTN_2>; 58 interrupt-parent = <&gsc>; 59 interrupts = <1>; 60 }; 61 62 key-eeprom-wp { 63 label = "eeprom_wp"; 64 linux,code = <BTN_3>; 65 interrupt-parent = <&gsc>; 66 interrupts = <2>; 67 }; 68 69 key-tamper { 70 label = "tamper"; 71 linux,code = <BTN_4>; 72 interrupt-parent = <&gsc>; 73 interrupts = <5>; 74 }; 75 76 switch-hold { 77 label = "switch_hold"; 78 linux,code = <BTN_5>; 79 interrupt-parent = <&gsc>; 80 interrupts = <7>; 81 }; 82 }; 83 84 led-controller { 85 compatible = "gpio-leds"; 86 pinctrl-names = "default"; 87 pinctrl-0 = <&pinctrl_gpio_leds>; 88 89 led-0 { 90 function = LED_FUNCTION_STATUS; 91 color = <LED_COLOR_ID_GREEN>; 92 label = "panel1"; 93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; 94 default-state = "off"; 95 }; 96 97 led-1 { 98 function = LED_FUNCTION_STATUS; 99 color = <LED_COLOR_ID_GREEN>; 100 label = "panel2"; 101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 102 default-state = "off"; 103 }; 104 105 led-2 { 106 function = LED_FUNCTION_STATUS; 107 color = <LED_COLOR_ID_GREEN>; 108 label = "panel3"; 109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 110 default-state = "off"; 111 }; 112 113 led-3 { 114 function = LED_FUNCTION_STATUS; 115 color = <LED_COLOR_ID_GREEN>; 116 label = "panel4"; 117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; 118 default-state = "off"; 119 }; 120 121 led-4 { 122 function = LED_FUNCTION_STATUS; 123 color = <LED_COLOR_ID_GREEN>; 124 label = "panel5"; 125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; 126 default-state = "off"; 127 }; 128 }; 129 130 pps { 131 compatible = "pps-gpio"; 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_pps>; 134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; 135 status = "okay"; 136 }; 137 138 reg_3p3v: regulator-3p3v { 139 compatible = "regulator-fixed"; 140 regulator-name = "3P3V"; 141 regulator-min-microvolt = <3300000>; 142 regulator-max-microvolt = <3300000>; 143 regulator-always-on; 144 }; 145 146 reg_usb1_vbus: regulator-usb1 { 147 compatible = "regulator-fixed"; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_reg_usb1>; 150 regulator-name = "usb_usb1_vbus"; 151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; 152 enable-active-high; 153 regulator-min-microvolt = <5000000>; 154 regulator-max-microvolt = <5000000>; 155 }; 156 157 reg_wifi: regulator-wifi { 158 compatible = "regulator-fixed"; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_reg_wl>; 161 regulator-name = "wifi"; 162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 163 enable-active-high; 164 startup-delay-us = <100>; 165 regulator-min-microvolt = <3300000>; 166 regulator-max-microvolt = <3300000>; 167 }; 168 }; 169 170 &A53_0 { 171 cpu-supply = <&buck2>; 172 }; 173 174 &A53_1 { 175 cpu-supply = <&buck2>; 176 }; 177 178 &A53_2 { 179 cpu-supply = <&buck2>; 180 }; 181 182 &A53_3 { 183 cpu-supply = <&buck2>; 184 }; 185 186 &ddrc { 187 operating-points-v2 = <&ddrc_opp_table>; 188 189 ddrc_opp_table: opp-table { 190 compatible = "operating-points-v2"; 191 192 opp-25M { 193 opp-hz = /bits/ 64 <25000000>; 194 }; 195 196 opp-100M { 197 opp-hz = /bits/ 64 <100000000>; 198 }; 199 200 opp-750M { 201 opp-hz = /bits/ 64 <750000000>; 202 }; 203 }; 204 }; 205 206 &ecspi1 { 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_spi1>; 209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 210 status = "okay"; 211 212 can@0 { 213 compatible = "microchip,mcp2515"; 214 reg = <0>; 215 clocks = <&can20m>; 216 oscillator-frequency = <20000000>; 217 interrupt-parent = <&gpio2>; 218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 219 spi-max-frequency = <10000000>; 220 }; 221 }; 222 223 &disp_blk_ctrl { 224 status = "disabled"; 225 }; 226 227 /* off-board header */ 228 &ecspi2 { 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_spi2>; 231 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 232 status = "okay"; 233 }; 234 235 &fec1 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_fec1>; 238 phy-mode = "rgmii-id"; 239 phy-handle = <ðphy0>; 240 local-mac-address = [00 00 00 00 00 00]; 241 status = "okay"; 242 243 mdio { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 ethphy0: ethernet-phy@0 { 248 compatible = "ethernet-phy-ieee802.3-c22"; 249 reg = <0>; 250 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 251 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 252 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 253 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 254 }; 255 }; 256 }; 257 258 &gpio1 { 259 gpio-line-names = "", "", "", "", "", "", "", "", 260 "", "", "", "", "", "m2_reset", "", "m2_wdis#", 261 "", "", "", "", "", "", "", "", 262 "", "", "", "", "", "", "", ""; 263 }; 264 265 &gpio2 { 266 gpio-line-names = "", "", "", "", "", "", "", "", 267 "uart2_en#", "", "", "", "", "", "", "", 268 "", "", "", "", "", "", "", "", 269 "", "", "", "", "", "", "", ""; 270 }; 271 272 &gpio3 { 273 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#", 274 "", "", "", "", "", "", "", "", 275 "", "", "", "", "", "", "", "", 276 "", "", "", "", "", "", "", ""; 277 }; 278 279 &gpio4 { 280 gpio-line-names = "", "", "", "", "", "", "", "", 281 "", "", "", "", "", "", "", "", 282 "", "", "", "", "", "app_gpio1", "", "uart1_rs485", 283 "", "uart1_term", "uart1_half", "app_gpio2", 284 "mipi_gpio1", "", "", ""; 285 }; 286 287 &gpio5 { 288 gpio-line-names = "", "", "", "mipi_gpio4", 289 "mipi_gpio3", "mipi_gpio2", "", "", 290 "", "", "", "", "", "", "", "", 291 "", "", "", "", "", "", "", "", 292 "", "", "", "", "", "", "", ""; 293 }; 294 295 &gpu { 296 status = "disabled"; 297 }; 298 299 &i2c1 { 300 clock-frequency = <100000>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_i2c1>; 303 status = "okay"; 304 305 gsc: gsc@20 { 306 compatible = "gw,gsc"; 307 reg = <0x20>; 308 pinctrl-0 = <&pinctrl_gsc>; 309 interrupt-parent = <&gpio2>; 310 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 311 interrupt-controller; 312 #interrupt-cells = <1>; 313 314 adc { 315 compatible = "gw,gsc-adc"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 319 channel@6 { 320 gw,mode = <0>; 321 reg = <0x06>; 322 label = "temp"; 323 }; 324 325 channel@8 { 326 gw,mode = <1>; 327 reg = <0x08>; 328 label = "vdd_bat"; 329 }; 330 331 channel@82 { 332 gw,mode = <2>; 333 reg = <0x82>; 334 label = "vin"; 335 gw,voltage-divider-ohms = <22100 1000>; 336 gw,voltage-offset-microvolt = <700000>; 337 }; 338 339 channel@84 { 340 gw,mode = <2>; 341 reg = <0x84>; 342 label = "vin_4p0"; 343 gw,voltage-divider-ohms = <10000 10000>; 344 }; 345 346 channel@86 { 347 gw,mode = <2>; 348 reg = <0x86>; 349 label = "vdd_3p3"; 350 gw,voltage-divider-ohms = <10000 10000>; 351 }; 352 353 channel@88 { 354 gw,mode = <2>; 355 reg = <0x88>; 356 label = "vdd_0p9"; 357 }; 358 359 channel@8c { 360 gw,mode = <2>; 361 reg = <0x8c>; 362 label = "vdd_soc"; 363 }; 364 365 channel@8e { 366 gw,mode = <2>; 367 reg = <0x8e>; 368 label = "vdd_arm"; 369 }; 370 371 channel@90 { 372 gw,mode = <2>; 373 reg = <0x90>; 374 label = "vdd_1p8"; 375 }; 376 377 channel@92 { 378 gw,mode = <2>; 379 reg = <0x92>; 380 label = "vdd_dram"; 381 }; 382 383 channel@98 { 384 gw,mode = <2>; 385 reg = <0x98>; 386 label = "vdd_1p0"; 387 }; 388 389 channel@9a { 390 gw,mode = <2>; 391 reg = <0x9a>; 392 label = "vdd_2p5"; 393 gw,voltage-divider-ohms = <10000 10000>; 394 }; 395 396 channel@9c { 397 gw,mode = <2>; 398 reg = <0x9c>; 399 label = "vdd_5p0"; 400 gw,voltage-divider-ohms = <10000 10000>; 401 }; 402 403 channel@a2 { 404 gw,mode = <2>; 405 reg = <0xa2>; 406 label = "vdd_gsc"; 407 gw,voltage-divider-ohms = <10000 10000>; 408 }; 409 }; 410 }; 411 412 gpio: gpio@23 { 413 compatible = "nxp,pca9555"; 414 reg = <0x23>; 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-parent = <&gsc>; 418 interrupts = <4>; 419 }; 420 421 pmic@4b { 422 compatible = "rohm,bd71847"; 423 reg = <0x4b>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pinctrl_pmic>; 426 interrupt-parent = <&gpio3>; 427 interrupts = <8 IRQ_TYPE_LEVEL_LOW>; 428 rohm,reset-snvs-powered; 429 #clock-cells = <0>; 430 clocks = <&osc_32k 0>; 431 clock-output-names = "clk-32k-out"; 432 433 regulators { 434 /* vdd_soc: 0.805-0.900V (typ=0.8V) */ 435 BUCK1 { 436 regulator-name = "buck1"; 437 regulator-min-microvolt = <700000>; 438 regulator-max-microvolt = <1300000>; 439 regulator-boot-on; 440 regulator-always-on; 441 regulator-ramp-delay = <1250>; 442 }; 443 444 /* vdd_arm: 0.805-1.0V (typ=0.9V) */ 445 buck2: BUCK2 { 446 regulator-name = "buck2"; 447 regulator-min-microvolt = <700000>; 448 regulator-max-microvolt = <1300000>; 449 regulator-boot-on; 450 regulator-always-on; 451 regulator-ramp-delay = <1250>; 452 rohm,dvs-run-voltage = <1000000>; 453 rohm,dvs-idle-voltage = <900000>; 454 }; 455 456 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */ 457 BUCK3 { 458 regulator-name = "buck3"; 459 regulator-min-microvolt = <700000>; 460 regulator-max-microvolt = <1350000>; 461 regulator-boot-on; 462 regulator-always-on; 463 }; 464 465 /* vdd_3p3 */ 466 BUCK4 { 467 regulator-name = "buck4"; 468 regulator-min-microvolt = <3000000>; 469 regulator-max-microvolt = <3300000>; 470 regulator-boot-on; 471 regulator-always-on; 472 }; 473 474 /* vdd_1p8 */ 475 BUCK5 { 476 regulator-name = "buck5"; 477 regulator-min-microvolt = <1605000>; 478 regulator-max-microvolt = <1995000>; 479 regulator-boot-on; 480 regulator-always-on; 481 }; 482 483 /* vdd_dram */ 484 BUCK6 { 485 regulator-name = "buck6"; 486 regulator-min-microvolt = <800000>; 487 regulator-max-microvolt = <1400000>; 488 regulator-boot-on; 489 regulator-always-on; 490 }; 491 492 /* nvcc_snvs_1p8 */ 493 LDO1 { 494 regulator-name = "ldo1"; 495 regulator-min-microvolt = <1600000>; 496 regulator-max-microvolt = <1900000>; 497 regulator-boot-on; 498 regulator-always-on; 499 }; 500 501 /* vdd_snvs_0p8 */ 502 LDO2 { 503 regulator-name = "ldo2"; 504 regulator-min-microvolt = <800000>; 505 regulator-max-microvolt = <900000>; 506 regulator-boot-on; 507 regulator-always-on; 508 }; 509 510 /* vdda_1p8 */ 511 LDO3 { 512 regulator-name = "ldo3"; 513 regulator-min-microvolt = <1800000>; 514 regulator-max-microvolt = <3300000>; 515 regulator-boot-on; 516 regulator-always-on; 517 }; 518 519 LDO4 { 520 regulator-name = "ldo4"; 521 regulator-min-microvolt = <900000>; 522 regulator-max-microvolt = <1800000>; 523 regulator-boot-on; 524 regulator-always-on; 525 }; 526 527 LDO6 { 528 regulator-name = "ldo6"; 529 regulator-min-microvolt = <900000>; 530 regulator-max-microvolt = <1800000>; 531 regulator-boot-on; 532 regulator-always-on; 533 }; 534 }; 535 }; 536 537 eeprom@50 { 538 compatible = "atmel,24c02"; 539 reg = <0x50>; 540 pagesize = <16>; 541 }; 542 543 eeprom@51 { 544 compatible = "atmel,24c02"; 545 reg = <0x51>; 546 pagesize = <16>; 547 }; 548 549 eeprom@52 { 550 compatible = "atmel,24c02"; 551 reg = <0x52>; 552 pagesize = <16>; 553 }; 554 555 eeprom@53 { 556 compatible = "atmel,24c02"; 557 reg = <0x53>; 558 pagesize = <16>; 559 }; 560 561 rtc@68 { 562 compatible = "dallas,ds1672"; 563 reg = <0x68>; 564 }; 565 }; 566 567 &i2c2 { 568 clock-frequency = <400000>; 569 pinctrl-names = "default"; 570 pinctrl-0 = <&pinctrl_i2c2>; 571 status = "okay"; 572 573 accelerometer@19 { 574 compatible = "st,lis2de12"; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&pinctrl_accel>; 577 reg = <0x19>; 578 st,drdy-int-pin = <1>; 579 interrupt-parent = <&gpio1>; 580 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 581 interrupt-names = "INT1"; 582 }; 583 }; 584 585 /* off-board header */ 586 &i2c3 { 587 clock-frequency = <400000>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_i2c3>; 590 status = "okay"; 591 }; 592 593 /* off-board header */ 594 &i2c4 { 595 clock-frequency = <400000>; 596 pinctrl-names = "default"; 597 pinctrl-0 = <&pinctrl_i2c4>; 598 status = "okay"; 599 }; 600 601 &pgc_gpumix { 602 status = "disabled"; 603 }; 604 605 /* off-board header */ 606 &sai3 { 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_sai3>; 609 assigned-clocks = <&clk IMX8MN_CLK_SAI3>; 610 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; 611 assigned-clock-rates = <24576000>; 612 status = "okay"; 613 }; 614 615 /* RS232/RS485/RS422 selectable */ 616 &uart1 { 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; 619 status = "okay"; 620 }; 621 622 /* RS232 console */ 623 &uart2 { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_uart2>; 626 status = "okay"; 627 }; 628 629 /* bluetooth HCI */ 630 &uart3 { 631 pinctrl-names = "default"; 632 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; 633 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 634 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 635 uart-has-rtscts; 636 status = "okay"; 637 638 bluetooth { 639 compatible = "brcm,bcm4330-bt"; 640 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 641 }; 642 }; 643 644 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */ 645 &uart4 { 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_uart4>; 648 status = "okay"; 649 }; 650 651 &usbotg1 { 652 dr_mode = "host"; 653 vbus-supply = <®_usb1_vbus>; 654 disable-over-current; 655 status = "okay"; 656 }; 657 658 /* SDIO WiFi */ 659 &usdhc2 { 660 pinctrl-names = "default"; 661 pinctrl-0 = <&pinctrl_usdhc2>; 662 bus-width = <4>; 663 non-removable; 664 vmmc-supply = <®_wifi>; 665 status = "okay"; 666 }; 667 668 /* eMMC */ 669 &usdhc3 { 670 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 671 pinctrl-0 = <&pinctrl_usdhc3>; 672 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 673 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 674 bus-width = <8>; 675 non-removable; 676 status = "okay"; 677 }; 678 679 &wdog1 { 680 pinctrl-names = "default"; 681 pinctrl-0 = <&pinctrl_wdog>; 682 fsl,ext-reset-output; 683 status = "okay"; 684 }; 685 686 &iomuxc { 687 pinctrl-names = "default"; 688 pinctrl-0 = <&pinctrl_hog>; 689 690 pinctrl_hog: hoggrp { 691 fsl,pins = < 692 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */ 693 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */ 694 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */ 695 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */ 696 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */ 697 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */ 698 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */ 699 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */ 700 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */ 701 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */ 702 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */ 703 >; 704 }; 705 706 pinctrl_accel: accelgrp { 707 fsl,pins = < 708 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159 709 >; 710 }; 711 712 pinctrl_fec1: fec1grp { 713 fsl,pins = < 714 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 715 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 716 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 717 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 718 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 719 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 720 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 721 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 722 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 723 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 724 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 725 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 726 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 727 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 728 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */ 729 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */ 730 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141 731 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141 732 >; 733 }; 734 735 pinctrl_gsc: gscgrp { 736 fsl,pins = < 737 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40 738 >; 739 }; 740 741 pinctrl_i2c1: i2c1grp { 742 fsl,pins = < 743 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 744 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 745 >; 746 }; 747 748 pinctrl_i2c2: i2c2grp { 749 fsl,pins = < 750 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 751 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 752 >; 753 }; 754 755 pinctrl_i2c3: i2c3grp { 756 fsl,pins = < 757 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 758 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 759 >; 760 }; 761 762 pinctrl_i2c4: i2c4grp { 763 fsl,pins = < 764 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 765 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 766 >; 767 }; 768 769 pinctrl_gpio_leds: gpioledgrp { 770 fsl,pins = < 771 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 772 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 773 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 774 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 775 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 776 >; 777 }; 778 779 pinctrl_pmic: pmicgrp { 780 fsl,pins = < 781 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41 782 >; 783 }; 784 785 pinctrl_pps: ppsgrp { 786 fsl,pins = < 787 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */ 788 >; 789 }; 790 791 pinctrl_reg_wl: regwlgrp { 792 fsl,pins = < 793 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */ 794 >; 795 }; 796 797 pinctrl_reg_usb1: regusb1grp { 798 fsl,pins = < 799 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41 800 >; 801 }; 802 803 pinctrl_sai3: sai3grp { 804 fsl,pins = < 805 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6 806 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6 807 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 808 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 809 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 810 >; 811 }; 812 813 pinctrl_spi1: spi1grp { 814 fsl,pins = < 815 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 816 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 817 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 818 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 819 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */ 820 >; 821 }; 822 823 pinctrl_spi2: spi2grp { 824 fsl,pins = < 825 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 826 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 827 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 828 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */ 829 >; 830 }; 831 832 pinctrl_uart1: uart1grp { 833 fsl,pins = < 834 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 835 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 836 >; 837 }; 838 839 pinctrl_uart1_gpio: uart1gpiogrp { 840 fsl,pins = < 841 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */ 842 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */ 843 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */ 844 >; 845 }; 846 847 pinctrl_uart2: uart2grp { 848 fsl,pins = < 849 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 850 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 851 >; 852 }; 853 854 pinctrl_uart3_gpio: uart3_gpiogrp { 855 fsl,pins = < 856 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */ 857 >; 858 }; 859 860 pinctrl_uart3: uart3grp { 861 fsl,pins = < 862 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 863 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 864 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */ 865 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */ 866 >; 867 }; 868 869 pinctrl_uart4: uart4grp { 870 fsl,pins = < 871 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 872 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 873 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */ 874 >; 875 }; 876 877 pinctrl_usdhc2: usdhc2grp { 878 fsl,pins = < 879 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 880 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 881 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 882 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 883 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 884 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 885 >; 886 }; 887 888 pinctrl_usdhc3: usdhc3grp { 889 fsl,pins = < 890 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 891 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 892 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 893 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 894 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 895 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 896 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 897 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 898 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 899 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 900 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 901 >; 902 }; 903 904 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 905 fsl,pins = < 906 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 907 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 908 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 909 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 910 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 911 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 912 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 913 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 914 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 915 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 916 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 917 >; 918 }; 919 920 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 921 fsl,pins = < 922 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 923 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 924 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 925 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 926 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 927 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 928 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 929 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 930 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 931 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 932 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 933 >; 934 }; 935 936 pinctrl_wdog: wdoggrp { 937 fsl,pins = < 938 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 939 >; 940 }; 941 };
Cache object: 08bf48d2103f0534e6988c35d3b424c5
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