imx8mp-tqma8mpql-mba8mpxl.dts

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    1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
    2 /*
    3  * Copyright 2021-2022 TQ-Systems GmbH
    4  * Author: Alexander Stein <alexander.stein@tq-group.com>
    5  */
    6 
    7 /dts-v1/;
    8 
    9 #include <dt-bindings/leds/common.h>
   10 #include <dt-bindings/net/ti-dp83867.h>
   11 #include <dt-bindings/pwm/pwm.h>
   12 #include "imx8mp-tqma8mpql.dtsi"
   13 
   14 / {
   15         model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
   16         compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
   17 
   18         chosen {
   19                 stdout-path = &uart4;
   20         };
   21 
   22         iio-hwmon {
   23                 compatible = "iio-hwmon";
   24                 io-channels = <&adc 0>, <&adc 1>;
   25         };
   26 
   27         aliases {
   28                 mmc0 = &usdhc3;
   29                 mmc1 = &usdhc2;
   30                 mmc2 = &usdhc1;
   31                 rtc0 = &pcf85063;
   32                 rtc1 = &snvs_rtc;
   33                 spi0 = &flexspi;
   34                 spi1 = &ecspi1;
   35                 spi2 = &ecspi2;
   36                 spi3 = &ecspi3;
   37         };
   38 
   39         backlight_lvds: backlight {
   40                 compatible = "pwm-backlight";
   41                 pinctrl-names = "default";
   42                 pinctrl-0 = <&pinctrl_backlight>;
   43                 pwms = <&pwm2 0 5000000 0>;
   44                 brightness-levels = <0 4 8 16 32 64 128 255>;
   45                 default-brightness-level = <7>;
   46                 power-supply = <&reg_vcc_12v0>;
   47                 enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
   48                 status = "disabled";
   49         };
   50 
   51         gpio-keys {
   52                 compatible = "gpio-keys";
   53                 pinctrl-names = "default";
   54                 pinctrl-0 = <&pinctrl_gpiobutton>;
   55                 autorepeat;
   56 
   57                 switch-1 {
   58                         label = "S12";
   59                         linux,code = <BTN_0>;
   60                         gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
   61                 };
   62 
   63                 switch-2 {
   64                         label = "S13";
   65                         linux,code = <BTN_1>;
   66                         gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
   67                 };
   68         };
   69 
   70         gpio-leds {
   71                 compatible = "gpio-leds";
   72                 pinctrl-names = "default";
   73                 pinctrl-0 = <&pinctrl_gpioled>;
   74 
   75                 led-0 {
   76                         color = <LED_COLOR_ID_GREEN>;
   77                         function = LED_FUNCTION_STATUS;
   78                         function-enumerator = <0>;
   79                         gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
   80                         linux,default-trigger = "default-on";
   81                 };
   82 
   83                 led-1 {
   84                         color = <LED_COLOR_ID_GREEN>;
   85                         function = LED_FUNCTION_HEARTBEAT;
   86                         gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
   87                         linux,default-trigger = "heartbeat";
   88                 };
   89 
   90                 led-2 {
   91                         color = <LED_COLOR_ID_YELLOW>;
   92                         function = LED_FUNCTION_STATUS;
   93                         function-enumerator = <1>;
   94                         gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
   95                 };
   96         };
   97 
   98         display: display {
   99                 /*
  100                  * Display is not fixed, so compatible has to be added from
  101                  * DT overlay
  102                  */
  103                 pinctrl-names = "default";
  104                 pinctrl-0 = <&pinctrl_lvdsdisplay>;
  105                 power-supply = <&reg_vcc_3v3>;
  106                 enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
  107                 backlight = <&backlight_lvds>;
  108                 status = "disabled";
  109         };
  110 
  111         reg_usdhc2_vmmc: regulator-usdhc2 {
  112                 compatible = "regulator-fixed";
  113                 pinctrl-names = "default";
  114                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  115                 regulator-name = "VSD_3V3";
  116                 regulator-min-microvolt = <3300000>;
  117                 regulator-max-microvolt = <3300000>;
  118                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  119                 enable-active-high;
  120                 startup-delay-us = <100>;
  121                 off-on-delay-us = <12000>;
  122         };
  123 
  124         reg_vcc_12v0: regulator-12v0 {
  125                 compatible = "regulator-fixed";
  126                 pinctrl-names = "default";
  127                 pinctrl-0 = <&pinctrl_reg12v0>;
  128                 regulator-name = "VCC_12V0";
  129                 regulator-min-microvolt = <12000000>;
  130                 regulator-max-microvolt = <12000000>;
  131                 gpio = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  132                 enable-active-high;
  133         };
  134 
  135         reg_vcc_3v3: regulator-3v3 {
  136                 compatible = "regulator-fixed";
  137                 regulator-name = "VCC_3V3";
  138                 regulator-min-microvolt = <3300000>;
  139                 regulator-max-microvolt = <3300000>;
  140         };
  141 
  142         reserved-memory {
  143                 #address-cells = <2>;
  144                 #size-cells = <2>;
  145                 ranges;
  146 
  147                 ocram: ocram@900000 {
  148                         no-map;
  149                         reg = <0 0x900000 0 0x70000>;
  150                 };
  151 
  152                 /* global autoconfigured region for contiguous allocations */
  153                 linux,cma {
  154                         compatible = "shared-dma-pool";
  155                         reusable;
  156                         size = <0 0x38000000>;
  157                         alloc-ranges = <0 0x40000000 0 0xB0000000>;
  158                         linux,cma-default;
  159                 };
  160         };
  161 };
  162 
  163 &ecspi1 {
  164         pinctrl-names = "default";
  165         pinctrl-0 = <&pinctrl_ecspi1>;
  166         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
  167         status = "okay";
  168 };
  169 
  170 &ecspi2 {
  171         pinctrl-names = "default";
  172         pinctrl-0 = <&pinctrl_ecspi2>;
  173         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  174         status = "okay";
  175 };
  176 
  177 &ecspi3 {
  178         pinctrl-names = "default";
  179         pinctrl-0 = <&pinctrl_ecspi3>;
  180         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
  181         status = "okay";
  182 
  183         adc: adc@0 {
  184                 reg = <0>;
  185                 compatible = "microchip,mcp3202";
  186                 /* 100 ksps * 18 */
  187                 spi-max-frequency = <1800000>;
  188                 vref-supply = <&reg_vcc_3v3>;
  189                 #io-channel-cells = <1>;
  190         };
  191 };
  192 
  193 &eqos {
  194         pinctrl-names = "default";
  195         pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eqos_phy>;
  196         phy-mode = "rgmii-id";
  197         phy-handle = <&ethphy3>;
  198         status = "okay";
  199 
  200         mdio {
  201                 compatible = "snps,dwmac-mdio";
  202                 #address-cells = <1>;
  203                 #size-cells = <0>;
  204 
  205                 ethphy3: ethernet-phy@3 {
  206                         compatible = "ethernet-phy-ieee802.3-c22";
  207                         reg = <3>;
  208                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  209                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  210                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  211                         ti,dp83867-rxctrl-strap-quirk;
  212                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
  213                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
  214                         reset-assert-us = <500000>;
  215                         reset-deassert-us = <50000>;
  216                         enet-phy-lane-no-swap;
  217                         interrupt-parent = <&gpio4>;
  218                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  219                 };
  220         };
  221 };
  222 
  223 &fec {
  224         pinctrl-names = "default";
  225         pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy>;
  226         phy-mode = "rgmii-id";
  227         phy-handle = <&ethphy0>;
  228         fsl,magic-packet;
  229         status = "okay";
  230 
  231         mdio {
  232                 #address-cells = <1>;
  233                 #size-cells = <0>;
  234 
  235                 ethphy0: ethernet-phy@0 {
  236                         compatible = "ethernet-phy-ieee802.3-c22";
  237                         reg = <0>;
  238                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  239                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  240                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  241                         ti,dp83867-rxctrl-strap-quirk;
  242                         ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
  243                         reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
  244                         reset-assert-us = <500000>;
  245                         reset-deassert-us = <50000>;
  246                         enet-phy-lane-no-swap;
  247                         interrupt-parent = <&gpio4>;
  248                         interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
  249                 };
  250         };
  251 };
  252 
  253 &flexcan1 {
  254         pinctrl-names = "default";
  255         pinctrl-0 = <&pinctrl_flexcan1>;
  256         xceiver-supply = <&reg_vcc_3v3>;
  257         status = "okay";
  258 };
  259 
  260 &flexcan2 {
  261         pinctrl-names = "default";
  262         pinctrl-0 = <&pinctrl_flexcan2>;
  263         xceiver-supply = <&reg_vcc_3v3>;
  264         status = "okay";
  265 };
  266 
  267 &gpio1 {
  268         pinctrl-names = "default";
  269         pinctrl-0 = <&pinctrl_gpio1>;
  270 
  271         gpio-line-names = "GPO1", "GPO0", "", "GPO3",
  272                           "", "", "GPO2", "GPI0",
  273                           "PMIC_IRQ", "GPI1", "OTG_ID", "USB_HUB_RST#",
  274                           "OTG_PWR", "", "GPI2", "GPI3",
  275                           "", "", "", "",
  276                           "", "", "", "",
  277                           "", "", "", "",
  278                           "", "", "", "";
  279 };
  280 
  281 &gpio2 {
  282         pinctrl-names = "default";
  283         pinctrl-0 = <&pinctrl_hoggpio2>;
  284 
  285         gpio-line-names = "", "", "", "",
  286                           "", "", "VCC12V_EN", "PERST#",
  287                           "", "", "CLKREQ#", "PEWAKE#",
  288                           "USDHC2_CD", "", "", "",
  289                           "", "", "", "V_SD3V3_EN",
  290                           "", "", "", "",
  291                           "", "", "", "",
  292                           "", "", "", "";
  293 
  294         perst-hog {
  295                 gpio-hog;
  296                 gpios = <7 0>;
  297                 output-high;
  298                 line-name = "PERST#";
  299         };
  300 
  301         clkreq-hog {
  302                 gpio-hog;
  303                 gpios = <10 0>;
  304                 input;
  305                 line-name = "CLKREQ#";
  306         };
  307 
  308         pewake-hog {
  309                 gpio-hog;
  310                 gpios = <11 0>;
  311                 input;
  312                 line-name = "PEWAKE#";
  313         };
  314 };
  315 
  316 &gpio3 {
  317         gpio-line-names = "", "", "", "",
  318                           "", "", "", "",
  319                           "", "", "", "",
  320                           "", "", "LVDS0_RESET#", "",
  321                           "", "", "", "LVDS0_BLT_EN",
  322                           "LVDS0_PWR_EN", "", "", "",
  323                           "", "", "", "",
  324                           "", "", "", "";
  325 };
  326 
  327 &gpio4 {
  328         pinctrl-names = "default";
  329         pinctrl-0 = <&pinctrl_gpio4>;
  330 
  331         gpio-line-names = "ENET0_RST#", "ENET0_INT#", "ENET1_RST#", "ENET1_INT#",
  332                           "", "", "", "",
  333                           "", "", "", "",
  334                           "", "", "", "",
  335                           "", "", "DP_IRQ", "DSI_EN",
  336                           "HDMI_OC#", "TEMP_EVENT#", "PCIE_CLK_OE#", "",
  337                           "", "", "", "FAN_PWR",
  338                           "RTC_EVENT#", "CODEC_RST#", "", "";
  339 };
  340 
  341 &gpio5 {
  342         gpio-line-names = "", "", "", "LED2",
  343                           "LED1", "LED0", "CSI0_RESET#", "CSI0_SYNC",
  344                           "CSI0_TRIGGER", "CSI0_ENABLE", "", "",
  345                           "", "ECSPI2_SS0", "", "",
  346                           "", "", "", "",
  347                           "", "", "", "",
  348                           "", "ECSPI3_SS0", "SWITCH_A", "SWITCH_B",
  349                           "", "", "", "";
  350 };
  351 
  352 &i2c2 {
  353         clock-frequency = <384000>;
  354         pinctrl-names = "default", "gpio";
  355         pinctrl-0 = <&pinctrl_i2c2>;
  356         pinctrl-1 = <&pinctrl_i2c2_gpio>;
  357         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  358         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  359         status = "okay";
  360 
  361         /* NXP SE97BTP with temperature sensor + eeprom */
  362         se97_1c: temperature-sensor-eeprom@1c {
  363                 compatible = "nxp,se97", "jedec,jc-42.4-temp";
  364                 reg = <0x1c>;
  365         };
  366 
  367         at24c02_54: eeprom@54 {
  368                 compatible = "nxp,se97b", "atmel,24c02";
  369                 reg = <0x54>;
  370                 pagesize = <16>;
  371                 vcc-supply = <&reg_vcc_3v3>;
  372         };
  373 };
  374 
  375 &i2c4 {
  376         clock-frequency = <384000>;
  377         pinctrl-names = "default", "gpio";
  378         pinctrl-0 = <&pinctrl_i2c4>;
  379         pinctrl-1 = <&pinctrl_i2c4_gpio>;
  380         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  381         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  382         status = "okay";
  383 };
  384 
  385 &i2c6 {
  386         clock-frequency = <384000>;
  387         pinctrl-names = "default", "gpio";
  388         pinctrl-0 = <&pinctrl_i2c6>;
  389         pinctrl-1 = <&pinctrl_i2c6_gpio>;
  390         scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  391         sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  392         status = "okay";
  393 };
  394 
  395 &pcf85063 {
  396         /* RTC_EVENT# is connected on MBa8MPxL */
  397         pinctrl-names = "default";
  398         pinctrl-0 = <&pinctrl_pcf85063>;
  399         interrupt-parent = <&gpio4>;
  400         interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
  401 };
  402 
  403 &pwm2 {
  404         pinctrl-names = "default";
  405         pinctrl-0 = <&pinctrl_pwm2>;
  406         status = "disabled";
  407 };
  408 
  409 &pwm3 {
  410         pinctrl-names = "default";
  411         pinctrl-0 = <&pinctrl_pwm3>;
  412         status = "okay";
  413 };
  414 
  415 &snvs_pwrkey {
  416         status = "okay";
  417 };
  418 
  419 &uart1 {
  420         pinctrl-names = "default";
  421         pinctrl-0 = <&pinctrl_uart1>;
  422         assigned-clocks = <&clk IMX8MP_CLK_UART1>;
  423         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
  424         status = "okay";
  425 };
  426 
  427 &uart2 {
  428         pinctrl-names = "default";
  429         pinctrl-0 = <&pinctrl_uart2>;
  430         assigned-clocks = <&clk IMX8MP_CLK_UART2>;
  431         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
  432         status = "okay";
  433 };
  434 
  435 &uart3 {
  436         pinctrl-names = "default";
  437         pinctrl-0 = <&pinctrl_uart3>;
  438         assigned-clocks = <&clk IMX8MP_CLK_UART3>;
  439         assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
  440         status = "okay";
  441 };
  442 
  443 &uart4 {
  444         /* console */
  445         pinctrl-names = "default";
  446         pinctrl-0 = <&pinctrl_uart4>;
  447         status = "okay";
  448 };
  449 
  450 &usdhc2 {
  451         pinctrl-names = "default", "state_100mhz", "state_200mhz";
  452         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  453         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  454         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  455         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  456         vmmc-supply = <&reg_usdhc2_vmmc>;
  457         no-mmc;
  458         no-sdio;
  459         disable-wp;
  460         bus-width = <4>;
  461         status = "okay";
  462 };
  463 
  464 &iomuxc {
  465         pinctrl_backlight: backlightgrp {
  466                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19          0x14>;
  467         };
  468 
  469         pinctrl_flexcan1: flexcan1grp {
  470                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX             0x150>,
  471                            <MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX             0x150>;
  472         };
  473 
  474         pinctrl_flexcan2: flexcan2grp {
  475                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX             0x150>,
  476                            <MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX             0x150>;
  477         };
  478 
  479         /* only on X57, primary used as CSI0 control signals */
  480         pinctrl_ecspi1: ecspi1grp {
  481                 fsl,pins = <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO       0x1c0>,
  482                            <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI       0x1c0>,
  483                            <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK       0x1c0>,
  484                            <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09         0x1c0>;
  485         };
  486 
  487         /* on X63 and optionally on X57, can also be used as CSI1 control signals */
  488         pinctrl_ecspi2: ecspi2grp {
  489                 fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO       0x1c0>,
  490                            <MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI       0x1c0>,
  491                            <MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK       0x1c0>,
  492                            <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13         0x1c0>;
  493         };
  494 
  495         pinctrl_ecspi3: ecspi3grp {
  496                 fsl,pins = <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI         0x1c0>,
  497                            <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK         0x1c0>,
  498                            <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO         0x1c0>,
  499                            <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25          0x1c0>;
  500         };
  501 
  502         pinctrl_eqos: eqosgrp {
  503                 fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                         0x40000044>,
  504                            <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                       0x40000044>,
  505                            <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                   0x90>,
  506                            <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                   0x90>,
  507                            <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                   0x90>,
  508                            <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                   0x90>,
  509                            <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   0x90>,
  510                            <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL             0x90>,
  511                            <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                   0x12>,
  512                            <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                   0x12>,
  513                            <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                   0x12>,
  514                            <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                   0x12>,
  515                            <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL             0x12>,
  516                            <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   0x14>;
  517         };
  518 
  519         pinctrl_eqos_event: eqosevtgrp {
  520                 fsl,pins = <MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT            0x100>,
  521                            <MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN             0x1c0>;
  522         };
  523 
  524         pinctrl_eqos_phy: eqosphygrp {
  525                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02                          0x100>,
  526                            <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03                          0x1c0>;
  527         };
  528 
  529         pinctrl_fec: fecgrp {
  530                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC           0x40000044>,
  531                            <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO          0x40000044>,
  532                            <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0     0x90>,
  533                            <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1     0x90>,
  534                            <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2     0x90>,
  535                            <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3     0x90>,
  536                            <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC      0x90>,
  537                            <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL  0x90>,
  538                            <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0     0x12>,
  539                            <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1     0x12>,
  540                            <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2     0x12>,
  541                            <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3     0x12>,
  542                            <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL  0x12>,
  543                            <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC     0x14>;
  544         };
  545 
  546         pinctrl_fec_event: fecevtgrp {
  547                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN        0x100>,
  548                            <MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT        0x1c0>;
  549         };
  550 
  551         pinctrl_fec_phy: fecphygrp {
  552                 fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00          0x100>,
  553                            <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01           0x1c0>;
  554         };
  555 
  556         pinctrl_fec_phyalt: fecphyaltgrp {
  557                 fsl,pins = <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24          0x180>,
  558                            <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25           0x180>;
  559         };
  560 
  561         pinctrl_gpiobutton: gpiobuttongrp {
  562                 fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26          0x10>,
  563                            <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27          0x10>;
  564         };
  565 
  566         pinctrl_gpioled: gpioledgrp {
  567                 fsl,pins = <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05      0x14>,
  568                            <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04           0x14>,
  569                            <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03           0x14>;
  570         };
  571 
  572         pinctrl_gpio1: gpio1grp {
  573                 fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00         0x10>,
  574                            <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01         0x10>,
  575                            <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03         0x10>,
  576                            <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06         0x10>,
  577                            <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07         0x80>,
  578                            <MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09         0x80>,
  579                            <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14         0x80>,
  580                            <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15         0x80>;
  581         };
  582 
  583         pinctrl_gpio4: gpio4grp {
  584                 fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20          0x180>,
  585                            <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22           0x180>;
  586         };
  587 
  588         pinctrl_hdmi: hdmigrp {
  589                 fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>,
  590                            <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>,
  591                            <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD     0x40000010>,
  592                            <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC     0x40000010>;
  593         };
  594 
  595         pinctrl_hoggpio2: hoggpio2grp {
  596                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07          0x140>,
  597                            <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10        0x140>,
  598                            <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11         0x140>;
  599         };
  600 
  601         pinctrl_i2c2: i2c2grp {
  602                 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL             0x400001e2>,
  603                            <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA             0x400001e2>;
  604         };
  605 
  606         pinctrl_i2c2_gpio: i2c2-gpiogrp {
  607                 fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16           0x400001e2>,
  608                            <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17           0x400001e2>;
  609         };
  610 
  611         pinctrl_i2c4: i2c4grp {
  612                 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL             0x400001e2>,
  613                            <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA             0x400001e2>;
  614         };
  615 
  616         pinctrl_i2c4_gpio: i2c4-gpiogrp {
  617                 fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20           0x400001e2>,
  618                            <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21           0x400001e2>;
  619         };
  620 
  621         pinctrl_i2c6: i2c6grp {
  622                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL            0x400001e2>,
  623                            <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA            0x400001e2>;
  624         };
  625 
  626         pinctrl_i2c6_gpio: i2c6-gpiogrp {
  627                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02          0x400001e2>,
  628                            <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03          0x400001e2>;
  629         };
  630 
  631         pinctrl_lvdsdisplay: lvdsdisplaygrp {
  632                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20           0x10>; /* Power enable */
  633         };
  634 
  635         pinctrl_pcf85063: pcf85063grp {
  636                 fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28          0x80>;
  637         };
  638 
  639         /* LVDS Backlight */
  640         pinctrl_pwm2: pwm2grp {
  641                 fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT            0x14>;
  642         };
  643 
  644         /* FAN */
  645         pinctrl_pwm3: pwm3grp {
  646                 fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT             0x14>;
  647         };
  648 
  649         pinctrl_reg12v0: reg12v0grp {
  650                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06          0x140>; /* VCC12V enable */
  651         };
  652 
  653         /* X61 */
  654         pinctrl_uart1: uart1grp {
  655                 fsl,pins = <MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX          0x140>,
  656                            <MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX          0x140>;
  657         };
  658 
  659         /* X61 */
  660         pinctrl_uart2: uart2grp {
  661                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX        0x140>,
  662                            <MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX        0x140>;
  663         };
  664 
  665         pinctrl_uart3: uart3grp {
  666                 fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX        0x140>,
  667                            <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX        0x140>;
  668         };
  669 
  670         pinctrl_uart4: uart4grp {
  671                 fsl,pins = <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX        0x140>,
  672                            <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX        0x140>;
  673         };
  674 
  675         pinctrl_usdhc2: usdhc2grp {
  676                 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK            0x192>,
  677                            <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD            0x1d2>,
  678                            <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d2>,
  679                            <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d2>,
  680                            <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d2>,
  681                            <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d2>,
  682                            <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
  683         };
  684 
  685         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  686                 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK            0x194>,
  687                            <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD            0x1d4>,
  688                            <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
  689                            <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
  690                            <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
  691                            <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
  692                            <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
  693         };
  694 
  695         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  696                 fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK            0x194>,
  697                            <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD            0x1d4>,
  698                            <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0        0x1d4>,
  699                            <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1        0x1d4>,
  700                            <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2        0x1d4>,
  701                            <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3        0x1d4>,
  702                            <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT     0xc0>;
  703         };
  704 
  705         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
  706                 fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12           0x1c0>;
  707         };
  708 };
Cache object: aea12096b66334f97e6be779c618fc34
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
