Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mp-venice-gw74xx.dts
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Copyright 2021 Gateworks Corporation 4 */ 5 6 /dts-v1/; 7 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/input/linux-event-codes.h> 10 #include <dt-bindings/leds/common.h> 11 12 #include "imx8mp.dtsi" 13 14 / { 15 model = "Gateworks Venice GW74xx i.MX8MP board"; 16 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; 17 18 aliases { 19 ethernet0 = &eqos; 20 ethernet1 = &fec; 21 ethernet2 = &lan1; 22 ethernet3 = &lan2; 23 ethernet4 = &lan3; 24 ethernet5 = &lan4; 25 ethernet6 = &lan5; 26 }; 27 28 chosen { 29 stdout-path = &uart2; 30 }; 31 32 memory@40000000 { 33 device_type = "memory"; 34 reg = <0x0 0x40000000 0 0x80000000>; 35 }; 36 37 gpio-keys { 38 compatible = "gpio-keys"; 39 40 key-0 { 41 label = "user_pb"; 42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>; 43 linux,code = <BTN_0>; 44 }; 45 46 key-1 { 47 label = "user_pb1x"; 48 linux,code = <BTN_1>; 49 interrupt-parent = <&gsc>; 50 interrupts = <0>; 51 }; 52 53 key-2 { 54 label = "key_erased"; 55 linux,code = <BTN_2>; 56 interrupt-parent = <&gsc>; 57 interrupts = <1>; 58 }; 59 60 key-3 { 61 label = "eeprom_wp"; 62 linux,code = <BTN_3>; 63 interrupt-parent = <&gsc>; 64 interrupts = <2>; 65 }; 66 67 key-4 { 68 label = "tamper"; 69 linux,code = <BTN_4>; 70 interrupt-parent = <&gsc>; 71 interrupts = <5>; 72 }; 73 74 key-5 { 75 label = "switch_hold"; 76 linux,code = <BTN_5>; 77 interrupt-parent = <&gsc>; 78 interrupts = <7>; 79 }; 80 }; 81 82 led-controller { 83 compatible = "gpio-leds"; 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_gpio_leds>; 86 87 led-0 { 88 function = LED_FUNCTION_HEARTBEAT; 89 color = <LED_COLOR_ID_GREEN>; 90 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 91 default-state = "on"; 92 linux,default-trigger = "heartbeat"; 93 }; 94 95 led-1 { 96 function = LED_FUNCTION_STATUS; 97 color = <LED_COLOR_ID_RED>; 98 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 99 default-state = "off"; 100 }; 101 }; 102 103 pps { 104 compatible = "pps-gpio"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_pps>; 107 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 108 }; 109 110 reg_usb2_vbus: regulator-usb2 { 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_reg_usb2>; 113 compatible = "regulator-fixed"; 114 regulator-name = "usb_usb2_vbus"; 115 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 regulator-min-microvolt = <5000000>; 118 regulator-max-microvolt = <5000000>; 119 }; 120 121 reg_can2_stby: regulator-can2-stby { 122 compatible = "regulator-fixed"; 123 pinctrl-names = "default"; 124 pinctrl-0 = <&pinctrl_reg_can>; 125 regulator-name = "can2_stby"; 126 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; 127 regulator-min-microvolt = <3300000>; 128 regulator-max-microvolt = <3300000>; 129 }; 130 131 reg_wifi_en: regulator-wifi-en { 132 pinctrl-names = "default"; 133 pinctrl-0 = <&pinctrl_reg_wifi>; 134 compatible = "regulator-fixed"; 135 regulator-name = "wl"; 136 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; 137 startup-delay-us = <100>; 138 enable-active-high; 139 regulator-min-microvolt = <1800000>; 140 regulator-max-microvolt = <1800000>; 141 }; 142 }; 143 144 /* off-board header */ 145 &ecspi2 { 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_spi2>; 148 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 149 status = "okay"; 150 }; 151 152 &eqos { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_eqos>; 155 phy-mode = "rgmii-id"; 156 phy-handle = <ðphy0>; 157 status = "okay"; 158 159 mdio { 160 compatible = "snps,dwmac-mdio"; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 164 ethphy0: ethernet-phy@0 { 165 compatible = "ethernet-phy-ieee802.3-c22"; 166 reg = <0x0>; 167 }; 168 }; 169 }; 170 171 &fec { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_fec>; 174 phy-mode = "rgmii-id"; 175 local-mac-address = [00 00 00 00 00 00]; 176 status = "okay"; 177 178 fixed-link { 179 speed = <1000>; 180 full-duplex; 181 }; 182 }; 183 184 &flexcan2 { 185 pinctrl-names = "default"; 186 pinctrl-0 = <&pinctrl_flexcan2>; 187 xceiver-supply = <®_can2_stby>; 188 status = "okay"; 189 }; 190 191 &gpio1 { 192 gpio-line-names = 193 "", "", "", "", "", "", "", "", 194 "", "", "dio0", "", "dio1", "", "", "", 195 "", "", "", "", "", "", "", "", 196 "", "", "", "", "", "", "", ""; 197 }; 198 199 &gpio2 { 200 gpio-line-names = 201 "", "", "", "", "", "", "", "", 202 "", "", "", "", "", "", "", "", 203 "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", 204 "", "", "", "", "", "", "", ""; 205 }; 206 207 &gpio3 { 208 gpio-line-names = 209 "m2_gdis#", "", "", "", "", "", "", "m2_rst#", 210 "", "", "", "", "", "", "", "", 211 "m2_off#", "", "", "", "", "", "", "", 212 "", "", "", "", "", "", "", ""; 213 }; 214 215 &gpio4 { 216 gpio-line-names = 217 "", "", "", "", "", "", "", "", 218 "", "", "", "", "", "", "", "", 219 "", "", "", "", "m2_wdis#", "", "", "", 220 "", "", "", "", "", "", "", "uart_rs485"; 221 }; 222 223 &gpio5 { 224 gpio-line-names = 225 "uart_half", "uart_term", "", "", "", "", "", "", 226 "", "", "", "", "", "", "", "", 227 "", "", "", "", "", "", "", "", 228 "", "", "", "", "", "", "", ""; 229 }; 230 231 &i2c1 { 232 clock-frequency = <100000>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_i2c1>; 235 status = "okay"; 236 237 gsc: gsc@20 { 238 compatible = "gw,gsc"; 239 reg = <0x20>; 240 pinctrl-0 = <&pinctrl_gsc>; 241 interrupt-parent = <&gpio4>; 242 interrupts = <20 IRQ_TYPE_EDGE_FALLING>; 243 interrupt-controller; 244 #interrupt-cells = <1>; 245 246 adc { 247 compatible = "gw,gsc-adc"; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 251 channel@6 { 252 gw,mode = <0>; 253 reg = <0x06>; 254 label = "temp"; 255 }; 256 257 channel@8 { 258 gw,mode = <1>; 259 reg = <0x08>; 260 label = "vdd_bat"; 261 }; 262 263 channel@82 { 264 gw,mode = <2>; 265 reg = <0x82>; 266 label = "vdd_adc1"; 267 gw,voltage-divider-ohms = <10000 10000>; 268 }; 269 270 channel@84 { 271 gw,mode = <2>; 272 reg = <0x84>; 273 label = "vdd_adc2"; 274 gw,voltage-divider-ohms = <10000 10000>; 275 }; 276 277 channel@86 { 278 gw,mode = <2>; 279 reg = <0x86>; 280 label = "vdd_vin"; 281 gw,voltage-divider-ohms = <22100 1000>; 282 }; 283 284 channel@88 { 285 gw,mode = <2>; 286 reg = <0x88>; 287 label = "vdd_3p3"; 288 gw,voltage-divider-ohms = <10000 10000>; 289 }; 290 291 channel@8c { 292 gw,mode = <2>; 293 reg = <0x8c>; 294 label = "vdd_2p5"; 295 gw,voltage-divider-ohms = <10000 10000>; 296 }; 297 298 channel@90 { 299 gw,mode = <2>; 300 reg = <0x90>; 301 label = "vdd_soc"; 302 }; 303 304 channel@92 { 305 gw,mode = <2>; 306 reg = <0x92>; 307 label = "vdd_arm"; 308 }; 309 310 channel@98 { 311 gw,mode = <2>; 312 reg = <0x98>; 313 label = "vdd_1p8"; 314 }; 315 316 channel@9a { 317 gw,mode = <2>; 318 reg = <0x9a>; 319 label = "vdd_1p2"; 320 }; 321 322 channel@9c { 323 gw,mode = <2>; 324 reg = <0x9c>; 325 label = "vdd_dram"; 326 }; 327 328 channel@a2 { 329 gw,mode = <2>; 330 reg = <0xa2>; 331 label = "vdd_gsc"; 332 gw,voltage-divider-ohms = <10000 10000>; 333 }; 334 }; 335 }; 336 337 gpio: gpio@23 { 338 compatible = "nxp,pca9555"; 339 reg = <0x23>; 340 gpio-controller; 341 #gpio-cells = <2>; 342 interrupt-parent = <&gsc>; 343 interrupts = <4>; 344 }; 345 346 pmic@25 { 347 compatible = "nxp,pca9450c"; 348 reg = <0x25>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_pmic>; 351 interrupt-parent = <&gpio3>; 352 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 353 354 regulators { 355 BUCK1 { 356 regulator-name = "BUCK1"; 357 regulator-min-microvolt = <720000>; 358 regulator-max-microvolt = <1000000>; 359 regulator-boot-on; 360 regulator-always-on; 361 regulator-ramp-delay = <3125>; 362 }; 363 364 BUCK2 { 365 regulator-name = "BUCK2"; 366 regulator-min-microvolt = <720000>; 367 regulator-max-microvolt = <1025000>; 368 regulator-boot-on; 369 regulator-always-on; 370 regulator-ramp-delay = <3125>; 371 nxp,dvs-run-voltage = <950000>; 372 nxp,dvs-standby-voltage = <850000>; 373 }; 374 375 BUCK4 { 376 regulator-name = "BUCK4"; 377 regulator-min-microvolt = <3000000>; 378 regulator-max-microvolt = <3600000>; 379 regulator-boot-on; 380 regulator-always-on; 381 }; 382 383 BUCK5 { 384 regulator-name = "BUCK5"; 385 regulator-min-microvolt = <1650000>; 386 regulator-max-microvolt = <1950000>; 387 regulator-boot-on; 388 regulator-always-on; 389 }; 390 391 BUCK6 { 392 regulator-name = "BUCK6"; 393 regulator-min-microvolt = <1045000>; 394 regulator-max-microvolt = <1155000>; 395 regulator-boot-on; 396 regulator-always-on; 397 }; 398 399 LDO1 { 400 regulator-name = "LDO1"; 401 regulator-min-microvolt = <1650000>; 402 regulator-max-microvolt = <1950000>; 403 regulator-boot-on; 404 regulator-always-on; 405 }; 406 407 LDO3 { 408 regulator-name = "LDO3"; 409 regulator-min-microvolt = <1710000>; 410 regulator-max-microvolt = <1890000>; 411 regulator-boot-on; 412 regulator-always-on; 413 }; 414 415 LDO5 { 416 regulator-name = "LDO5"; 417 regulator-min-microvolt = <1800000>; 418 regulator-max-microvolt = <3300000>; 419 regulator-boot-on; 420 regulator-always-on; 421 }; 422 }; 423 }; 424 425 eeprom@50 { 426 compatible = "atmel,24c02"; 427 reg = <0x50>; 428 pagesize = <16>; 429 }; 430 431 eeprom@51 { 432 compatible = "atmel,24c02"; 433 reg = <0x51>; 434 pagesize = <16>; 435 }; 436 437 eeprom@52 { 438 compatible = "atmel,24c02"; 439 reg = <0x52>; 440 pagesize = <16>; 441 }; 442 443 eeprom@53 { 444 compatible = "atmel,24c02"; 445 reg = <0x53>; 446 pagesize = <16>; 447 }; 448 449 rtc@68 { 450 compatible = "dallas,ds1672"; 451 reg = <0x68>; 452 }; 453 }; 454 455 &i2c2 { 456 clock-frequency = <400000>; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&pinctrl_i2c2>; 459 status = "okay"; 460 461 accelerometer@19 { 462 compatible = "st,lis2de12"; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_accel>; 465 reg = <0x19>; 466 st,drdy-int-pin = <1>; 467 interrupt-parent = <&gpio1>; 468 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 469 interrupt-names = "INT1"; 470 }; 471 472 switch: switch@5f { 473 compatible = "microchip,ksz9897"; 474 reg = <0x5f>; 475 pinctrl-0 = <&pinctrl_ksz>; 476 interrupt-parent = <&gpio4>; 477 interrupts = <29 IRQ_TYPE_EDGE_FALLING>; 478 479 ports { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 483 lan1: port@0 { 484 reg = <0>; 485 label = "lan1"; 486 phy-mode = "internal"; 487 local-mac-address = [00 00 00 00 00 00]; 488 }; 489 490 lan2: port@1 { 491 reg = <1>; 492 label = "lan2"; 493 phy-mode = "internal"; 494 local-mac-address = [00 00 00 00 00 00]; 495 }; 496 497 lan3: port@2 { 498 reg = <2>; 499 label = "lan3"; 500 phy-mode = "internal"; 501 local-mac-address = [00 00 00 00 00 00]; 502 }; 503 504 lan4: port@3 { 505 reg = <3>; 506 label = "lan4"; 507 phy-mode = "internal"; 508 local-mac-address = [00 00 00 00 00 00]; 509 }; 510 511 lan5: port@4 { 512 reg = <4>; 513 label = "lan5"; 514 phy-mode = "internal"; 515 local-mac-address = [00 00 00 00 00 00]; 516 }; 517 518 port@5 { 519 reg = <5>; 520 label = "cpu"; 521 ethernet = <&fec>; 522 phy-mode = "rgmii-id"; 523 524 fixed-link { 525 speed = <1000>; 526 full-duplex; 527 }; 528 }; 529 }; 530 }; 531 }; 532 533 /* off-board header */ 534 &i2c3 { 535 clock-frequency = <400000>; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pinctrl_i2c3>; 538 status = "okay"; 539 }; 540 541 /* off-board header */ 542 &i2c4 { 543 clock-frequency = <400000>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_i2c4>; 546 status = "okay"; 547 }; 548 549 /* GPS / off-board header */ 550 &uart1 { 551 pinctrl-names = "default"; 552 pinctrl-0 = <&pinctrl_uart1>; 553 status = "okay"; 554 }; 555 556 /* RS232 console */ 557 &uart2 { 558 pinctrl-names = "default"; 559 pinctrl-0 = <&pinctrl_uart2>; 560 status = "okay"; 561 }; 562 563 &uart4 { 564 pinctrl-names = "default"; 565 pinctrl-0 = <&pinctrl_uart4>; 566 status = "okay"; 567 }; 568 569 /* USB1 - Type C front panel */ 570 &usb3_phy0 { 571 pinctrl-names = "default"; 572 pinctrl-0 = <&pinctrl_usb1>; 573 status = "okay"; 574 }; 575 576 &usb3_0 { 577 fsl,over-current-active-low; 578 status = "okay"; 579 }; 580 581 &usb_dwc3_0 { 582 dr_mode = "host"; 583 status = "okay"; 584 }; 585 586 /* USB2 - USB3.0 Hub */ 587 &usb3_phy1 { 588 vbus-supply = <®_usb2_vbus>; 589 status = "okay"; 590 }; 591 592 &usb3_1 { 593 fsl,permanently-attached; 594 fsl,disable-port-power-control; 595 status = "okay"; 596 }; 597 598 &usb_dwc3_1 { 599 dr_mode = "host"; 600 status = "okay"; 601 }; 602 603 /* eMMC */ 604 &usdhc3 { 605 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 606 assigned-clock-rates = <400000000>; 607 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 608 pinctrl-0 = <&pinctrl_usdhc3>; 609 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 610 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 611 bus-width = <8>; 612 non-removable; 613 status = "okay"; 614 }; 615 616 &wdog1 { 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_wdog>; 619 fsl,ext-reset-output; 620 status = "okay"; 621 }; 622 623 &iomuxc { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_hog>; 626 627 pinctrl_hog: hoggrp { 628 fsl,pins = < 629 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ 630 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ 631 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ 632 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */ 633 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ 634 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ 635 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ 636 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ 637 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ 638 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ 639 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ 640 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ 641 >; 642 }; 643 644 pinctrl_accel: accelgrp { 645 fsl,pins = < 646 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150 647 >; 648 }; 649 650 pinctrl_eqos: eqosgrp { 651 fsl,pins = < 652 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 653 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 654 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 655 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 656 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 657 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 658 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 659 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 660 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 661 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 662 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 663 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 664 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 665 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 666 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */ 667 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */ 668 >; 669 }; 670 671 pinctrl_fec: fecgrp { 672 fsl,pins = < 673 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 674 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 675 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 676 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 677 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 678 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 679 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 680 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 681 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 682 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 683 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 684 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 685 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140 686 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140 687 >; 688 }; 689 690 pinctrl_flexcan2: flexcan2grp { 691 fsl,pins = < 692 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 693 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 694 >; 695 }; 696 697 pinctrl_gsc: gscgrp { 698 fsl,pins = < 699 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150 700 >; 701 }; 702 703 pinctrl_i2c1: i2c1grp { 704 fsl,pins = < 705 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 706 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 707 >; 708 }; 709 710 pinctrl_i2c2: i2c2grp { 711 fsl,pins = < 712 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 713 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 714 >; 715 }; 716 717 pinctrl_i2c3: i2c3grp { 718 fsl,pins = < 719 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 720 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 721 >; 722 }; 723 724 pinctrl_i2c4: i2c4grp { 725 fsl,pins = < 726 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 727 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 728 >; 729 }; 730 731 pinctrl_ksz: kszgrp { 732 fsl,pins = < 733 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */ 734 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */ 735 >; 736 }; 737 738 pinctrl_gpio_leds: ledgrp { 739 fsl,pins = < 740 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10 741 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 742 >; 743 }; 744 745 pinctrl_pmic: pmicgrp { 746 fsl,pins = < 747 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 748 >; 749 }; 750 751 pinctrl_pps: ppsgrp { 752 fsl,pins = < 753 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 754 >; 755 }; 756 757 pinctrl_reg_can: regcangrp { 758 fsl,pins = < 759 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 760 >; 761 }; 762 763 pinctrl_reg_usb2: regusb2grp { 764 fsl,pins = < 765 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 766 >; 767 }; 768 769 pinctrl_reg_wifi: regwifigrp { 770 fsl,pins = < 771 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110 772 >; 773 }; 774 775 pinctrl_sai2: sai2grp { 776 fsl,pins = < 777 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 778 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 779 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 780 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 781 >; 782 }; 783 784 pinctrl_spi2: spi2grp { 785 fsl,pins = < 786 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 787 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 788 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 789 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 790 >; 791 }; 792 793 pinctrl_uart1: uart1grp { 794 fsl,pins = < 795 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 796 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 797 >; 798 }; 799 800 pinctrl_uart2: uart2grp { 801 fsl,pins = < 802 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 803 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 804 >; 805 }; 806 807 pinctrl_uart3: uart3grp { 808 fsl,pins = < 809 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 810 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 811 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 812 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 813 >; 814 }; 815 816 pinctrl_uart3_gpio: uart3gpiogrp { 817 fsl,pins = < 818 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110 819 >; 820 }; 821 822 pinctrl_uart4: uart4grp { 823 fsl,pins = < 824 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 825 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 826 >; 827 }; 828 829 pinctrl_usb1: usb1grp { 830 fsl,pins = < 831 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 832 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 833 >; 834 }; 835 836 pinctrl_usdhc1: usdhc1grp { 837 fsl,pins = < 838 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 839 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 840 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 841 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 842 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 843 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 844 >; 845 }; 846 847 pinctrl_usdhc3: usdhc3grp { 848 fsl,pins = < 849 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 850 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 851 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 852 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 853 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 854 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 855 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 856 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 857 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 858 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 859 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 860 >; 861 }; 862 863 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 864 fsl,pins = < 865 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 866 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 867 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 868 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 869 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 870 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 871 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 872 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 873 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 874 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 875 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 876 >; 877 }; 878 879 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 880 fsl,pins = < 881 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 882 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 883 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 884 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 885 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 886 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 887 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 888 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 889 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 890 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 891 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 892 >; 893 }; 894 895 pinctrl_wdog: wdoggrp { 896 fsl,pins = < 897 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 898 >; 899 }; 900 };
Cache object: afc582dacd16ee04dc8e59ac4a60dff1
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]