imx8mq-tqma8mq-mba8mx.dts

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    1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
    2 /*
    3  * Copyright 2019-2021 TQ-Systems GmbH
    4  */
    5 
    6 /dts-v1/;
    7 
    8 #include "imx8mq-tqma8mq.dtsi"
    9 #include "mba8mx.dtsi"
   10 
   11 / {
   12         model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx";
   13         compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq";
   14 
   15         aliases {
   16                 eeprom0 = &eeprom3;
   17                 mmc0 = &usdhc1;
   18                 mmc1 = &usdhc2;
   19                 rtc0 = &pcf85063;
   20                 rtc1 = &snvs_rtc;
   21         };
   22 
   23         extcon_usbotg: extcon-usbotg0 {
   24                 compatible = "linux,extcon-usb-gpio";
   25                 pinctrl-names = "default";
   26                 pinctrl-0 = <&pinctrl_usbcon0>;
   27                 id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
   28         };
   29 
   30         pcie0_refclk: pcie0-refclk {
   31                 compatible = "fixed-clock";
   32                 #clock-cells = <0>;
   33                 clock-frequency = <100000000>;
   34         };
   35 
   36         pcie1_refclk: pcie1-refclk {
   37                 compatible = "fixed-clock";
   38                 #clock-cells = <0>;
   39                 clock-frequency = <100000000>;
   40         };
   41 
   42         reg_otg_vbus: regulator-otg-vbus {
   43                 compatible = "regulator-fixed";
   44                 pinctrl-names = "default";
   45                 pinctrl-0 = <&pinctrl_regotgvbus>;
   46                 regulator-name = "MBA8MQ_OTG_VBUS";
   47                 regulator-min-microvolt = <5000000>;
   48                 regulator-max-microvolt = <5000000>;
   49                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
   50                 enable-active-high;
   51         };
   52 
   53         reg_usdhc2_vmmc: regulator-vmmc {
   54                 compatible = "regulator-fixed";
   55                 regulator-name = "VSD_3V3";
   56                 regulator-min-microvolt = <3300000>;
   57                 regulator-max-microvolt = <3300000>;
   58                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
   59                 enable-active-high;
   60         };
   61 };
   62 
   63 &btn2 {
   64         gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
   65 };
   66 
   67 &gpio_leds {
   68         led3 {
   69                 label = "led3";
   70                 gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
   71         };
   72 };
   73 
   74 &i2c1 {
   75         expander2: gpio@25 {
   76                 compatible = "nxp,pca9555";
   77                 reg = <0x25>;
   78                 gpio-controller;
   79                 #gpio-cells = <2>;
   80                 vcc-supply = <&reg_vcc_3v3>;
   81                 pinctrl-names = "default";
   82                 pinctrl-0 = <&pinctrl_expander>;
   83                 interrupt-parent = <&gpio1>;
   84                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
   85                 interrupt-controller;
   86                 #interrupt-cells = <2>;
   87 
   88                 mpcie-rst-hog {
   89                         gpio-hog;
   90                         gpios = <13 0>;
   91                         output-high;
   92                         line-name = "MPCIE_RST#";
   93                 };
   94         };
   95 };
   96 
   97 &irqsteer {
   98         status = "okay";
   99 };
  100 
  101 &led2 {
  102         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  103 };
  104 
  105 &pcie0 {
  106         reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
  107         clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
  108                  <&clk IMX8MQ_CLK_PCIE1_AUX>,
  109                  <&clk IMX8MQ_CLK_PCIE1_PHY>,
  110                  <&pcie0_refclk>;
  111         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
  112         epdev_on-supply = <&reg_vcc_3v3>;
  113         hard-wired = <1>;
  114         status = "okay";
  115 };
  116 
  117 /*
  118  * miniPCIe, also usable for cards with USB. Therefore configure the reset as
  119  * static gpio hog.
  120  */
  121 &pcie1 {
  122         clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
  123                  <&clk IMX8MQ_CLK_PCIE2_AUX>,
  124                  <&clk IMX8MQ_CLK_PCIE2_PHY>,
  125                  <&pcie1_refclk>;
  126         clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
  127         epdev_on-supply = <&reg_vcc_3v3>;
  128         hard-wired = <1>;
  129         status = "okay";
  130 };
  131 
  132 &sai3 {
  133         assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
  134         assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
  135         clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
  136         clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
  137                 <&clk IMX8MQ_CLK_SAI3_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
  138                 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
  139                 <&clk IMX8MQ_AUDIO_PLL2_OUT>;
  140 };
  141 
  142 &tlv320aic3x04 {
  143         clock-names = "mclk";
  144         clocks = <&clk IMX8MQ_CLK_SAI3_ROOT>;
  145 };
  146 
  147 &uart1 {
  148         assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
  149         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
  150 };
  151 
  152 &uart2 {
  153         assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
  154         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
  155 };
  156 
  157 /* console */
  158 &uart3 {
  159         assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
  160         assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
  161 };
  162 
  163 &usb3_phy0 {
  164         vbus-supply = <&reg_otg_vbus>;
  165         status = "okay";
  166 };
  167 
  168 &usb_dwc3_0 {
  169         /* we implement dual role but not full featured OTG */
  170         extcon = <&extcon_usbotg>;
  171         hnp-disable;
  172         srp-disable;
  173         adp-disable;
  174         /* OC not supported due to non matching active polarity */
  175         disable-over-current;
  176         dr_mode = "otg";
  177         status = "okay";
  178 };
  179 
  180 &usb3_phy1 {
  181         status = "okay";
  182 };
  183 
  184 &usb_dwc3_1 {
  185         status = "okay";
  186         dr_mode = "host";
  187 };
  188 
  189 &wdog1 {
  190         pinctrl-names = "default";
  191         pinctrl-0 = <&pinctrl_wdog>;
  192         fsl,ext-reset-output;
  193         status = "okay";
  194 };
  195 
  196 &iomuxc {
  197         pinctrl_ecspi1: ecspi1grp {
  198                 fsl,pins = <MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK        0x0000004e>,
  199                            <MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI        0x0000004e>,
  200                            <MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO        0x0000004e>,
  201                            <MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9           0x0000004e>;
  202         };
  203 
  204         pinctrl_ecspi2: ecspi2grp {
  205                 fsl,pins = <MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK        0x0000004e>,
  206                            <MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI        0x0000004e>,
  207                            <MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO        0x0000004e>,
  208                            <MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13          0x0000004e>;
  209         };
  210 
  211         pinctrl_expander: expandergrp {
  212                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9           0xd6>;
  213         };
  214 
  215         pinctrl_fec1: fec1grp {
  216                 fsl,pins = <MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC             0x3>,
  217                            <MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO           0x23>,
  218                            <MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3       0x1f>,
  219                            <MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2       0x1f>,
  220                            <MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1       0x1f>,
  221                            <MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0       0x1f>,
  222                            <MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3       0x91>,
  223                            <MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2       0x91>,
  224                            <MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1       0x91>,
  225                            <MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0       0x91>,
  226                            <MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC       0x1f>,
  227                            <MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC       0x91>,
  228                            <MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91>,
  229                            <MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f>;
  230         };
  231 
  232         pinctrl_gpiobutton: gpiobuttongrp {
  233                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5           0x41>,
  234                            <MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7           0x41>,
  235                            <MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17           0x41>;
  236         };
  237 
  238         pinctrl_gpioled: gpioledgrp {
  239                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0           0x41>,
  240                            <MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8           0x41>,
  241                            <MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16        0x41>;
  242         };
  243 
  244         pinctrl_i2c2: i2c2grp {
  245                 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL              0x40000067>,
  246                            <MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA              0x40000067>;
  247         };
  248 
  249         pinctrl_i2c2_gpio: i2c2gpiogrp {
  250                 fsl,pins = <MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16            0x40000067>,
  251                            <MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17            0x40000067>;
  252         };
  253 
  254         pinctrl_i2c3: i2c3grp {
  255                 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL              0x40000067>,
  256                            <MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA              0x40000067>;
  257         };
  258 
  259         pinctrl_i2c3_gpio: i2c3gpiogrp {
  260                 fsl,pins = <MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18            0x40000067>,
  261                            <MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19            0x40000067>;
  262         };
  263 
  264         pinctrl_pwm3: pwm3grp {
  265                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT            0x16>;
  266         };
  267 
  268         pinctrl_pwm4: pwm4grp {
  269                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT            0x16>;
  270         };
  271 
  272         pinctrl_regotgvbus: reggotgvbusgrp {
  273                 /* USB1 OTG PWR as GPIO */
  274                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12          0x06>;
  275         };
  276 
  277         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
  278                 fsl,pins = <MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19         0xc1>;
  279         };
  280 
  281         pinctrl_sai3: sai3grp {
  282                 fsl,pins = <MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK            0xd6>,
  283                            <MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK          0xd6>,
  284                            <MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC         0xd6>,
  285                            <MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0         0xd6>,
  286                            <MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC         0xd6>,
  287                            <MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0         0xd6>,
  288                            <MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK          0xd6>;
  289         };
  290 
  291         pinctrl_uart1: uart1grp {
  292                 fsl,pins = <MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX         0x79>,
  293                            <MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX         0x79>;
  294         };
  295 
  296         pinctrl_uart2: uart2grp {
  297                 fsl,pins = <MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX         0x79>,
  298                            <MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX         0x79>;
  299         };
  300 
  301         pinctrl_uart3: uart3grp {
  302                 fsl,pins = <MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX         0x79>,
  303                            <MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX         0x79>;
  304         };
  305 
  306         pinctrl_uart4: uart4grp {
  307                 fsl,pins = <MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX         0x79>,
  308                            <MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX         0x79>;
  309         };
  310 
  311         pinctrl_usbcon0: usb0congrp {
  312                 /* ID: floating / high: device, low: host -> use PU */
  313                 fsl,pins = <MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10          0xe6>;
  314         };
  315 
  316         pinctrl_usdhc2: usdhc2grp {
  317                 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK             0x83>,
  318                            <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD             0xc3>,
  319                            <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0         0xc3>,
  320                            <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1         0xc3>,
  321                            <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2         0xc3>,
  322                            <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3         0xc3>,
  323                            <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0xc1>;
  324         };
  325 
  326         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
  327                 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK             0x85>,
  328                            <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD             0xc5>,
  329                            <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0         0xc5>,
  330                            <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1         0xc5>,
  331                            <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2         0xc5>,
  332                            <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3         0xc5>,
  333                            <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0xc1>;
  334         };
  335 
  336         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
  337                 fsl,pins = <MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK             0x9f>,
  338                            <MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD             0xc7>,
  339                            <MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0         0xc7>,
  340                            <MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1         0xc7>,
  341                            <MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2         0xc7>,
  342                            <MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3         0xc7>,
  343                            <MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT      0xc1>;
  344         };
  345 
  346         pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
  347                 fsl,pins = <MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12            0x41>;
  348         };
  349 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/freescale/imx8mq-tqma8mq-mba8mx.dts
