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     1 // SPDX-License-Identifier: GPL-2.0+
    2 /*
    3  * Copyright 2018-2019 NXP
    4  *      Dong Aisheng <aisheng.dong@nxp.com>
    5  */
    6 
    7 &dma_subsys {
    8         uart4_lpcg: clock-controller@5a4a0000 {
    9                 compatible = "fsl,imx8qxp-lpcg";
   10                 reg = <0x5a4a0000 0x10000>;
   11                 #clock-cells = <1>;
   12                 clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>,
   13                          <&dma_ipg_clk>;
   14                 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
   15                 clock-output-names = "uart4_lpcg_baud_clk",
   16                                      "uart4_lpcg_ipg_clk";
   17                 power-domains = <&pd IMX_SC_R_UART_4>;
   18         };
   19 };
   20 
   21 &lpuart0 {
   22         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
   23 };
   24 
   25 &lpuart1 {
   26         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
   27 };
   28 
   29 &lpuart2 {
   30         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
   31 };
   32 
   33 &lpuart3 {
   34         compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
   35 };
   36 
   37 &i2c0 {
   38         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
   39 };
   40 
   41 &i2c1 {
   42         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
   43 };
   44 
   45 &i2c2 {
   46         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
   47 };
   48 
   49 &i2c3 {
   50         compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
   51 };
Cache object: 64484f8d40b10aa3193ca5e363f0b072 
 
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