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sys/contrib/device-tree/src/arm64/hisilicon/hi3660.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, HiSilicon Ltd. 6 */ 7 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/hi3660-clock.h> 10 #include <dt-bindings/thermal/thermal.h> 11 12 / { 13 compatible = "hisilicon,hi3660"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 psci { 19 compatible = "arm,psci-0.2"; 20 method = "smc"; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 core3 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 cluster1 { 43 core0 { 44 cpu = <&cpu4>; 45 }; 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 core2 { 50 cpu = <&cpu6>; 51 }; 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 next-level-cache = <&A53_L2>; 64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 65 capacity-dmips-mhz = <592>; 66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 67 operating-points-v2 = <&cluster0_opp>; 68 #cooling-cells = <2>; 69 dynamic-power-coefficient = <110>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "psci"; 77 next-level-cache = <&A53_L2>; 78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 79 capacity-dmips-mhz = <592>; 80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 81 operating-points-v2 = <&cluster0_opp>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu2: cpu@2 { 86 compatible = "arm,cortex-a53"; 87 device_type = "cpu"; 88 reg = <0x0 0x2>; 89 enable-method = "psci"; 90 next-level-cache = <&A53_L2>; 91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92 capacity-dmips-mhz = <592>; 93 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 94 operating-points-v2 = <&cluster0_opp>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu3: cpu@3 { 99 compatible = "arm,cortex-a53"; 100 device_type = "cpu"; 101 reg = <0x0 0x3>; 102 enable-method = "psci"; 103 next-level-cache = <&A53_L2>; 104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 105 capacity-dmips-mhz = <592>; 106 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 107 operating-points-v2 = <&cluster0_opp>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu4: cpu@100 { 112 compatible = "arm,cortex-a73"; 113 device_type = "cpu"; 114 reg = <0x0 0x100>; 115 enable-method = "psci"; 116 next-level-cache = <&A73_L2>; 117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 118 capacity-dmips-mhz = <1024>; 119 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 120 operating-points-v2 = <&cluster1_opp>; 121 #cooling-cells = <2>; 122 dynamic-power-coefficient = <550>; 123 }; 124 125 cpu5: cpu@101 { 126 compatible = "arm,cortex-a73"; 127 device_type = "cpu"; 128 reg = <0x0 0x101>; 129 enable-method = "psci"; 130 next-level-cache = <&A73_L2>; 131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 132 capacity-dmips-mhz = <1024>; 133 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 134 operating-points-v2 = <&cluster1_opp>; 135 #cooling-cells = <2>; 136 }; 137 138 cpu6: cpu@102 { 139 compatible = "arm,cortex-a73"; 140 device_type = "cpu"; 141 reg = <0x0 0x102>; 142 enable-method = "psci"; 143 next-level-cache = <&A73_L2>; 144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 145 capacity-dmips-mhz = <1024>; 146 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 147 operating-points-v2 = <&cluster1_opp>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu7: cpu@103 { 152 compatible = "arm,cortex-a73"; 153 device_type = "cpu"; 154 reg = <0x0 0x103>; 155 enable-method = "psci"; 156 next-level-cache = <&A73_L2>; 157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 158 capacity-dmips-mhz = <1024>; 159 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 160 operating-points-v2 = <&cluster1_opp>; 161 #cooling-cells = <2>; 162 }; 163 164 idle-states { 165 entry-method = "psci"; 166 167 CPU_SLEEP_0: cpu-sleep-0 { 168 compatible = "arm,idle-state"; 169 local-timer-stop; 170 arm,psci-suspend-param = <0x0010000>; 171 entry-latency-us = <400>; 172 exit-latency-us = <650>; 173 min-residency-us = <1500>; 174 }; 175 CLUSTER_SLEEP_0: cluster-sleep-0 { 176 compatible = "arm,idle-state"; 177 local-timer-stop; 178 arm,psci-suspend-param = <0x1010000>; 179 entry-latency-us = <500>; 180 exit-latency-us = <1600>; 181 min-residency-us = <3500>; 182 }; 183 184 185 CPU_SLEEP_1: cpu-sleep-1 { 186 compatible = "arm,idle-state"; 187 local-timer-stop; 188 arm,psci-suspend-param = <0x0010000>; 189 entry-latency-us = <400>; 190 exit-latency-us = <550>; 191 min-residency-us = <1500>; 192 }; 193 194 CLUSTER_SLEEP_1: cluster-sleep-1 { 195 compatible = "arm,idle-state"; 196 local-timer-stop; 197 arm,psci-suspend-param = <0x1010000>; 198 entry-latency-us = <800>; 199 exit-latency-us = <2900>; 200 min-residency-us = <3500>; 201 }; 202 }; 203 204 A53_L2: l2-cache0 { 205 compatible = "cache"; 206 }; 207 208 A73_L2: l2-cache1 { 209 compatible = "cache"; 210 }; 211 }; 212 213 cluster0_opp: opp-table-0 { 214 compatible = "operating-points-v2"; 215 opp-shared; 216 217 opp00 { 218 opp-hz = /bits/ 64 <533000000>; 219 opp-microvolt = <700000>; 220 clock-latency-ns = <300000>; 221 }; 222 223 opp01 { 224 opp-hz = /bits/ 64 <999000000>; 225 opp-microvolt = <800000>; 226 clock-latency-ns = <300000>; 227 }; 228 229 opp02 { 230 opp-hz = /bits/ 64 <1402000000>; 231 opp-microvolt = <900000>; 232 clock-latency-ns = <300000>; 233 }; 234 235 opp03 { 236 opp-hz = /bits/ 64 <1709000000>; 237 opp-microvolt = <1000000>; 238 clock-latency-ns = <300000>; 239 }; 240 241 opp04 { 242 opp-hz = /bits/ 64 <1844000000>; 243 opp-microvolt = <1100000>; 244 clock-latency-ns = <300000>; 245 }; 246 }; 247 248 cluster1_opp: opp-table-1 { 249 compatible = "operating-points-v2"; 250 opp-shared; 251 252 opp10 { 253 opp-hz = /bits/ 64 <903000000>; 254 opp-microvolt = <700000>; 255 clock-latency-ns = <300000>; 256 }; 257 258 opp11 { 259 opp-hz = /bits/ 64 <1421000000>; 260 opp-microvolt = <800000>; 261 clock-latency-ns = <300000>; 262 }; 263 264 opp12 { 265 opp-hz = /bits/ 64 <1805000000>; 266 opp-microvolt = <900000>; 267 clock-latency-ns = <300000>; 268 }; 269 270 opp13 { 271 opp-hz = /bits/ 64 <2112000000>; 272 opp-microvolt = <1000000>; 273 clock-latency-ns = <300000>; 274 }; 275 276 opp14 { 277 opp-hz = /bits/ 64 <2362000000>; 278 opp-microvolt = <1100000>; 279 clock-latency-ns = <300000>; 280 }; 281 }; 282 283 gic: interrupt-controller@e82b0000 { 284 compatible = "arm,gic-400"; 285 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 286 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 287 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 288 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 289 #address-cells = <0>; 290 #interrupt-cells = <3>; 291 interrupt-controller; 292 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 293 IRQ_TYPE_LEVEL_HIGH)>; 294 }; 295 296 a53-pmu { 297 compatible = "arm,cortex-a53-pmu"; 298 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-affinity = <&cpu0>, 303 <&cpu1>, 304 <&cpu2>, 305 <&cpu3>; 306 }; 307 308 a73-pmu { 309 compatible = "arm,cortex-a73-pmu"; 310 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-affinity = <&cpu4>, 315 <&cpu5>, 316 <&cpu6>, 317 <&cpu7>; 318 }; 319 320 timer { 321 compatible = "arm,armv8-timer"; 322 interrupt-parent = <&gic>; 323 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 324 IRQ_TYPE_LEVEL_LOW)>, 325 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 326 IRQ_TYPE_LEVEL_LOW)>, 327 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 328 IRQ_TYPE_LEVEL_LOW)>, 329 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 330 IRQ_TYPE_LEVEL_LOW)>; 331 }; 332 333 soc { 334 compatible = "simple-bus"; 335 #address-cells = <2>; 336 #size-cells = <2>; 337 ranges; 338 339 crg_ctrl: crg_ctrl@fff35000 { 340 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 341 reg = <0x0 0xfff35000 0x0 0x1000>; 342 #clock-cells = <1>; 343 }; 344 345 crg_rst: crg_rst_controller { 346 compatible = "hisilicon,hi3660-reset"; 347 #reset-cells = <2>; 348 hisi,rst-syscon = <&crg_ctrl>; 349 }; 350 351 352 pctrl: pctrl@e8a09000 { 353 compatible = "hisilicon,hi3660-pctrl", "syscon"; 354 reg = <0x0 0xe8a09000 0x0 0x2000>; 355 #clock-cells = <1>; 356 }; 357 358 pmuctrl: crg_ctrl@fff34000 { 359 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 360 reg = <0x0 0xfff34000 0x0 0x1000>; 361 #clock-cells = <1>; 362 }; 363 364 sctrl: sctrl@fff0a000 { 365 compatible = "hisilicon,hi3660-sctrl", "syscon"; 366 reg = <0x0 0xfff0a000 0x0 0x1000>; 367 #clock-cells = <1>; 368 }; 369 370 iomcu: iomcu@ffd7e000 { 371 compatible = "hisilicon,hi3660-iomcu", "syscon"; 372 reg = <0x0 0xffd7e000 0x0 0x1000>; 373 #clock-cells = <1>; 374 375 }; 376 377 iomcu_rst: reset { 378 compatible = "hisilicon,hi3660-reset"; 379 hisi,rst-syscon = <&iomcu>; 380 #reset-cells = <2>; 381 }; 382 383 mailbox: mailbox@e896b000 { 384 compatible = "hisilicon,hi3660-mbox"; 385 reg = <0x0 0xe896b000 0x0 0x1000>; 386 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 388 #mbox-cells = <3>; 389 }; 390 391 stub_clock: stub_clock@e896b500 { 392 compatible = "hisilicon,hi3660-stub-clk"; 393 reg = <0x0 0xe896b500 0x0 0x0100>; 394 #clock-cells = <1>; 395 mboxes = <&mailbox 13 3 0>; 396 }; 397 398 dual_timer0: timer@fff14000 { 399 compatible = "arm,sp804", "arm,primecell"; 400 reg = <0x0 0xfff14000 0x0 0x1000>; 401 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&crg_ctrl HI3660_OSC32K>, 404 <&crg_ctrl HI3660_OSC32K>, 405 <&crg_ctrl HI3660_OSC32K>; 406 clock-names = "timer1", "timer2", "apb_pclk"; 407 }; 408 409 i2c0: i2c@ffd71000 { 410 compatible = "snps,designware-i2c"; 411 reg = <0x0 0xffd71000 0x0 0x1000>; 412 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clock-frequency = <400000>; 416 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 417 resets = <&iomcu_rst 0x20 3>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 420 status = "disabled"; 421 }; 422 423 i2c1: i2c@ffd72000 { 424 compatible = "snps,designware-i2c"; 425 reg = <0x0 0xffd72000 0x0 0x1000>; 426 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clock-frequency = <400000>; 430 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 431 resets = <&iomcu_rst 0x20 4>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 434 status = "disabled"; 435 }; 436 437 i2c3: i2c@fdf0c000 { 438 compatible = "snps,designware-i2c"; 439 reg = <0x0 0xfdf0c000 0x0 0x1000>; 440 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 clock-frequency = <400000>; 444 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 445 resets = <&crg_rst 0x78 7>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 448 status = "disabled"; 449 }; 450 451 i2c7: i2c@fdf0b000 { 452 compatible = "snps,designware-i2c"; 453 reg = <0x0 0xfdf0b000 0x0 0x1000>; 454 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clock-frequency = <400000>; 458 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 459 resets = <&crg_rst 0x60 14>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 462 status = "disabled"; 463 }; 464 465 uart0: serial@fdf02000 { 466 compatible = "arm,pl011", "arm,primecell"; 467 reg = <0x0 0xfdf02000 0x0 0x1000>; 468 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 470 <&crg_ctrl HI3660_PCLK>; 471 clock-names = "uartclk", "apb_pclk"; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 474 status = "disabled"; 475 }; 476 477 uart1: serial@fdf00000 { 478 compatible = "arm,pl011", "arm,primecell"; 479 reg = <0x0 0xfdf00000 0x0 0x1000>; 480 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 481 dma-names = "rx", "tx"; 482 dmas = <&dma0 2 &dma0 3>; 483 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 484 <&crg_ctrl HI3660_CLK_GATE_UART1>; 485 clock-names = "uartclk", "apb_pclk"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 488 status = "disabled"; 489 }; 490 491 uart2: serial@fdf03000 { 492 compatible = "arm,pl011", "arm,primecell"; 493 reg = <0x0 0xfdf03000 0x0 0x1000>; 494 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 495 dma-names = "rx", "tx"; 496 dmas = <&dma0 4 &dma0 5>; 497 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 498 <&crg_ctrl HI3660_PCLK>; 499 clock-names = "uartclk", "apb_pclk"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 502 status = "disabled"; 503 }; 504 505 uart3: serial@ffd74000 { 506 compatible = "arm,pl011", "arm,primecell"; 507 reg = <0x0 0xffd74000 0x0 0x1000>; 508 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 510 <&crg_ctrl HI3660_PCLK>; 511 clock-names = "uartclk", "apb_pclk"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 514 status = "disabled"; 515 }; 516 517 uart4: serial@fdf01000 { 518 compatible = "arm,pl011", "arm,primecell"; 519 reg = <0x0 0xfdf01000 0x0 0x1000>; 520 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 521 dma-names = "rx", "tx"; 522 dmas = <&dma0 6 &dma0 7>; 523 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 524 <&crg_ctrl HI3660_CLK_GATE_UART4>; 525 clock-names = "uartclk", "apb_pclk"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 528 status = "disabled"; 529 }; 530 531 uart5: serial@fdf05000 { 532 compatible = "arm,pl011", "arm,primecell"; 533 reg = <0x0 0xfdf05000 0x0 0x1000>; 534 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 535 dma-names = "rx", "tx"; 536 dmas = <&dma0 8 &dma0 9>; 537 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 538 <&crg_ctrl HI3660_CLK_GATE_UART5>; 539 clock-names = "uartclk", "apb_pclk"; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 542 status = "disabled"; 543 }; 544 545 uart6: serial@fff32000 { 546 compatible = "arm,pl011", "arm,primecell"; 547 reg = <0x0 0xfff32000 0x0 0x1000>; 548 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&crg_ctrl HI3660_CLK_UART6>, 550 <&crg_ctrl HI3660_PCLK>; 551 clock-names = "uartclk", "apb_pclk"; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 554 status = "disabled"; 555 }; 556 557 dma0: dma@fdf30000 { 558 compatible = "hisilicon,k3-dma-1.0"; 559 reg = <0x0 0xfdf30000 0x0 0x1000>; 560 #dma-cells = <1>; 561 dma-channels = <16>; 562 dma-requests = <32>; 563 dma-channel-mask = <0xfffe>; 564 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 566 dma-no-cci; 567 dma-type = "hi3660_dma"; 568 }; 569 570 asp_dmac: dma-controller@e804b000 { 571 compatible = "hisilicon,hisi-pcm-asp-dma-1.0"; 572 reg = <0x0 0xe804b000 0x0 0x1000>; 573 #dma-cells = <1>; 574 dma-channels = <16>; 575 dma-requests = <32>; 576 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 577 interrupt-names = "asp_dma_irq"; 578 }; 579 580 rtc0: rtc@fff04000 { 581 compatible = "arm,pl031", "arm,primecell"; 582 reg = <0x0 0Xfff04000 0x0 0x1000>; 583 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 584 clocks = <&crg_ctrl HI3660_PCLK>; 585 clock-names = "apb_pclk"; 586 }; 587 588 gpio0: gpio@e8a0b000 { 589 compatible = "arm,pl061", "arm,primecell"; 590 reg = <0 0xe8a0b000 0 0x1000>; 591 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 592 gpio-controller; 593 #gpio-cells = <2>; 594 gpio-ranges = <&pmx0 1 0 7>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 598 clock-names = "apb_pclk"; 599 }; 600 601 gpio1: gpio@e8a0c000 { 602 compatible = "arm,pl061", "arm,primecell"; 603 reg = <0 0xe8a0c000 0 0x1000>; 604 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 605 gpio-controller; 606 #gpio-cells = <2>; 607 gpio-ranges = <&pmx0 1 7 7>; 608 interrupt-controller; 609 #interrupt-cells = <2>; 610 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 611 clock-names = "apb_pclk"; 612 }; 613 614 gpio2: gpio@e8a0d000 { 615 compatible = "arm,pl061", "arm,primecell"; 616 reg = <0 0xe8a0d000 0 0x1000>; 617 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 618 gpio-controller; 619 #gpio-cells = <2>; 620 gpio-ranges = <&pmx0 0 14 8>; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 624 clock-names = "apb_pclk"; 625 }; 626 627 gpio3: gpio@e8a0e000 { 628 compatible = "arm,pl061", "arm,primecell"; 629 reg = <0 0xe8a0e000 0 0x1000>; 630 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 631 gpio-controller; 632 #gpio-cells = <2>; 633 gpio-ranges = <&pmx0 0 22 8>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 637 clock-names = "apb_pclk"; 638 }; 639 640 gpio4: gpio@e8a0f000 { 641 compatible = "arm,pl061", "arm,primecell"; 642 reg = <0 0xe8a0f000 0 0x1000>; 643 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 644 gpio-controller; 645 #gpio-cells = <2>; 646 gpio-ranges = <&pmx0 0 30 8>; 647 interrupt-controller; 648 #interrupt-cells = <2>; 649 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 650 clock-names = "apb_pclk"; 651 }; 652 653 gpio5: gpio@e8a10000 { 654 compatible = "arm,pl061", "arm,primecell"; 655 reg = <0 0xe8a10000 0 0x1000>; 656 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 657 gpio-controller; 658 #gpio-cells = <2>; 659 gpio-ranges = <&pmx0 0 38 8>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 663 clock-names = "apb_pclk"; 664 }; 665 666 gpio6: gpio@e8a11000 { 667 compatible = "arm,pl061", "arm,primecell"; 668 reg = <0 0xe8a11000 0 0x1000>; 669 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 670 gpio-controller; 671 #gpio-cells = <2>; 672 gpio-ranges = <&pmx0 0 46 8>; 673 interrupt-controller; 674 #interrupt-cells = <2>; 675 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 676 clock-names = "apb_pclk"; 677 }; 678 679 gpio7: gpio@e8a12000 { 680 compatible = "arm,pl061", "arm,primecell"; 681 reg = <0 0xe8a12000 0 0x1000>; 682 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 683 gpio-controller; 684 #gpio-cells = <2>; 685 gpio-ranges = <&pmx0 0 54 8>; 686 interrupt-controller; 687 #interrupt-cells = <2>; 688 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 689 clock-names = "apb_pclk"; 690 }; 691 692 gpio8: gpio@e8a13000 { 693 compatible = "arm,pl061", "arm,primecell"; 694 reg = <0 0xe8a13000 0 0x1000>; 695 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 696 gpio-controller; 697 #gpio-cells = <2>; 698 gpio-ranges = <&pmx0 0 62 8>; 699 interrupt-controller; 700 #interrupt-cells = <2>; 701 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 702 clock-names = "apb_pclk"; 703 }; 704 705 gpio9: gpio@e8a14000 { 706 compatible = "arm,pl061", "arm,primecell"; 707 reg = <0 0xe8a14000 0 0x1000>; 708 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 709 gpio-controller; 710 #gpio-cells = <2>; 711 gpio-ranges = <&pmx0 0 70 8>; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 715 clock-names = "apb_pclk"; 716 }; 717 718 gpio10: gpio@e8a15000 { 719 compatible = "arm,pl061", "arm,primecell"; 720 reg = <0 0xe8a15000 0 0x1000>; 721 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 722 gpio-controller; 723 #gpio-cells = <2>; 724 gpio-ranges = <&pmx0 0 78 8>; 725 interrupt-controller; 726 #interrupt-cells = <2>; 727 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 728 clock-names = "apb_pclk"; 729 }; 730 731 gpio11: gpio@e8a16000 { 732 compatible = "arm,pl061", "arm,primecell"; 733 reg = <0 0xe8a16000 0 0x1000>; 734 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 735 gpio-controller; 736 #gpio-cells = <2>; 737 gpio-ranges = <&pmx0 0 86 8>; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 741 clock-names = "apb_pclk"; 742 }; 743 744 gpio12: gpio@e8a17000 { 745 compatible = "arm,pl061", "arm,primecell"; 746 reg = <0 0xe8a17000 0 0x1000>; 747 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 748 gpio-controller; 749 #gpio-cells = <2>; 750 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 751 interrupt-controller; 752 #interrupt-cells = <2>; 753 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 754 clock-names = "apb_pclk"; 755 }; 756 757 gpio13: gpio@e8a18000 { 758 compatible = "arm,pl061", "arm,primecell"; 759 reg = <0 0xe8a18000 0 0x1000>; 760 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 761 gpio-controller; 762 #gpio-cells = <2>; 763 gpio-ranges = <&pmx0 0 102 8>; 764 interrupt-controller; 765 #interrupt-cells = <2>; 766 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 767 clock-names = "apb_pclk"; 768 }; 769 770 gpio14: gpio@e8a19000 { 771 compatible = "arm,pl061", "arm,primecell"; 772 reg = <0 0xe8a19000 0 0x1000>; 773 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 774 gpio-controller; 775 #gpio-cells = <2>; 776 gpio-ranges = <&pmx0 0 110 8>; 777 interrupt-controller; 778 #interrupt-cells = <2>; 779 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 780 clock-names = "apb_pclk"; 781 }; 782 783 gpio15: gpio@e8a1a000 { 784 compatible = "arm,pl061", "arm,primecell"; 785 reg = <0 0xe8a1a000 0 0x1000>; 786 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 787 gpio-controller; 788 #gpio-cells = <2>; 789 gpio-ranges = <&pmx0 0 118 6>; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 793 clock-names = "apb_pclk"; 794 }; 795 796 gpio16: gpio@e8a1b000 { 797 compatible = "arm,pl061", "arm,primecell"; 798 reg = <0 0xe8a1b000 0 0x1000>; 799 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 800 gpio-controller; 801 #gpio-cells = <2>; 802 interrupt-controller; 803 #interrupt-cells = <2>; 804 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 805 clock-names = "apb_pclk"; 806 }; 807 808 gpio17: gpio@e8a1c000 { 809 compatible = "arm,pl061", "arm,primecell"; 810 reg = <0 0xe8a1c000 0 0x1000>; 811 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 812 gpio-controller; 813 #gpio-cells = <2>; 814 interrupt-controller; 815 #interrupt-cells = <2>; 816 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 817 clock-names = "apb_pclk"; 818 }; 819 820 gpio18: gpio@ff3b4000 { 821 compatible = "arm,pl061", "arm,primecell"; 822 reg = <0 0xff3b4000 0 0x1000>; 823 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 824 gpio-controller; 825 #gpio-cells = <2>; 826 gpio-ranges = <&pmx2 0 0 8>; 827 interrupt-controller; 828 #interrupt-cells = <2>; 829 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 830 clock-names = "apb_pclk"; 831 }; 832 833 gpio19: gpio@ff3b5000 { 834 compatible = "arm,pl061", "arm,primecell"; 835 reg = <0 0xff3b5000 0 0x1000>; 836 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 837 gpio-controller; 838 #gpio-cells = <2>; 839 gpio-ranges = <&pmx2 0 8 4>; 840 interrupt-controller; 841 #interrupt-cells = <2>; 842 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 843 clock-names = "apb_pclk"; 844 }; 845 846 gpio20: gpio@e8a1f000 { 847 compatible = "arm,pl061", "arm,primecell"; 848 reg = <0 0xe8a1f000 0 0x1000>; 849 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 850 gpio-controller; 851 #gpio-cells = <2>; 852 gpio-ranges = <&pmx1 0 0 6>; 853 interrupt-controller; 854 #interrupt-cells = <2>; 855 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 856 clock-names = "apb_pclk"; 857 }; 858 859 gpio21: gpio@e8a20000 { 860 compatible = "arm,pl061", "arm,primecell"; 861 reg = <0 0xe8a20000 0 0x1000>; 862 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 863 gpio-controller; 864 #gpio-cells = <2>; 865 interrupt-controller; 866 #interrupt-cells = <2>; 867 gpio-ranges = <&pmx3 0 0 6>; 868 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 869 clock-names = "apb_pclk"; 870 }; 871 872 gpio22: gpio@fff0b000 { 873 compatible = "arm,pl061", "arm,primecell"; 874 reg = <0 0xfff0b000 0 0x1000>; 875 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 876 gpio-controller; 877 #gpio-cells = <2>; 878 /* GPIO176 */ 879 gpio-ranges = <&pmx4 2 0 6>; 880 interrupt-controller; 881 #interrupt-cells = <2>; 882 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 883 clock-names = "apb_pclk"; 884 }; 885 886 gpio23: gpio@fff0c000 { 887 compatible = "arm,pl061", "arm,primecell"; 888 reg = <0 0xfff0c000 0 0x1000>; 889 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 890 gpio-controller; 891 #gpio-cells = <2>; 892 /* GPIO184 */ 893 gpio-ranges = <&pmx4 0 6 7>; 894 interrupt-controller; 895 #interrupt-cells = <2>; 896 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 897 clock-names = "apb_pclk"; 898 }; 899 900 gpio24: gpio@fff0d000 { 901 compatible = "arm,pl061", "arm,primecell"; 902 reg = <0 0xfff0d000 0 0x1000>; 903 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 904 gpio-controller; 905 #gpio-cells = <2>; 906 /* GPIO192 */ 907 gpio-ranges = <&pmx4 0 13 8>; 908 interrupt-controller; 909 #interrupt-cells = <2>; 910 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 911 clock-names = "apb_pclk"; 912 }; 913 914 gpio25: gpio@fff0e000 { 915 compatible = "arm,pl061", "arm,primecell"; 916 reg = <0 0xfff0e000 0 0x1000>; 917 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 918 gpio-controller; 919 #gpio-cells = <2>; 920 /* GPIO200 */ 921 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 922 interrupt-controller; 923 #interrupt-cells = <2>; 924 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 925 clock-names = "apb_pclk"; 926 }; 927 928 gpio26: gpio@fff0f000 { 929 compatible = "arm,pl061", "arm,primecell"; 930 reg = <0 0xfff0f000 0 0x1000>; 931 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 932 gpio-controller; 933 #gpio-cells = <2>; 934 /* GPIO208 */ 935 gpio-ranges = <&pmx4 0 28 8>; 936 interrupt-controller; 937 #interrupt-cells = <2>; 938 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 939 clock-names = "apb_pclk"; 940 }; 941 942 gpio27: gpio@fff10000 { 943 compatible = "arm,pl061", "arm,primecell"; 944 reg = <0 0xfff10000 0 0x1000>; 945 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 946 gpio-controller; 947 #gpio-cells = <2>; 948 /* GPIO216 */ 949 gpio-ranges = <&pmx4 0 36 6>; 950 interrupt-controller; 951 #interrupt-cells = <2>; 952 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 953 clock-names = "apb_pclk"; 954 }; 955 956 gpio28: gpio@fff1d000 { 957 compatible = "arm,pl061", "arm,primecell"; 958 reg = <0 0xfff1d000 0 0x1000>; 959 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 960 gpio-controller; 961 #gpio-cells = <2>; 962 interrupt-controller; 963 #interrupt-cells = <2>; 964 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 965 clock-names = "apb_pclk"; 966 }; 967 968 spi2: spi@ffd68000 { 969 compatible = "arm,pl022", "arm,primecell"; 970 reg = <0x0 0xffd68000 0x0 0x1000>; 971 #address-cells = <1>; 972 #size-cells = <0>; 973 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>; 975 clock-names = "sspclk", "apb_pclk"; 976 pinctrl-names = "default"; 977 pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>; 978 num-cs = <1>; 979 cs-gpios = <&gpio27 2 0>; 980 status = "disabled"; 981 }; 982 983 spi3: spi@ff3b3000 { 984 compatible = "arm,pl022", "arm,primecell"; 985 reg = <0x0 0xff3b3000 0x0 0x1000>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>; 990 clock-names = "sspclk", "apb_pclk"; 991 pinctrl-names = "default"; 992 pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>; 993 num-cs = <1>; 994 cs-gpios = <&gpio18 5 0>; 995 status = "disabled"; 996 }; 997 998 pcie@f4000000 { 999 compatible = "hisilicon,kirin960-pcie"; 1000 reg = <0x0 0xf4000000 0x0 0x1000>, 1001 <0x0 0xff3fe000 0x0 0x1000>, 1002 <0x0 0xf3f20000 0x0 0x40000>, 1003 <0x0 0xf5000000 0x0 0x2000>; 1004 reg-names = "dbi", "apb", "phy", "config"; 1005 bus-range = <0x0 0xff>; 1006 #address-cells = <3>; 1007 #size-cells = <2>; 1008 device_type = "pci"; 1009 ranges = <0x02000000 0x0 0x00000000 1010 0x0 0xf6000000 1011 0x0 0x02000000>; 1012 num-lanes = <1>; 1013 #interrupt-cells = <1>; 1014 interrupts = <0 283 4>; 1015 interrupt-names = "msi"; 1016 interrupt-map-mask = <0xf800 0 0 7>; 1017 interrupt-map = <0x0 0 0 1 1018 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1019 <0x0 0 0 2 1020 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1021 <0x0 0 0 3 1022 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1023 <0x0 0 0 4 1024 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 1025 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 1026 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 1027 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 1028 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 1029 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 1030 clock-names = "pcie_phy_ref", "pcie_aux", 1031 "pcie_apb_phy", "pcie_apb_sys", 1032 "pcie_aclk"; 1033 reset-gpios = <&gpio11 1 0 >; 1034 }; 1035 1036 /* UFS */ 1037 ufs: ufs@ff3b0000 { 1038 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 1039 /* 0: HCI standard */ 1040 /* 1: UFS SYS CTRL */ 1041 reg = <0x0 0xff3b0000 0x0 0x1000>, 1042 <0x0 0xff3b1000 0x0 0x1000>; 1043 interrupt-parent = <&gic>; 1044 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 1046 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 1047 clock-names = "ref_clk", "phy_clk"; 1048 freq-table-hz = <0 0>, 1049 <0 0>; 1050 /* offset: 0x84; bit: 12 */ 1051 resets = <&crg_rst 0x84 12>; 1052 reset-names = "rst"; 1053 }; 1054 1055 /* SD */ 1056 dwmmc1: dwmmc1@ff37f000 { 1057 compatible = "hisilicon,hi3660-dw-mshc"; 1058 reg = <0x0 0xff37f000 0x0 0x1000>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1063 <&crg_ctrl HI3660_HCLK_GATE_SD>; 1064 clock-names = "ciu", "biu"; 1065 clock-frequency = <3200000>; 1066 resets = <&crg_rst 0x94 18>; 1067 reset-names = "reset"; 1068 hisilicon,peripheral-syscon = <&sctrl>; 1069 card-detect-delay = <200>; 1070 status = "disabled"; 1071 }; 1072 1073 /* SDIO */ 1074 dwmmc2: dwmmc2@ff3ff000 { 1075 compatible = "hisilicon,hi3660-dw-mshc"; 1076 reg = <0x0 0xff3ff000 0x0 0x1000>; 1077 #address-cells = <0x1>; 1078 #size-cells = <0x0>; 1079 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1080 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1081 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1082 clock-names = "ciu", "biu"; 1083 resets = <&crg_rst 0x94 20>; 1084 reset-names = "reset"; 1085 card-detect-delay = <200>; 1086 status = "disabled"; 1087 }; 1088 1089 watchdog0: watchdog@e8a06000 { 1090 compatible = "arm,sp805", "arm,primecell"; 1091 reg = <0x0 0xe8a06000 0x0 0x1000>; 1092 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&crg_ctrl HI3660_OSC32K>, 1094 <&crg_ctrl HI3660_OSC32K>; 1095 clock-names = "wdog_clk", "apb_pclk"; 1096 }; 1097 1098 watchdog1: watchdog@e8a07000 { 1099 compatible = "arm,sp805", "arm,primecell"; 1100 reg = <0x0 0xe8a07000 0x0 0x1000>; 1101 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&crg_ctrl HI3660_OSC32K>, 1103 <&crg_ctrl HI3660_OSC32K>; 1104 clock-names = "wdog_clk", "apb_pclk"; 1105 }; 1106 1107 tsensor: tsensor@fff30000 { 1108 compatible = "hisilicon,hi3660-tsensor"; 1109 reg = <0x0 0xfff30000 0x0 0x1000>; 1110 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1111 #thermal-sensor-cells = <1>; 1112 }; 1113 1114 thermal-zones { 1115 1116 cls0: cls0-thermal { 1117 polling-delay = <1000>; 1118 polling-delay-passive = <100>; 1119 sustainable-power = <4500>; 1120 1121 /* sensor ID */ 1122 thermal-sensors = <&tsensor 1>; 1123 1124 trips { 1125 threshold: trip-point0 { 1126 temperature = <65000>; 1127 hysteresis = <1000>; 1128 type = "passive"; 1129 }; 1130 1131 target: trip-point1 { 1132 temperature = <75000>; 1133 hysteresis = <1000>; 1134 type = "passive"; 1135 }; 1136 }; 1137 1138 cooling-maps { 1139 map0 { 1140 trip = <&target>; 1141 contribution = <1024>; 1142 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1143 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1144 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1145 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1146 }; 1147 map1 { 1148 trip = <&target>; 1149 contribution = <512>; 1150 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1151 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1152 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1153 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1154 }; 1155 }; 1156 }; 1157 }; 1158 1159 usb3_otg_bc: usb3_otg_bc@ff200000 { 1160 compatible = "syscon", "simple-mfd"; 1161 reg = <0x0 0xff200000 0x0 0x1000>; 1162 1163 usb_phy: usb-phy { 1164 compatible = "hisilicon,hi3660-usb-phy"; 1165 #phy-cells = <0>; 1166 hisilicon,pericrg-syscon = <&crg_ctrl>; 1167 hisilicon,pctrl-syscon = <&pctrl>; 1168 hisilicon,eye-diagram-param = <0x22466e4>; 1169 }; 1170 }; 1171 1172 dwc3: usb@ff100000 { 1173 compatible = "snps,dwc3"; 1174 reg = <0x0 0xff100000 0x0 0x100000>; 1175 1176 clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, 1177 <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; 1178 clock-names = "ref", "bus_early"; 1179 1180 assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; 1181 assigned-clock-rates = <229000000>; 1182 1183 resets = <&crg_rst 0x90 8>, 1184 <&crg_rst 0x90 7>, 1185 <&crg_rst 0x90 6>, 1186 <&crg_rst 0x90 5>; 1187 1188 interrupts = <0 159 4>, <0 161 4>; 1189 phys = <&usb_phy>; 1190 phy-names = "usb3-phy"; 1191 }; 1192 }; 1193 }; 1194 1195 #include "hi3660-coresight.dtsi"
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