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sys/contrib/device-tree/src/arm64/hisilicon/hi3798cv200.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DTS File for HiSilicon Hi3798cv200 SoC. 4 * 5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #include <dt-bindings/clock/histb-clock.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/phy/phy.h> 12 #include <dt-bindings/reset/ti-syscon.h> 13 14 / { 15 compatible = "hisilicon,hi3798cv200"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu@0 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 reg = <0x0 0x0>; 33 enable-method = "psci"; 34 }; 35 36 cpu@1 { 37 compatible = "arm,cortex-a53"; 38 device_type = "cpu"; 39 reg = <0x0 0x1>; 40 enable-method = "psci"; 41 }; 42 43 cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <0x0 0x2>; 47 enable-method = "psci"; 48 }; 49 50 cpu@3 { 51 compatible = "arm,cortex-a53"; 52 device_type = "cpu"; 53 reg = <0x0 0x3>; 54 enable-method = "psci"; 55 }; 56 }; 57 58 gic: interrupt-controller@f1001000 { 59 compatible = "arm,gic-400"; 60 reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */ 61 <0x0 0xf1002000 0x0 0x100>; /* GICC */ 62 #address-cells = <0>; 63 #interrupt-cells = <3>; 64 interrupt-controller; 65 }; 66 67 timer { 68 compatible = "arm,armv8-timer"; 69 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 70 IRQ_TYPE_LEVEL_LOW)>, 71 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 72 IRQ_TYPE_LEVEL_LOW)>, 73 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 74 IRQ_TYPE_LEVEL_LOW)>, 75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 76 IRQ_TYPE_LEVEL_LOW)>; 77 }; 78 79 soc: soc@f0000000 { 80 compatible = "simple-bus"; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges = <0x0 0x0 0xf0000000 0x10000000>; 84 85 crg: clock-reset-controller@8a22000 { 86 compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd"; 87 reg = <0x8a22000 0x1000>; 88 #clock-cells = <1>; 89 #reset-cells = <2>; 90 91 gmacphyrst: reset-controller { 92 compatible = "ti,syscon-reset"; 93 #reset-cells = <1>; 94 ti,reset-bits = < 95 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) 96 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE) 97 >; 98 }; 99 }; 100 101 sysctrl: system-controller@8000000 { 102 compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; 103 reg = <0x8000000 0x1000>; 104 #clock-cells = <1>; 105 #reset-cells = <2>; 106 }; 107 108 perictrl: peripheral-controller@8a20000 { 109 compatible = "hisilicon,hi3798cv200-perictrl", "syscon", 110 "simple-mfd"; 111 reg = <0x8a20000 0x1000>; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0x0 0x8a20000 0x1000>; 115 116 usb2_phy1: usb2_phy@120 { 117 compatible = "hisilicon,hi3798cv200-usb2-phy"; 118 reg = <0x120 0x4>; 119 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; 120 resets = <&crg 0xbc 4>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 usb2_phy1_port0: phy@0 { 125 reg = <0>; 126 #phy-cells = <0>; 127 resets = <&crg 0xbc 8>; 128 }; 129 130 usb2_phy1_port1: phy@1 { 131 reg = <1>; 132 #phy-cells = <0>; 133 resets = <&crg 0xbc 9>; 134 }; 135 }; 136 137 usb2_phy2: usb2_phy@124 { 138 compatible = "hisilicon,hi3798cv200-usb2-phy"; 139 reg = <0x124 0x4>; 140 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; 141 resets = <&crg 0xbc 6>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 usb2_phy2_port0: phy@0 { 146 reg = <0>; 147 #phy-cells = <0>; 148 resets = <&crg 0xbc 10>; 149 }; 150 }; 151 152 combphy0: phy@850 { 153 compatible = "hisilicon,hi3798cv200-combphy"; 154 reg = <0x850 0x8>; 155 #phy-cells = <1>; 156 clocks = <&crg HISTB_COMBPHY0_CLK>; 157 resets = <&crg 0x188 4>; 158 assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; 159 assigned-clock-rates = <100000000>; 160 hisilicon,fixed-mode = <PHY_TYPE_USB3>; 161 }; 162 163 combphy1: phy@858 { 164 compatible = "hisilicon,hi3798cv200-combphy"; 165 reg = <0x858 0x8>; 166 #phy-cells = <1>; 167 clocks = <&crg HISTB_COMBPHY1_CLK>; 168 resets = <&crg 0x188 12>; 169 assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; 170 assigned-clock-rates = <100000000>; 171 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; 172 }; 173 }; 174 175 pmx0: pinconf@8a21000 { 176 compatible = "pinconf-single"; 177 reg = <0x8a21000 0x180>; 178 pinctrl-single,register-width = <32>; 179 pinctrl-single,function-mask = <7>; 180 pinctrl-single,gpio-range = < 181 &range 0 8 2 /* GPIO 0 */ 182 &range 8 1 0 /* GPIO 1 */ 183 &range 9 4 2 184 &range 13 1 0 185 &range 14 1 1 186 &range 15 1 0 187 &range 16 5 0 /* GPIO 2 */ 188 &range 21 3 1 189 &range 24 4 1 /* GPIO 3 */ 190 &range 28 2 2 191 &range 86 1 1 192 &range 87 1 0 193 &range 30 4 2 /* GPIO 4 */ 194 &range 34 3 0 195 &range 37 1 2 196 &range 38 3 2 /* GPIO 6 */ 197 &range 41 5 0 198 &range 46 8 1 /* GPIO 7 */ 199 &range 54 8 1 /* GPIO 8 */ 200 &range 64 7 1 /* GPIO 9 */ 201 &range 71 1 0 202 &range 72 6 1 /* GPIO 10 */ 203 &range 78 1 0 204 &range 79 1 1 205 &range 80 6 1 /* GPIO 11 */ 206 &range 70 2 1 207 &range 88 8 0 /* GPIO 12 */ 208 >; 209 210 range: gpio-range { 211 #pinctrl-single,gpio-range-cells = <3>; 212 }; 213 }; 214 215 uart0: serial@8b00000 { 216 compatible = "arm,pl011", "arm,primecell"; 217 reg = <0x8b00000 0x1000>; 218 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>; 220 clock-names = "uartclk", "apb_pclk"; 221 status = "disabled"; 222 }; 223 224 uart2: serial@8b02000 { 225 compatible = "arm,pl011", "arm,primecell"; 226 reg = <0x8b02000 0x1000>; 227 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>; 229 clock-names = "uartclk", "apb_pclk"; 230 status = "disabled"; 231 }; 232 233 i2c0: i2c@8b10000 { 234 compatible = "hisilicon,hix5hd2-i2c"; 235 reg = <0x8b10000 0x1000>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 239 clock-frequency = <400000>; 240 clocks = <&crg HISTB_I2C0_CLK>; 241 status = "disabled"; 242 }; 243 244 i2c1: i2c@8b11000 { 245 compatible = "hisilicon,hix5hd2-i2c"; 246 reg = <0x8b11000 0x1000>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 250 clock-frequency = <400000>; 251 clocks = <&crg HISTB_I2C1_CLK>; 252 status = "disabled"; 253 }; 254 255 i2c2: i2c@8b12000 { 256 compatible = "hisilicon,hix5hd2-i2c"; 257 reg = <0x8b12000 0x1000>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 261 clock-frequency = <400000>; 262 clocks = <&crg HISTB_I2C2_CLK>; 263 status = "disabled"; 264 }; 265 266 i2c3: i2c@8b13000 { 267 compatible = "hisilicon,hix5hd2-i2c"; 268 reg = <0x8b13000 0x1000>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 272 clock-frequency = <400000>; 273 clocks = <&crg HISTB_I2C3_CLK>; 274 status = "disabled"; 275 }; 276 277 i2c4: i2c@8b14000 { 278 compatible = "hisilicon,hix5hd2-i2c"; 279 reg = <0x8b14000 0x1000>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 283 clock-frequency = <400000>; 284 clocks = <&crg HISTB_I2C4_CLK>; 285 status = "disabled"; 286 }; 287 288 spi0: spi@8b1a000 { 289 compatible = "arm,pl022", "arm,primecell"; 290 reg = <0x8b1a000 0x1000>; 291 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 292 num-cs = <1>; 293 cs-gpios = <&gpio7 1 0>; 294 clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>; 295 clock-names = "sspclk", "apb_pclk"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 sd0: mmc@9820000 { 302 compatible = "snps,dw-mshc"; 303 reg = <0x9820000 0x10000>; 304 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&crg HISTB_SDIO0_CIU_CLK>, 306 <&crg HISTB_SDIO0_BIU_CLK>; 307 clock-names = "biu", "ciu"; 308 resets = <&crg 0x9c 4>; 309 reset-names = "reset"; 310 status = "disabled"; 311 }; 312 313 emmc: mmc@9830000 { 314 compatible = "hisilicon,hi3798cv200-dw-mshc"; 315 reg = <0x9830000 0x10000>; 316 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&crg HISTB_MMC_CIU_CLK>, 318 <&crg HISTB_MMC_BIU_CLK>, 319 <&crg HISTB_MMC_SAMPLE_CLK>, 320 <&crg HISTB_MMC_DRV_CLK>; 321 clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; 322 resets = <&crg 0xa0 4>; 323 reset-names = "reset"; 324 status = "disabled"; 325 }; 326 327 gpio0: gpio@8b20000 { 328 compatible = "arm,pl061", "arm,primecell"; 329 reg = <0x8b20000 0x1000>; 330 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 gpio-ranges = <&pmx0 0 0 8>; 336 clocks = <&crg HISTB_APB_CLK>; 337 clock-names = "apb_pclk"; 338 status = "disabled"; 339 }; 340 341 gpio1: gpio@8b21000 { 342 compatible = "arm,pl061", "arm,primecell"; 343 reg = <0x8b21000 0x1000>; 344 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 interrupt-controller; 348 #interrupt-cells = <2>; 349 gpio-ranges = < 350 &pmx0 0 8 1 351 &pmx0 1 9 4 352 &pmx0 5 13 1 353 &pmx0 6 14 1 354 &pmx0 7 15 1 355 >; 356 clocks = <&crg HISTB_APB_CLK>; 357 clock-names = "apb_pclk"; 358 status = "disabled"; 359 }; 360 361 gpio2: gpio@8b22000 { 362 compatible = "arm,pl061", "arm,primecell"; 363 reg = <0x8b22000 0x1000>; 364 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 interrupt-controller; 368 #interrupt-cells = <2>; 369 gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; 370 clocks = <&crg HISTB_APB_CLK>; 371 clock-names = "apb_pclk"; 372 status = "disabled"; 373 }; 374 375 gpio3: gpio@8b23000 { 376 compatible = "arm,pl061", "arm,primecell"; 377 reg = <0x8b23000 0x1000>; 378 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 gpio-ranges = < 384 &pmx0 0 24 4 385 &pmx0 4 28 2 386 &pmx0 6 86 1 387 &pmx0 7 87 1 388 >; 389 clocks = <&crg HISTB_APB_CLK>; 390 clock-names = "apb_pclk"; 391 status = "disabled"; 392 }; 393 394 gpio4: gpio@8b24000 { 395 compatible = "arm,pl061", "arm,primecell"; 396 reg = <0x8b24000 0x1000>; 397 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 398 gpio-controller; 399 #gpio-cells = <2>; 400 interrupt-controller; 401 #interrupt-cells = <2>; 402 gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; 403 clocks = <&crg HISTB_APB_CLK>; 404 clock-names = "apb_pclk"; 405 status = "disabled"; 406 }; 407 408 gpio5: gpio@8004000 { 409 compatible = "arm,pl061", "arm,primecell"; 410 reg = <0x8004000 0x1000>; 411 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 412 gpio-controller; 413 #gpio-cells = <2>; 414 interrupt-controller; 415 #interrupt-cells = <2>; 416 clocks = <&crg HISTB_APB_CLK>; 417 clock-names = "apb_pclk"; 418 status = "disabled"; 419 }; 420 421 gpio6: gpio@8b26000 { 422 compatible = "arm,pl061", "arm,primecell"; 423 reg = <0x8b26000 0x1000>; 424 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 425 gpio-controller; 426 #gpio-cells = <2>; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; 430 clocks = <&crg HISTB_APB_CLK>; 431 clock-names = "apb_pclk"; 432 status = "disabled"; 433 }; 434 435 gpio7: gpio@8b27000 { 436 compatible = "arm,pl061", "arm,primecell"; 437 reg = <0x8b27000 0x1000>; 438 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 gpio-ranges = <&pmx0 0 46 8>; 444 clocks = <&crg HISTB_APB_CLK>; 445 clock-names = "apb_pclk"; 446 status = "disabled"; 447 }; 448 449 gpio8: gpio@8b28000 { 450 compatible = "arm,pl061", "arm,primecell"; 451 reg = <0x8b28000 0x1000>; 452 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 453 gpio-controller; 454 #gpio-cells = <2>; 455 interrupt-controller; 456 #interrupt-cells = <2>; 457 gpio-ranges = <&pmx0 0 54 8>; 458 clocks = <&crg HISTB_APB_CLK>; 459 clock-names = "apb_pclk"; 460 status = "disabled"; 461 }; 462 463 gpio9: gpio@8b29000 { 464 compatible = "arm,pl061", "arm,primecell"; 465 reg = <0x8b29000 0x1000>; 466 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; 472 clocks = <&crg HISTB_APB_CLK>; 473 clock-names = "apb_pclk"; 474 status = "disabled"; 475 }; 476 477 gpio10: gpio@8b2a000 { 478 compatible = "arm,pl061", "arm,primecell"; 479 reg = <0x8b2a000 0x1000>; 480 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 481 gpio-controller; 482 #gpio-cells = <2>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; 486 clocks = <&crg HISTB_APB_CLK>; 487 clock-names = "apb_pclk"; 488 status = "disabled"; 489 }; 490 491 gpio11: gpio@8b2b000 { 492 compatible = "arm,pl061", "arm,primecell"; 493 reg = <0x8b2b000 0x1000>; 494 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 495 gpio-controller; 496 #gpio-cells = <2>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; 500 clocks = <&crg HISTB_APB_CLK>; 501 clock-names = "apb_pclk"; 502 status = "disabled"; 503 }; 504 505 gpio12: gpio@8b2c000 { 506 compatible = "arm,pl061", "arm,primecell"; 507 reg = <0x8b2c000 0x1000>; 508 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 509 gpio-controller; 510 #gpio-cells = <2>; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 gpio-ranges = <&pmx0 0 88 8>; 514 clocks = <&crg HISTB_APB_CLK>; 515 clock-names = "apb_pclk"; 516 status = "disabled"; 517 }; 518 519 gmac0: ethernet@9840000 { 520 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 521 reg = <0x9840000 0x1000>, 522 <0x984300c 0x4>; 523 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&crg HISTB_ETH0_MAC_CLK>, 525 <&crg HISTB_ETH0_MACIF_CLK>; 526 clock-names = "mac_core", "mac_ifc"; 527 resets = <&crg 0xcc 8>, 528 <&crg 0xcc 10>, 529 <&gmacphyrst 0>; 530 reset-names = "mac_core", "mac_ifc", "phy"; 531 status = "disabled"; 532 }; 533 534 gmac1: ethernet@9841000 { 535 compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; 536 reg = <0x9841000 0x1000>, 537 <0x9843010 0x4>; 538 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&crg HISTB_ETH1_MAC_CLK>, 540 <&crg HISTB_ETH1_MACIF_CLK>; 541 clock-names = "mac_core", "mac_ifc"; 542 resets = <&crg 0xcc 9>, 543 <&crg 0xcc 11>, 544 <&gmacphyrst 1>; 545 reset-names = "mac_core", "mac_ifc", "phy"; 546 status = "disabled"; 547 }; 548 549 ir: ir@8001000 { 550 compatible = "hisilicon,hix5hd2-ir"; 551 reg = <0x8001000 0x1000>; 552 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&sysctrl HISTB_IR_CLK>; 554 status = "disabled"; 555 }; 556 557 pcie: pcie@9860000 { 558 compatible = "hisilicon,hi3798cv200-pcie"; 559 reg = <0x9860000 0x1000>, 560 <0x0 0x2000>, 561 <0x2000000 0x01000000>; 562 reg-names = "control", "rc-dbi", "config"; 563 #address-cells = <3>; 564 #size-cells = <2>; 565 device_type = "pci"; 566 bus-range = <0x00 0xff>; 567 num-lanes = <1>; 568 ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000>, 569 <0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; 570 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 571 interrupt-names = "msi"; 572 #interrupt-cells = <1>; 573 interrupt-map-mask = <0 0 0 0>; 574 interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&crg HISTB_PCIE_AUX_CLK>, 576 <&crg HISTB_PCIE_PIPE_CLK>, 577 <&crg HISTB_PCIE_SYS_CLK>, 578 <&crg HISTB_PCIE_BUS_CLK>; 579 clock-names = "aux", "pipe", "sys", "bus"; 580 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; 581 reset-names = "soft", "sys", "bus"; 582 phys = <&combphy1 PHY_TYPE_PCIE>; 583 phy-names = "phy"; 584 status = "disabled"; 585 }; 586 587 ohci: usb@9880000 { 588 compatible = "generic-ohci"; 589 reg = <0x9880000 0x10000>; 590 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&crg HISTB_USB2_BUS_CLK>, 592 <&crg HISTB_USB2_12M_CLK>, 593 <&crg HISTB_USB2_48M_CLK>; 594 clock-names = "bus", "clk12", "clk48"; 595 resets = <&crg 0xb8 12>; 596 reset-names = "bus"; 597 phys = <&usb2_phy1_port0>; 598 phy-names = "usb"; 599 status = "disabled"; 600 }; 601 602 ehci: usb@9890000 { 603 compatible = "generic-ehci"; 604 reg = <0x9890000 0x10000>; 605 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&crg HISTB_USB2_BUS_CLK>, 607 <&crg HISTB_USB2_PHY_CLK>, 608 <&crg HISTB_USB2_UTMI_CLK>; 609 clock-names = "bus", "phy", "utmi"; 610 resets = <&crg 0xb8 12>, 611 <&crg 0xb8 16>, 612 <&crg 0xb8 13>; 613 reset-names = "bus", "phy", "utmi"; 614 phys = <&usb2_phy1_port0>; 615 phy-names = "usb"; 616 status = "disabled"; 617 }; 618 }; 619 };
Cache object: 941d15ea32c24ee7eef272997ab5d251
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