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sys/contrib/device-tree/src/arm64/hisilicon/hikey960-pinctrl.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pinctrl dts fils for Hislicon HiKey960 development board 4 * 5 */ 6 7 #include <dt-bindings/pinctrl/hisi.h> 8 9 / { 10 soc { 11 /* [IOMG_000, IOMG_123] */ 12 range: gpio-range { 13 #pinctrl-single,gpio-range-cells = <3>; 14 }; 15 16 pmx0: pinmux@e896c000 { 17 compatible = "pinctrl-single"; 18 reg = <0x0 0xe896c000 0x0 0x1f0>; 19 #pinctrl-cells = <1>; 20 #gpio-range-cells = <0x3>; 21 pinctrl-single,register-width = <0x20>; 22 pinctrl-single,function-mask = <0x7>; 23 /* pin base, nr pins & gpio function */ 24 pinctrl-single,gpio-range = < 25 &range 0 7 0 26 &range 8 116 0>; 27 28 pmu_pmx_func: pmu_pmx_func { 29 pinctrl-single,pins = < 30 0x008 MUX_M1 /* PMU1_SSI */ 31 0x00c MUX_M1 /* PMU2_SSI */ 32 0x010 MUX_M1 /* PMU_CLKOUT */ 33 0x100 MUX_M1 /* PMU_HKADC_SSI */ 34 >; 35 }; 36 37 csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func { 38 pinctrl-single,pins = < 39 0x044 MUX_M0 /* CSI0_PWD_N */ 40 >; 41 }; 42 43 csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func { 44 pinctrl-single,pins = < 45 0x04c MUX_M0 /* CSI1_PWD_N */ 46 >; 47 }; 48 49 isp0_pmx_func: isp0_pmx_func { 50 pinctrl-single,pins = < 51 0x058 MUX_M1 /* ISP_CLK0 */ 52 0x064 MUX_M1 /* ISP_SCL0 */ 53 0x068 MUX_M1 /* ISP_SDA0 */ 54 >; 55 }; 56 57 isp1_pmx_func: isp1_pmx_func { 58 pinctrl-single,pins = < 59 0x05c MUX_M1 /* ISP_CLK1 */ 60 0x06c MUX_M1 /* ISP_SCL1 */ 61 0x070 MUX_M1 /* ISP_SDA1 */ 62 >; 63 }; 64 65 pwr_key_pmx_func: pwr_key_pmx_func { 66 pinctrl-single,pins = < 67 0x080 MUX_M0 /* GPIO_034 */ 68 >; 69 }; 70 71 i2c3_pmx_func: i2c3_pmx_func { 72 pinctrl-single,pins = < 73 0x02c MUX_M1 /* I2C3_SCL */ 74 0x030 MUX_M1 /* I2C3_SDA */ 75 >; 76 }; 77 78 i2c4_pmx_func: i2c4_pmx_func { 79 pinctrl-single,pins = < 80 0x090 MUX_M1 /* I2C4_SCL */ 81 0x094 MUX_M1 /* I2C4_SDA */ 82 >; 83 }; 84 85 pcie_perstn_pmx_func: pcie_perstn_pmx_func { 86 pinctrl-single,pins = < 87 0x15c MUX_M1 /* PCIE_PERST_N */ 88 >; 89 }; 90 91 usbhub5734_pmx_func: usbhub5734_pmx_func { 92 pinctrl-single,pins = < 93 0x11c MUX_M0 /* GPIO_073 */ 94 0x120 MUX_M0 /* GPIO_074 */ 95 >; 96 }; 97 98 uart0_pmx_func: uart0_pmx_func { 99 pinctrl-single,pins = < 100 0x0cc MUX_M2 /* UART0_RXD */ 101 0x0d0 MUX_M2 /* UART0_TXD */ 102 >; 103 }; 104 105 uart1_pmx_func: uart1_pmx_func { 106 pinctrl-single,pins = < 107 0x0b0 MUX_M2 /* UART1_CTS_N */ 108 0x0b4 MUX_M2 /* UART1_RTS_N */ 109 0x0a8 MUX_M2 /* UART1_RXD */ 110 0x0ac MUX_M2 /* UART1_TXD */ 111 >; 112 }; 113 114 uart2_pmx_func: uart2_pmx_func { 115 pinctrl-single,pins = < 116 0x0bc MUX_M2 /* UART2_CTS_N */ 117 0x0c0 MUX_M2 /* UART2_RTS_N */ 118 0x0c8 MUX_M2 /* UART2_RXD */ 119 0x0c4 MUX_M2 /* UART2_TXD */ 120 >; 121 }; 122 123 uart3_pmx_func: uart3_pmx_func { 124 pinctrl-single,pins = < 125 0x0dc MUX_M1 /* UART3_CTS_N */ 126 0x0e0 MUX_M1 /* UART3_RTS_N */ 127 0x0e4 MUX_M1 /* UART3_RXD */ 128 0x0e8 MUX_M1 /* UART3_TXD */ 129 >; 130 }; 131 132 uart4_pmx_func: uart4_pmx_func { 133 pinctrl-single,pins = < 134 0x0ec MUX_M1 /* UART4_CTS_N */ 135 0x0f0 MUX_M1 /* UART4_RTS_N */ 136 0x0f4 MUX_M1 /* UART4_RXD */ 137 0x0f8 MUX_M1 /* UART4_TXD */ 138 >; 139 }; 140 141 uart5_pmx_func: uart5_pmx_func { 142 pinctrl-single,pins = < 143 0x0c4 MUX_M3 /* UART5_CTS_N */ 144 0x0c8 MUX_M3 /* UART5_RTS_N */ 145 0x0bc MUX_M3 /* UART5_RXD */ 146 0x0c0 MUX_M3 /* UART5_TXD */ 147 >; 148 }; 149 150 uart6_pmx_func: uart6_pmx_func { 151 pinctrl-single,pins = < 152 0x0cc MUX_M1 /* UART6_CTS_N */ 153 0x0d0 MUX_M1 /* UART6_RTS_N */ 154 0x0d4 MUX_M1 /* UART6_RXD */ 155 0x0d8 MUX_M1 /* UART6_TXD */ 156 >; 157 }; 158 159 cam0_rst_pmx_func: cam0_rst_pmx_func { 160 pinctrl-single,pins = < 161 0x0c8 MUX_M0 /* CAM0_RST */ 162 >; 163 }; 164 165 cam1_rst_pmx_func: cam1_rst_pmx_func { 166 pinctrl-single,pins = < 167 0x124 MUX_M0 /* CAM1_RST */ 168 >; 169 }; 170 }; 171 172 /* [IOMG_MMC0_000, IOMG_MMC0_005] */ 173 pmx1: pinmux@ff37e000 { 174 compatible = "pinctrl-single"; 175 reg = <0x0 0xff37e000 0x0 0x18>; 176 #gpio-range-cells = <0x3>; 177 #pinctrl-cells = <1>; 178 pinctrl-single,register-width = <0x20>; 179 pinctrl-single,function-mask = <0x7>; 180 /* pin base, nr pins & gpio function */ 181 pinctrl-single,gpio-range = <&range 0 6 0>; 182 183 sd_pmx_func: sd_pmx_func { 184 pinctrl-single,pins = < 185 0x000 MUX_M1 /* SD_CLK */ 186 0x004 MUX_M1 /* SD_CMD */ 187 0x008 MUX_M1 /* SD_DATA0 */ 188 0x00c MUX_M1 /* SD_DATA1 */ 189 0x010 MUX_M1 /* SD_DATA2 */ 190 0x014 MUX_M1 /* SD_DATA3 */ 191 >; 192 }; 193 }; 194 195 /* [IOMG_FIX_000, IOMG_FIX_011] */ 196 pmx2: pinmux@ff3b6000 { 197 compatible = "pinctrl-single"; 198 reg = <0x0 0xff3b6000 0x0 0x30>; 199 #pinctrl-cells = <1>; 200 #gpio-range-cells = <0x3>; 201 pinctrl-single,register-width = <0x20>; 202 pinctrl-single,function-mask = <0x7>; 203 /* pin base, nr pins & gpio function */ 204 pinctrl-single,gpio-range = <&range 0 12 0>; 205 206 ufs_pmx_func: ufs_pmx_func { 207 pinctrl-single,pins = < 208 0x000 MUX_M1 /* UFS_REF_CLK */ 209 0x004 MUX_M1 /* UFS_RST_N */ 210 >; 211 }; 212 213 spi3_pmx_func: spi3_pmx_func { 214 pinctrl-single,pins = < 215 0x008 MUX_M1 /* SPI3_CLK */ 216 0x00c MUX_M1 /* SPI3_DI */ 217 0x010 MUX_M1 /* SPI3_DO */ 218 0x014 MUX_M1 /* SPI3_CS0_N */ 219 >; 220 }; 221 }; 222 223 /* [IOMG_MMC1_000, IOMG_MMC1_005] */ 224 pmx3: pinmux@ff3fd000 { 225 compatible = "pinctrl-single"; 226 reg = <0x0 0xff3fd000 0x0 0x18>; 227 #pinctrl-cells = <1>; 228 #gpio-range-cells = <0x3>; 229 pinctrl-single,register-width = <0x20>; 230 pinctrl-single,function-mask = <0x7>; 231 /* pin base, nr pins & gpio function */ 232 pinctrl-single,gpio-range = <&range 0 6 0>; 233 234 sdio_pmx_func: sdio_pmx_func { 235 pinctrl-single,pins = < 236 0x000 MUX_M1 /* SDIO_CLK */ 237 0x004 MUX_M1 /* SDIO_CMD */ 238 0x008 MUX_M1 /* SDIO_DATA0 */ 239 0x00c MUX_M1 /* SDIO_DATA1 */ 240 0x010 MUX_M1 /* SDIO_DATA2 */ 241 0x014 MUX_M1 /* SDIO_DATA3 */ 242 >; 243 }; 244 }; 245 246 /* [IOMG_AO_000, IOMG_AO_041] */ 247 pmx4: pinmux@fff11000 { 248 compatible = "pinctrl-single"; 249 reg = <0x0 0xfff11000 0x0 0xa8>; 250 #pinctrl-cells = <1>; 251 #gpio-range-cells = <0x3>; 252 pinctrl-single,register-width = <0x20>; 253 pinctrl-single,function-mask = <0x7>; 254 /* pin base in node, nr pins & gpio function */ 255 pinctrl-single,gpio-range = <&range 0 42 0>; 256 257 i2s2_pmx_func: i2s2_pmx_func { 258 pinctrl-single,pins = < 259 0x044 MUX_M1 /* I2S2_DI */ 260 0x048 MUX_M1 /* I2S2_DO */ 261 0x04c MUX_M1 /* I2S2_XCLK */ 262 0x050 MUX_M1 /* I2S2_XFS */ 263 >; 264 }; 265 266 slimbus_pmx_func: slimbus_pmx_func { 267 pinctrl-single,pins = < 268 0x02c MUX_M1 /* SLIMBUS_CLK */ 269 0x030 MUX_M1 /* SLIMBUS_DATA */ 270 >; 271 }; 272 273 i2c0_pmx_func: i2c0_pmx_func { 274 pinctrl-single,pins = < 275 0x014 MUX_M1 /* I2C0_SCL */ 276 0x018 MUX_M1 /* I2C0_SDA */ 277 >; 278 }; 279 280 i2c1_pmx_func: i2c1_pmx_func { 281 pinctrl-single,pins = < 282 0x01c MUX_M1 /* I2C1_SCL */ 283 0x020 MUX_M1 /* I2C1_SDA */ 284 >; 285 }; 286 287 i2c7_pmx_func: i2c7_pmx_func { 288 pinctrl-single,pins = < 289 0x024 MUX_M3 /* I2C7_SCL */ 290 0x028 MUX_M3 /* I2C7_SDA */ 291 >; 292 }; 293 294 pcie_pmx_func: pcie_pmx_func { 295 pinctrl-single,pins = < 296 0x084 MUX_M1 /* PCIE_CLKREQ_N */ 297 0x088 MUX_M1 /* PCIE_WAKE_N */ 298 >; 299 }; 300 301 spi2_pmx_func: spi2_pmx_func { 302 pinctrl-single,pins = < 303 0x08c MUX_M1 /* SPI2_CLK */ 304 0x090 MUX_M1 /* SPI2_DI */ 305 0x094 MUX_M1 /* SPI2_DO */ 306 0x098 MUX_M1 /* SPI2_CS0_N */ 307 >; 308 }; 309 310 i2s0_pmx_func: i2s0_pmx_func { 311 pinctrl-single,pins = < 312 0x034 MUX_M1 /* I2S0_DI */ 313 0x038 MUX_M1 /* I2S0_DO */ 314 0x03c MUX_M1 /* I2S0_XCLK */ 315 0x040 MUX_M1 /* I2S0_XFS */ 316 >; 317 }; 318 }; 319 320 pmx5: pinmux@e896c800 { 321 compatible = "pinconf-single"; 322 reg = <0x0 0xe896c800 0x0 0x200>; 323 #pinctrl-cells = <1>; 324 pinctrl-single,register-width = <0x20>; 325 326 pmu_cfg_func: pmu_cfg_func { 327 pinctrl-single,pins = < 328 0x010 0x0 /* PMU1_SSI */ 329 0x014 0x0 /* PMU2_SSI */ 330 0x018 0x0 /* PMU_CLKOUT */ 331 0x10c 0x0 /* PMU_HKADC_SSI */ 332 >; 333 pinctrl-single,bias-pulldown = < 334 PULL_DIS 335 PULL_DOWN 336 PULL_DIS 337 PULL_DOWN 338 >; 339 pinctrl-single,bias-pullup = < 340 PULL_DIS 341 PULL_UP 342 PULL_DIS 343 PULL_UP 344 >; 345 pinctrl-single,drive-strength = < 346 DRIVE7_06MA DRIVE6_MASK 347 >; 348 }; 349 350 i2c3_cfg_func: i2c3_cfg_func { 351 pinctrl-single,pins = < 352 0x038 0x0 /* I2C3_SCL */ 353 0x03c 0x0 /* I2C3_SDA */ 354 >; 355 pinctrl-single,bias-pulldown = < 356 PULL_DIS 357 PULL_DOWN 358 PULL_DIS 359 PULL_DOWN 360 >; 361 pinctrl-single,bias-pullup = < 362 PULL_DIS 363 PULL_UP 364 PULL_DIS 365 PULL_UP 366 >; 367 pinctrl-single,drive-strength = < 368 DRIVE7_02MA DRIVE6_MASK 369 >; 370 }; 371 372 csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func { 373 pinctrl-single,pins = < 374 0x050 0x0 /* CSI0_PWD_N */ 375 >; 376 pinctrl-single,bias-pulldown = < 377 PULL_DIS 378 PULL_DOWN 379 PULL_DIS 380 PULL_DOWN 381 >; 382 pinctrl-single,bias-pullup = < 383 PULL_DIS 384 PULL_UP 385 PULL_DIS 386 PULL_UP 387 >; 388 pinctrl-single,drive-strength = < 389 DRIVE7_04MA DRIVE6_MASK 390 >; 391 }; 392 393 csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func { 394 pinctrl-single,pins = < 395 0x058 0x0 /* CSI1_PWD_N */ 396 >; 397 pinctrl-single,bias-pulldown = < 398 PULL_DIS 399 PULL_DOWN 400 PULL_DIS 401 PULL_DOWN 402 >; 403 pinctrl-single,bias-pullup = < 404 PULL_DIS 405 PULL_UP 406 PULL_DIS 407 PULL_UP 408 >; 409 pinctrl-single,drive-strength = < 410 DRIVE7_04MA DRIVE6_MASK 411 >; 412 }; 413 414 isp0_cfg_func: isp0_cfg_func { 415 pinctrl-single,pins = < 416 0x064 0x0 /* ISP_CLK0 */ 417 0x070 0x0 /* ISP_SCL0 */ 418 0x074 0x0 /* ISP_SDA0 */ 419 >; 420 pinctrl-single,bias-pulldown = < 421 PULL_DIS 422 PULL_DOWN 423 PULL_DIS 424 PULL_DOWN 425 >; 426 pinctrl-single,bias-pullup = < 427 PULL_DIS 428 PULL_UP 429 PULL_DIS 430 PULL_UP 431 >; 432 pinctrl-single,drive-strength = < 433 DRIVE7_04MA DRIVE6_MASK>; 434 }; 435 436 isp1_cfg_func: isp1_cfg_func { 437 pinctrl-single,pins = < 438 0x068 0x0 /* ISP_CLK1 */ 439 0x078 0x0 /* ISP_SCL1 */ 440 0x07c 0x0 /* ISP_SDA1 */ 441 >; 442 pinctrl-single,bias-pulldown = < 443 PULL_DIS 444 PULL_DOWN 445 PULL_DIS 446 PULL_DOWN 447 >; 448 pinctrl-single,bias-pullup = < 449 PULL_DIS 450 PULL_UP 451 PULL_DIS 452 PULL_UP 453 >; 454 pinctrl-single,drive-strength = < 455 DRIVE7_04MA DRIVE6_MASK 456 >; 457 }; 458 459 pwr_key_cfg_func: pwr_key_cfg_func { 460 pinctrl-single,pins = < 461 0x08c 0x0 /* GPIO_034 */ 462 >; 463 pinctrl-single,bias-pulldown = < 464 PULL_DIS 465 PULL_DOWN 466 PULL_DIS 467 PULL_DOWN 468 >; 469 pinctrl-single,bias-pullup = < 470 PULL_DIS 471 PULL_UP 472 PULL_DIS 473 PULL_UP 474 >; 475 pinctrl-single,drive-strength = < 476 DRIVE7_02MA DRIVE6_MASK 477 >; 478 }; 479 480 uart1_cfg_func: uart1_cfg_func { 481 pinctrl-single,pins = < 482 0x0b4 0x0 /* UART1_RXD */ 483 0x0b8 0x0 /* UART1_TXD */ 484 0x0bc 0x0 /* UART1_CTS_N */ 485 0x0c0 0x0 /* UART1_RTS_N */ 486 >; 487 pinctrl-single,bias-pulldown = < 488 PULL_DIS 489 PULL_DOWN 490 PULL_DIS 491 PULL_DOWN 492 >; 493 pinctrl-single,bias-pullup = < 494 PULL_DIS 495 PULL_UP 496 PULL_DIS 497 PULL_UP 498 >; 499 pinctrl-single,drive-strength = < 500 DRIVE7_02MA DRIVE6_MASK 501 >; 502 }; 503 504 uart2_cfg_func: uart2_cfg_func { 505 pinctrl-single,pins = < 506 0x0c8 0x0 /* UART2_CTS_N */ 507 0x0cc 0x0 /* UART2_RTS_N */ 508 0x0d0 0x0 /* UART2_TXD */ 509 0x0d4 0x0 /* UART2_RXD */ 510 >; 511 pinctrl-single,bias-pulldown = < 512 PULL_DIS 513 PULL_DOWN 514 PULL_DIS 515 PULL_DOWN 516 >; 517 pinctrl-single,bias-pullup = < 518 PULL_DIS 519 PULL_UP 520 PULL_DIS 521 PULL_UP 522 >; 523 pinctrl-single,drive-strength = < 524 DRIVE7_02MA DRIVE6_MASK 525 >; 526 }; 527 528 uart5_cfg_func: uart5_cfg_func { 529 pinctrl-single,pins = < 530 0x0c8 0x0 /* UART5_RXD */ 531 0x0cc 0x0 /* UART5_TXD */ 532 0x0d0 0x0 /* UART5_CTS_N */ 533 0x0d4 0x0 /* UART5_RTS_N */ 534 >; 535 pinctrl-single,bias-pulldown = < 536 PULL_DIS 537 PULL_DOWN 538 PULL_DIS 539 PULL_DOWN 540 >; 541 pinctrl-single,bias-pullup = < 542 PULL_DIS 543 PULL_UP 544 PULL_DIS 545 PULL_UP 546 >; 547 pinctrl-single,drive-strength = < 548 DRIVE7_02MA DRIVE6_MASK 549 >; 550 }; 551 552 cam0_rst_cfg_func: cam0_rst_cfg_func { 553 pinctrl-single,pins = < 554 0x0d4 0x0 /* CAM0_RST */ 555 >; 556 pinctrl-single,bias-pulldown = < 557 PULL_DIS 558 PULL_DOWN 559 PULL_DIS 560 PULL_DOWN 561 >; 562 pinctrl-single,bias-pullup = < 563 PULL_DIS 564 PULL_UP 565 PULL_DIS 566 PULL_UP 567 >; 568 pinctrl-single,drive-strength = < 569 DRIVE7_04MA DRIVE6_MASK 570 >; 571 }; 572 573 uart0_cfg_func: uart0_cfg_func { 574 pinctrl-single,pins = < 575 0x0d8 0x0 /* UART0_RXD */ 576 0x0dc 0x0 /* UART0_TXD */ 577 >; 578 pinctrl-single,bias-pulldown = < 579 PULL_DIS 580 PULL_DOWN 581 PULL_DIS 582 PULL_DOWN 583 >; 584 pinctrl-single,bias-pullup = < 585 PULL_DIS 586 PULL_UP 587 PULL_DIS 588 PULL_UP 589 >; 590 pinctrl-single,drive-strength = < 591 DRIVE7_02MA DRIVE6_MASK 592 >; 593 }; 594 595 uart6_cfg_func: uart6_cfg_func { 596 pinctrl-single,pins = < 597 0x0d8 0x0 /* UART6_CTS_N */ 598 0x0dc 0x0 /* UART6_RTS_N */ 599 0x0e0 0x0 /* UART6_RXD */ 600 0x0e4 0x0 /* UART6_TXD */ 601 >; 602 pinctrl-single,bias-pulldown = < 603 PULL_DIS 604 PULL_DOWN 605 PULL_DIS 606 PULL_DOWN 607 >; 608 pinctrl-single,bias-pullup = < 609 PULL_DIS 610 PULL_UP 611 PULL_DIS 612 PULL_UP 613 >; 614 pinctrl-single,drive-strength = < 615 DRIVE7_02MA DRIVE6_MASK 616 >; 617 }; 618 619 uart3_cfg_func: uart3_cfg_func { 620 pinctrl-single,pins = < 621 0x0e8 0x0 /* UART3_CTS_N */ 622 0x0ec 0x0 /* UART3_RTS_N */ 623 0x0f0 0x0 /* UART3_RXD */ 624 0x0f4 0x0 /* UART3_TXD */ 625 >; 626 pinctrl-single,bias-pulldown = < 627 PULL_DIS 628 PULL_DOWN 629 PULL_DIS 630 PULL_DOWN 631 >; 632 pinctrl-single,bias-pullup = < 633 PULL_DIS 634 PULL_UP 635 PULL_DIS 636 PULL_UP 637 >; 638 pinctrl-single,drive-strength = < 639 DRIVE7_02MA DRIVE6_MASK 640 >; 641 }; 642 643 uart4_cfg_func: uart4_cfg_func { 644 pinctrl-single,pins = < 645 0x0f8 0x0 /* UART4_CTS_N */ 646 0x0fc 0x0 /* UART4_RTS_N */ 647 0x100 0x0 /* UART4_RXD */ 648 0x104 0x0 /* UART4_TXD */ 649 >; 650 pinctrl-single,bias-pulldown = < 651 PULL_DIS 652 PULL_DOWN 653 PULL_DIS 654 PULL_DOWN 655 >; 656 pinctrl-single,bias-pullup = < 657 PULL_DIS 658 PULL_UP 659 PULL_DIS 660 PULL_UP 661 >; 662 pinctrl-single,drive-strength = < 663 DRIVE7_02MA DRIVE6_MASK 664 >; 665 }; 666 667 cam1_rst_cfg_func: cam1_rst_cfg_func { 668 pinctrl-single,pins = < 669 0x130 0x0 /* CAM1_RST */ 670 >; 671 pinctrl-single,bias-pulldown = < 672 PULL_DIS 673 PULL_DOWN 674 PULL_DIS 675 PULL_DOWN 676 >; 677 pinctrl-single,bias-pullup = < 678 PULL_DIS 679 PULL_UP 680 PULL_DIS 681 PULL_UP 682 >; 683 pinctrl-single,drive-strength = < 684 DRIVE7_04MA DRIVE6_MASK 685 >; 686 }; 687 }; 688 689 pmx6: pinmux@ff3b6800 { 690 compatible = "pinconf-single"; 691 reg = <0x0 0xff3b6800 0x0 0x18>; 692 #pinctrl-cells = <1>; 693 pinctrl-single,register-width = <0x20>; 694 695 ufs_cfg_func: ufs_cfg_func { 696 pinctrl-single,pins = < 697 0x000 0x0 /* UFS_REF_CLK */ 698 0x004 0x0 /* UFS_RST_N */ 699 >; 700 pinctrl-single,bias-pulldown = < 701 PULL_DIS 702 PULL_DOWN 703 PULL_DIS 704 PULL_DOWN 705 >; 706 pinctrl-single,bias-pullup = < 707 PULL_DIS 708 PULL_UP 709 PULL_DIS 710 PULL_UP 711 >; 712 pinctrl-single,drive-strength = < 713 DRIVE7_08MA DRIVE6_MASK 714 >; 715 }; 716 717 spi3_cfg_func: spi3_cfg_func { 718 pinctrl-single,pins = < 719 0x008 0x0 /* SPI3_CLK */ 720 0x00c 0x0 /* SPI3_DI */ 721 0x010 0x0 /* SPI3_DO */ 722 0x014 0x0 /* SPI3_CS0_N */ 723 >; 724 pinctrl-single,bias-pulldown = < 725 PULL_DIS 726 PULL_DOWN 727 PULL_DIS 728 PULL_DOWN 729 >; 730 pinctrl-single,bias-pullup = < 731 PULL_DIS 732 PULL_UP 733 PULL_DIS 734 PULL_UP 735 >; 736 pinctrl-single,drive-strength = < 737 DRIVE7_06MA DRIVE6_MASK 738 >; 739 }; 740 }; 741 742 pmx7: pinmux@ff3fd800 { 743 compatible = "pinconf-single"; 744 reg = <0x0 0xff3fd800 0x0 0x18>; 745 #pinctrl-cells = <1>; 746 pinctrl-single,register-width = <0x20>; 747 748 sdio_clk_cfg_func: sdio_clk_cfg_func { 749 pinctrl-single,pins = < 750 0x000 0x0 /* SDIO_CLK */ 751 >; 752 pinctrl-single,bias-pulldown = < 753 PULL_DIS 754 PULL_DOWN 755 PULL_DIS 756 PULL_DOWN 757 >; 758 pinctrl-single,bias-pullup = < 759 PULL_DIS 760 PULL_UP 761 PULL_DIS 762 PULL_UP 763 >; 764 pinctrl-single,drive-strength = < 765 DRIVE6_32MA DRIVE6_MASK 766 >; 767 }; 768 769 sdio_cfg_func: sdio_cfg_func { 770 pinctrl-single,pins = < 771 0x004 0x0 /* SDIO_CMD */ 772 0x008 0x0 /* SDIO_DATA0 */ 773 0x00c 0x0 /* SDIO_DATA1 */ 774 0x010 0x0 /* SDIO_DATA2 */ 775 0x014 0x0 /* SDIO_DATA3 */ 776 >; 777 pinctrl-single,bias-pulldown = < 778 PULL_DIS 779 PULL_DOWN 780 PULL_DIS 781 PULL_DOWN 782 >; 783 pinctrl-single,bias-pullup = < 784 PULL_UP 785 PULL_UP 786 PULL_DIS 787 PULL_UP 788 >; 789 pinctrl-single,drive-strength = < 790 DRIVE6_19MA DRIVE6_MASK 791 >; 792 }; 793 }; 794 795 pmx8: pinmux@ff37e800 { 796 compatible = "pinconf-single"; 797 reg = <0x0 0xff37e800 0x0 0x18>; 798 #pinctrl-cells = <1>; 799 pinctrl-single,register-width = <0x20>; 800 801 sd_clk_cfg_func: sd_clk_cfg_func { 802 pinctrl-single,pins = < 803 0x000 0x0 /* SD_CLK */ 804 >; 805 pinctrl-single,bias-pulldown = < 806 PULL_DIS 807 PULL_DOWN 808 PULL_DIS 809 PULL_DOWN 810 >; 811 pinctrl-single,bias-pullup = < 812 PULL_DIS 813 PULL_UP 814 PULL_DIS 815 PULL_UP 816 >; 817 pinctrl-single,drive-strength = < 818 DRIVE6_32MA 819 DRIVE6_MASK 820 >; 821 }; 822 823 sd_cfg_func: sd_cfg_func { 824 pinctrl-single,pins = < 825 0x004 0x0 /* SD_CMD */ 826 0x008 0x0 /* SD_DATA0 */ 827 0x00c 0x0 /* SD_DATA1 */ 828 0x010 0x0 /* SD_DATA2 */ 829 0x014 0x0 /* SD_DATA3 */ 830 >; 831 pinctrl-single,bias-pulldown = < 832 PULL_DIS 833 PULL_DOWN 834 PULL_DIS 835 PULL_DOWN 836 >; 837 pinctrl-single,bias-pullup = < 838 PULL_UP 839 PULL_UP 840 PULL_DIS 841 PULL_UP 842 >; 843 pinctrl-single,drive-strength = < 844 DRIVE6_19MA 845 DRIVE6_MASK 846 >; 847 }; 848 }; 849 850 pmx9: pinmux@fff11800 { 851 compatible = "pinconf-single"; 852 reg = <0x0 0xfff11800 0x0 0xbc>; 853 #pinctrl-cells = <1>; 854 pinctrl-single,register-width = <0x20>; 855 856 i2c0_cfg_func: i2c0_cfg_func { 857 pinctrl-single,pins = < 858 0x01c 0x0 /* I2C0_SCL */ 859 0x020 0x0 /* I2C0_SDA */ 860 >; 861 pinctrl-single,bias-pulldown = < 862 PULL_DIS 863 PULL_DOWN 864 PULL_DIS 865 PULL_DOWN 866 >; 867 pinctrl-single,bias-pullup = < 868 PULL_UP 869 PULL_UP 870 PULL_DIS 871 PULL_UP 872 >; 873 pinctrl-single,drive-strength = < 874 DRIVE7_02MA DRIVE6_MASK 875 >; 876 }; 877 878 i2c1_cfg_func: i2c1_cfg_func { 879 pinctrl-single,pins = < 880 0x024 0x0 /* I2C1_SCL */ 881 0x028 0x0 /* I2C1_SDA */ 882 >; 883 pinctrl-single,bias-pulldown = < 884 PULL_DIS 885 PULL_DOWN 886 PULL_DIS 887 PULL_DOWN 888 >; 889 pinctrl-single,bias-pullup = < 890 PULL_UP 891 PULL_UP 892 PULL_DIS 893 PULL_UP 894 >; 895 pinctrl-single,drive-strength = < 896 DRIVE7_02MA DRIVE6_MASK 897 >; 898 }; 899 900 i2c7_cfg_func: i2c7_cfg_func { 901 pinctrl-single,pins = < 902 0x02c 0x0 /* I2C7_SCL */ 903 0x030 0x0 /* I2C7_SDA */ 904 >; 905 pinctrl-single,bias-pulldown = < 906 PULL_DIS 907 PULL_DOWN 908 PULL_DIS 909 PULL_DOWN 910 >; 911 pinctrl-single,bias-pullup = < 912 PULL_UP 913 PULL_UP 914 PULL_DIS 915 PULL_UP 916 >; 917 pinctrl-single,drive-strength = < 918 DRIVE7_02MA DRIVE6_MASK 919 >; 920 }; 921 922 slimbus_cfg_func: slimbus_cfg_func { 923 pinctrl-single,pins = < 924 0x034 0x0 /* SLIMBUS_CLK */ 925 0x038 0x0 /* SLIMBUS_DATA */ 926 >; 927 pinctrl-single,bias-pulldown = < 928 PULL_DIS 929 PULL_DOWN 930 PULL_DIS 931 PULL_DOWN 932 >; 933 pinctrl-single,bias-pullup = < 934 PULL_UP 935 PULL_UP 936 PULL_DIS 937 PULL_UP 938 >; 939 pinctrl-single,drive-strength = < 940 DRIVE7_02MA DRIVE6_MASK 941 >; 942 }; 943 944 i2s0_cfg_func: i2s0_cfg_func { 945 pinctrl-single,pins = < 946 0x040 0x0 /* I2S0_DI */ 947 0x044 0x0 /* I2S0_DO */ 948 0x048 0x0 /* I2S0_XCLK */ 949 0x04c 0x0 /* I2S0_XFS */ 950 >; 951 pinctrl-single,bias-pulldown = < 952 PULL_DIS 953 PULL_DOWN 954 PULL_DIS 955 PULL_DOWN 956 >; 957 pinctrl-single,bias-pullup = < 958 PULL_UP 959 PULL_UP 960 PULL_DIS 961 PULL_UP 962 >; 963 pinctrl-single,drive-strength = < 964 DRIVE7_02MA DRIVE6_MASK 965 >; 966 }; 967 968 i2s2_cfg_func: i2s2_cfg_func { 969 pinctrl-single,pins = < 970 0x050 0x0 /* I2S2_DI */ 971 0x054 0x0 /* I2S2_DO */ 972 0x058 0x0 /* I2S2_XCLK */ 973 0x05c 0x0 /* I2S2_XFS */ 974 >; 975 pinctrl-single,bias-pulldown = < 976 PULL_DIS 977 PULL_DOWN 978 PULL_DIS 979 PULL_DOWN 980 >; 981 pinctrl-single,bias-pullup = < 982 PULL_UP 983 PULL_UP 984 PULL_DIS 985 PULL_UP 986 >; 987 pinctrl-single,drive-strength = < 988 DRIVE7_02MA DRIVE6_MASK 989 >; 990 }; 991 992 pcie_cfg_func: pcie_cfg_func { 993 pinctrl-single,pins = < 994 0x094 0x0 /* PCIE_CLKREQ_N */ 995 0x098 0x0 /* PCIE_WAKE_N */ 996 >; 997 pinctrl-single,bias-pulldown = < 998 PULL_DIS 999 PULL_DOWN 1000 PULL_DIS 1001 PULL_DOWN 1002 >; 1003 pinctrl-single,bias-pullup = < 1004 PULL_UP 1005 PULL_UP 1006 PULL_DIS 1007 PULL_UP 1008 >; 1009 pinctrl-single,drive-strength = < 1010 DRIVE7_02MA DRIVE6_MASK 1011 >; 1012 }; 1013 1014 spi2_cfg_func: spi2_cfg_func { 1015 pinctrl-single,pins = < 1016 0x09c 0x0 /* SPI2_CLK */ 1017 0x0a0 0x0 /* SPI2_DI */ 1018 0x0a4 0x0 /* SPI2_DO */ 1019 0x0a8 0x0 /* SPI2_CS0_N */ 1020 >; 1021 pinctrl-single,bias-pulldown = < 1022 PULL_DIS 1023 PULL_DOWN 1024 PULL_DIS 1025 PULL_DOWN 1026 >; 1027 pinctrl-single,bias-pullup = < 1028 PULL_UP 1029 PULL_UP 1030 PULL_DIS 1031 PULL_UP 1032 >; 1033 pinctrl-single,drive-strength = < 1034 DRIVE7_06MA DRIVE6_MASK 1035 >; 1036 }; 1037 1038 usb_cfg_func: usb_cfg_func { 1039 pinctrl-single,pins = < 1040 0x0ac 0x0 /* GPIO_219 */ 1041 >; 1042 pinctrl-single,bias-pulldown = < 1043 PULL_DIS 1044 PULL_DOWN 1045 PULL_DIS 1046 PULL_DOWN 1047 >; 1048 pinctrl-single,bias-pullup = < 1049 PULL_UP 1050 PULL_UP 1051 PULL_DIS 1052 PULL_UP 1053 >; 1054 pinctrl-single,drive-strength = < 1055 DRIVE7_02MA DRIVE6_MASK 1056 >; 1057 }; 1058 }; 1059 }; 1060 };
Cache object: 8cfdd8039163f5d79d353a103944e502
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