mt7622-rfb1.dts

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
    1 /*
    2  * Copyright (c) 2017 MediaTek Inc.
    3  * Author: Ming Huang <ming.huang@mediatek.com>
    4  *         Sean Wang <sean.wang@mediatek.com>
    5  *
    6  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
    7  */
    8 
    9 /dts-v1/;
   10 #include <dt-bindings/input/input.h>
   11 #include <dt-bindings/gpio/gpio.h>
   12 
   13 #include "mt7622.dtsi"
   14 #include "mt6380.dtsi"
   15 
   16 / {
   17         model = "MediaTek MT7622 RFB1 board";
   18         compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
   19 
   20         aliases {
   21                 serial0 = &uart0;
   22         };
   23 
   24         chosen {
   25                 stdout-path = "serial0:115200n8";
   26                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
   27         };
   28 
   29         cpus {
   30                 cpu@0 {
   31                         proc-supply = <&mt6380_vcpu_reg>;
   32                         sram-supply = <&mt6380_vm_reg>;
   33                 };
   34 
   35                 cpu@1 {
   36                         proc-supply = <&mt6380_vcpu_reg>;
   37                         sram-supply = <&mt6380_vm_reg>;
   38                 };
   39         };
   40 
   41         gpio-keys {
   42                 compatible = "gpio-keys";
   43 
   44                 key-factory {
   45                         label = "factory";
   46                         linux,code = <BTN_0>;
   47                         gpios = <&pio 0 0>;
   48                 };
   49 
   50                 key-wps {
   51                         label = "wps";
   52                         linux,code = <KEY_WPS_BUTTON>;
   53                         gpios = <&pio 102 0>;
   54                 };
   55         };
   56 
   57         memory {
   58                 reg = <0 0x40000000 0 0x20000000>;
   59         };
   60 
   61         reg_1p8v: regulator-1p8v {
   62                 compatible = "regulator-fixed";
   63                 regulator-name = "fixed-1.8V";
   64                 regulator-min-microvolt = <1800000>;
   65                 regulator-max-microvolt = <1800000>;
   66                 regulator-always-on;
   67         };
   68 
   69         reg_3p3v: regulator-3p3v {
   70                 compatible = "regulator-fixed";
   71                 regulator-name = "fixed-3.3V";
   72                 regulator-min-microvolt = <3300000>;
   73                 regulator-max-microvolt = <3300000>;
   74                 regulator-boot-on;
   75                 regulator-always-on;
   76         };
   77 
   78         reg_5v: regulator-5v {
   79                 compatible = "regulator-fixed";
   80                 regulator-name = "fixed-5V";
   81                 regulator-min-microvolt = <5000000>;
   82                 regulator-max-microvolt = <5000000>;
   83                 regulator-boot-on;
   84                 regulator-always-on;
   85         };
   86 };
   87 
   88 &bch {
   89         status = "disabled";
   90 };
   91 
   92 &btif {
   93         status = "okay";
   94 };
   95 
   96 &cir {
   97         pinctrl-names = "default";
   98         pinctrl-0 = <&irrx_pins>;
   99         status = "okay";
  100 };
  101 
  102 &eth {
  103         pinctrl-names = "default";
  104         pinctrl-0 = <&eth_pins>;
  105         status = "okay";
  106 
  107         gmac0: mac@0 {
  108                 compatible = "mediatek,eth-mac";
  109                 reg = <0>;
  110                 phy-mode = "2500base-x";
  111 
  112                 fixed-link {
  113                         speed = <2500>;
  114                         full-duplex;
  115                         pause;
  116                 };
  117         };
  118 
  119         mdio-bus {
  120                 #address-cells = <1>;
  121                 #size-cells = <0>;
  122 
  123                 switch@0 {
  124                         compatible = "mediatek,mt7531";
  125                         reg = <0>;
  126                         reset-gpios = <&pio 54 0>;
  127 
  128                         ports {
  129                                 #address-cells = <1>;
  130                                 #size-cells = <0>;
  131 
  132                                 port@0 {
  133                                         reg = <0>;
  134                                         label = "lan0";
  135                                 };
  136 
  137                                 port@1 {
  138                                         reg = <1>;
  139                                         label = "lan1";
  140                                 };
  141 
  142                                 port@2 {
  143                                         reg = <2>;
  144                                         label = "lan2";
  145                                 };
  146 
  147                                 port@3 {
  148                                         reg = <3>;
  149                                         label = "lan3";
  150                                 };
  151 
  152                                 port@4 {
  153                                         reg = <4>;
  154                                         label = "wan";
  155                                 };
  156 
  157                                 port@6 {
  158                                         reg = <6>;
  159                                         label = "cpu";
  160                                         ethernet = <&gmac0>;
  161                                         phy-mode = "2500base-x";
  162 
  163                                         fixed-link {
  164                                                 speed = <2500>;
  165                                                 full-duplex;
  166                                                 pause;
  167                                         };
  168                                 };
  169                         };
  170                 };
  171 
  172         };
  173 };
  174 
  175 &i2c1 {
  176         pinctrl-names = "default";
  177         pinctrl-0 = <&i2c1_pins>;
  178         status = "okay";
  179 };
  180 
  181 &i2c2 {
  182         pinctrl-names = "default";
  183         pinctrl-0 = <&i2c2_pins>;
  184         status = "okay";
  185 };
  186 
  187 &mmc0 {
  188         pinctrl-names = "default", "state_uhs";
  189         pinctrl-0 = <&emmc_pins_default>;
  190         pinctrl-1 = <&emmc_pins_uhs>;
  191         status = "okay";
  192         bus-width = <8>;
  193         max-frequency = <50000000>;
  194         cap-mmc-highspeed;
  195         mmc-hs200-1_8v;
  196         vmmc-supply = <&reg_3p3v>;
  197         vqmmc-supply = <&reg_1p8v>;
  198         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
  199         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
  200         non-removable;
  201 };
  202 
  203 &mmc1 {
  204         pinctrl-names = "default", "state_uhs";
  205         pinctrl-0 = <&sd0_pins_default>;
  206         pinctrl-1 = <&sd0_pins_uhs>;
  207         status = "okay";
  208         bus-width = <4>;
  209         max-frequency = <50000000>;
  210         cap-sd-highspeed;
  211         r_smpl = <1>;
  212         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
  213         vmmc-supply = <&reg_3p3v>;
  214         vqmmc-supply = <&reg_3p3v>;
  215         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
  216         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
  217 };
  218 
  219 &nandc {
  220         pinctrl-names = "default";
  221         pinctrl-0 = <&parallel_nand_pins>;
  222         status = "disabled";
  223 };
  224 
  225 &nor_flash {
  226         pinctrl-names = "default";
  227         pinctrl-0 = <&spi_nor_pins>;
  228         status = "disabled";
  229 
  230         flash@0 {
  231                 compatible = "jedec,spi-nor";
  232                 reg = <0>;
  233         };
  234 };
  235 
  236 &pcie0 {
  237         pinctrl-names = "default";
  238         pinctrl-0 = <&pcie0_pins>;
  239         status = "okay";
  240 };
  241 
  242 &pio {
  243         /* eMMC is shared pin with parallel NAND */
  244         emmc_pins_default: emmc-pins-default {
  245                 mux {
  246                         function = "emmc", "emmc_rst";
  247                         groups = "emmc";
  248                 };
  249 
  250                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
  251                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
  252                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
  253                  */
  254                 conf-cmd-dat {
  255                         pins = "NDL0", "NDL1", "NDL2",
  256                                "NDL3", "NDL4", "NDL5",
  257                                "NDL6", "NDL7", "NRB";
  258                         input-enable;
  259                         bias-pull-up;
  260                 };
  261 
  262                 conf-clk {
  263                         pins = "NCLE";
  264                         bias-pull-down;
  265                 };
  266         };
  267 
  268         emmc_pins_uhs: emmc-pins-uhs {
  269                 mux {
  270                         function = "emmc";
  271                         groups = "emmc";
  272                 };
  273 
  274                 conf-cmd-dat {
  275                         pins = "NDL0", "NDL1", "NDL2",
  276                                "NDL3", "NDL4", "NDL5",
  277                                "NDL6", "NDL7", "NRB";
  278                         input-enable;
  279                         drive-strength = <4>;
  280                         bias-pull-up;
  281                 };
  282 
  283                 conf-clk {
  284                         pins = "NCLE";
  285                         drive-strength = <4>;
  286                         bias-pull-down;
  287                 };
  288         };
  289 
  290         eth_pins: eth-pins {
  291                 mux {
  292                         function = "eth";
  293                         groups = "mdc_mdio", "rgmii_via_gmac2";
  294                 };
  295         };
  296 
  297         i2c1_pins: i2c1-pins {
  298                 mux {
  299                         function = "i2c";
  300                         groups = "i2c1_0";
  301                 };
  302         };
  303 
  304         i2c2_pins: i2c2-pins {
  305                 mux {
  306                         function = "i2c";
  307                         groups = "i2c2_0";
  308                 };
  309         };
  310 
  311         i2s1_pins: i2s1-pins {
  312                 mux {
  313                         function = "i2s";
  314                         groups =  "i2s_out_mclk_bclk_ws",
  315                                   "i2s1_in_data",
  316                                   "i2s1_out_data";
  317                 };
  318 
  319                 conf {
  320                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
  321                                "I2S_WS", "I2S_MCLK";
  322                         drive-strength = <12>;
  323                         bias-pull-down;
  324                 };
  325         };
  326 
  327         irrx_pins: irrx-pins {
  328                 mux {
  329                         function = "ir";
  330                         groups = "ir_1_rx";
  331                 };
  332         };
  333 
  334         irtx_pins: irtx-pins {
  335                 mux {
  336                         function = "ir";
  337                         groups = "ir_1_tx";
  338                 };
  339         };
  340 
  341         /* Parallel nand is shared pin with eMMC */
  342         parallel_nand_pins: parallel-nand-pins {
  343                 mux {
  344                         function = "flash";
  345                         groups = "par_nand";
  346                 };
  347         };
  348 
  349         pcie0_pins: pcie0-pins {
  350                 mux {
  351                         function = "pcie";
  352                         groups = "pcie0_pad_perst",
  353                                  "pcie0_1_waken",
  354                                  "pcie0_1_clkreq";
  355                 };
  356         };
  357 
  358         pcie1_pins: pcie1-pins {
  359                 mux {
  360                         function = "pcie";
  361                         groups = "pcie1_pad_perst",
  362                                  "pcie1_0_waken",
  363                                  "pcie1_0_clkreq";
  364                 };
  365         };
  366 
  367         pmic_bus_pins: pmic-bus-pins {
  368                 mux {
  369                         function = "pmic";
  370                         groups = "pmic_bus";
  371                 };
  372         };
  373 
  374         pwm7_pins: pwm1-2-pins {
  375                 mux {
  376                         function = "pwm";
  377                         groups = "pwm_ch7_2";
  378                 };
  379         };
  380 
  381         wled_pins: wled-pins {
  382                 mux {
  383                         function = "led";
  384                         groups = "wled";
  385                 };
  386         };
  387 
  388         sd0_pins_default: sd0-pins-default {
  389                 mux {
  390                         function = "sd";
  391                         groups = "sd_0";
  392                 };
  393 
  394                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
  395                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
  396                  *  DAT2, DAT3, CMD, CLK for SD respectively.
  397                  */
  398                 conf-cmd-data {
  399                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
  400                                "I2S2_IN","I2S4_OUT";
  401                         input-enable;
  402                         drive-strength = <8>;
  403                         bias-pull-up;
  404                 };
  405                 conf-clk {
  406                         pins = "I2S3_OUT";
  407                         drive-strength = <12>;
  408                         bias-pull-down;
  409                 };
  410                 conf-cd {
  411                         pins = "TXD3";
  412                         bias-pull-up;
  413                 };
  414         };
  415 
  416         sd0_pins_uhs: sd0-pins-uhs {
  417                 mux {
  418                         function = "sd";
  419                         groups = "sd_0";
  420                 };
  421 
  422                 conf-cmd-data {
  423                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
  424                                "I2S2_IN","I2S4_OUT";
  425                         input-enable;
  426                         bias-pull-up;
  427                 };
  428 
  429                 conf-clk {
  430                         pins = "I2S3_OUT";
  431                         bias-pull-down;
  432                 };
  433         };
  434 
  435         /* Serial NAND is shared pin with SPI-NOR */
  436         serial_nand_pins: serial-nand-pins {
  437                 mux {
  438                         function = "flash";
  439                         groups = "snfi";
  440                 };
  441         };
  442 
  443         spic0_pins: spic0-pins {
  444                 mux {
  445                         function = "spi";
  446                         groups = "spic0_0";
  447                 };
  448         };
  449 
  450         spic1_pins: spic1-pins {
  451                 mux {
  452                         function = "spi";
  453                         groups = "spic1_0";
  454                 };
  455         };
  456 
  457         /* SPI-NOR is shared pin with serial NAND */
  458         spi_nor_pins: spi-nor-pins {
  459                 mux {
  460                         function = "flash";
  461                         groups = "spi_nor";
  462                 };
  463         };
  464 
  465         /* serial NAND is shared pin with SPI-NOR */
  466         serial_nand_pins: serial-nand-pins {
  467                 mux {
  468                         function = "flash";
  469                         groups = "snfi";
  470                 };
  471         };
  472 
  473         uart0_pins: uart0-pins {
  474                 mux {
  475                         function = "uart";
  476                         groups = "uart0_0_tx_rx" ;
  477                 };
  478         };
  479 
  480         uart2_pins: uart2-pins {
  481                 mux {
  482                         function = "uart";
  483                         groups = "uart2_1_tx_rx" ;
  484                 };
  485         };
  486 
  487         watchdog_pins: watchdog-pins {
  488                 mux {
  489                         function = "watchdog";
  490                         groups = "watchdog";
  491                 };
  492         };
  493 
  494         wmac_pins: wmac-pins {
  495                 mux {
  496                         function = "antsel";
  497                         groups = "antsel0", "antsel1", "antsel2", "antsel3",
  498                                  "antsel4", "antsel5", "antsel6", "antsel7",
  499                                  "antsel8", "antsel9", "antsel12", "antsel13",
  500                                  "antsel14", "antsel15", "antsel16", "antsel17";
  501                 };
  502         };
  503 };
  504 
  505 &pwm {
  506         pinctrl-names = "default";
  507         pinctrl-0 = <&pwm7_pins>;
  508         status = "okay";
  509 };
  510 
  511 &pwrap {
  512         pinctrl-names = "default";
  513         pinctrl-0 = <&pmic_bus_pins>;
  514 
  515         status = "okay";
  516 };
  517 
  518 &sata {
  519         status = "okay";
  520 };
  521 
  522 &sata_phy {
  523         status = "okay";
  524 };
  525 
  526 &spi0 {
  527         pinctrl-names = "default";
  528         pinctrl-0 = <&spic0_pins>;
  529         status = "okay";
  530 };
  531 
  532 &spi1 {
  533         pinctrl-names = "default";
  534         pinctrl-0 = <&spic1_pins>;
  535         status = "okay";
  536 };
  537 
  538 &ssusb {
  539         vusb33-supply = <&reg_3p3v>;
  540         vbus-supply = <&reg_5v>;
  541         status = "okay";
  542 };
  543 
  544 &u3phy {
  545         status = "okay";
  546 };
  547 
  548 &uart0 {
  549         pinctrl-names = "default";
  550         pinctrl-0 = <&uart0_pins>;
  551         status = "okay";
  552 };
  553 
  554 &uart2 {
  555         pinctrl-names = "default";
  556         pinctrl-0 = <&uart2_pins>;
  557         status = "okay";
  558 };
  559 
  560 &watchdog {
  561         pinctrl-names = "default";
  562         pinctrl-0 = <&watchdog_pins>;
  563         status = "okay";
  564 };
  565 
  566 &wmac {
  567         pinctrl-names = "default";
  568         pinctrl-0 = <&wmac_pins>;
  569         status = "okay";
  570 };
Cache object: 6ff736f67e05ff05a4073012c5fde62c
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.
FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/mediatek/mt7622-rfb1.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/mediatek/mt7622-rfb1.dts
