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sys/contrib/device-tree/src/arm64/mediatek/mt8192.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (C) 2020 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7 /dts-v1/; 8 #include <dt-bindings/clock/mt8192-clk.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/memory/mt8192-larb-port.h> 12 #include <dt-bindings/pinctrl/mt8192-pinfunc.h> 13 #include <dt-bindings/phy/phy.h> 14 #include <dt-bindings/power/mt8192-power.h> 15 16 / { 17 compatible = "mediatek,mt8192"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clk26m: oscillator0 { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <26000000>; 26 clock-output-names = "clk26m"; 27 }; 28 29 clk32k: oscillator1 { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <32768>; 33 clock-output-names = "clk32k"; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x000>; 44 enable-method = "psci"; 45 clock-frequency = <1701000000>; 46 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 47 next-level-cache = <&l2_0>; 48 capacity-dmips-mhz = <530>; 49 }; 50 51 cpu1: cpu@100 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x100>; 55 enable-method = "psci"; 56 clock-frequency = <1701000000>; 57 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 58 next-level-cache = <&l2_0>; 59 capacity-dmips-mhz = <530>; 60 }; 61 62 cpu2: cpu@200 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a55"; 65 reg = <0x200>; 66 enable-method = "psci"; 67 clock-frequency = <1701000000>; 68 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 69 next-level-cache = <&l2_0>; 70 capacity-dmips-mhz = <530>; 71 }; 72 73 cpu3: cpu@300 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a55"; 76 reg = <0x300>; 77 enable-method = "psci"; 78 clock-frequency = <1701000000>; 79 cpu-idle-states = <&cpu_sleep_l &cluster_sleep_l>; 80 next-level-cache = <&l2_0>; 81 capacity-dmips-mhz = <530>; 82 }; 83 84 cpu4: cpu@400 { 85 device_type = "cpu"; 86 compatible = "arm,cortex-a76"; 87 reg = <0x400>; 88 enable-method = "psci"; 89 clock-frequency = <2171000000>; 90 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 91 next-level-cache = <&l2_1>; 92 capacity-dmips-mhz = <1024>; 93 }; 94 95 cpu5: cpu@500 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a76"; 98 reg = <0x500>; 99 enable-method = "psci"; 100 clock-frequency = <2171000000>; 101 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 102 next-level-cache = <&l2_1>; 103 capacity-dmips-mhz = <1024>; 104 }; 105 106 cpu6: cpu@600 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a76"; 109 reg = <0x600>; 110 enable-method = "psci"; 111 clock-frequency = <2171000000>; 112 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 113 next-level-cache = <&l2_1>; 114 capacity-dmips-mhz = <1024>; 115 }; 116 117 cpu7: cpu@700 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a76"; 120 reg = <0x700>; 121 enable-method = "psci"; 122 clock-frequency = <2171000000>; 123 cpu-idle-states = <&cpu_sleep_b &cluster_sleep_b>; 124 next-level-cache = <&l2_1>; 125 capacity-dmips-mhz = <1024>; 126 }; 127 128 cpu-map { 129 cluster0 { 130 core0 { 131 cpu = <&cpu0>; 132 }; 133 core1 { 134 cpu = <&cpu1>; 135 }; 136 core2 { 137 cpu = <&cpu2>; 138 }; 139 core3 { 140 cpu = <&cpu3>; 141 }; 142 }; 143 144 cluster1 { 145 core0 { 146 cpu = <&cpu4>; 147 }; 148 core1 { 149 cpu = <&cpu5>; 150 }; 151 core2 { 152 cpu = <&cpu6>; 153 }; 154 core3 { 155 cpu = <&cpu7>; 156 }; 157 }; 158 }; 159 160 l2_0: l2-cache0 { 161 compatible = "cache"; 162 next-level-cache = <&l3_0>; 163 }; 164 165 l2_1: l2-cache1 { 166 compatible = "cache"; 167 next-level-cache = <&l3_0>; 168 }; 169 170 l3_0: l3-cache { 171 compatible = "cache"; 172 }; 173 174 idle-states { 175 entry-method = "psci"; 176 cpu_sleep_l: cpu-sleep-l { 177 compatible = "arm,idle-state"; 178 arm,psci-suspend-param = <0x00010001>; 179 local-timer-stop; 180 entry-latency-us = <55>; 181 exit-latency-us = <140>; 182 min-residency-us = <780>; 183 }; 184 cpu_sleep_b: cpu-sleep-b { 185 compatible = "arm,idle-state"; 186 arm,psci-suspend-param = <0x00010001>; 187 local-timer-stop; 188 entry-latency-us = <35>; 189 exit-latency-us = <145>; 190 min-residency-us = <720>; 191 }; 192 cluster_sleep_l: cluster-sleep-l { 193 compatible = "arm,idle-state"; 194 arm,psci-suspend-param = <0x01010002>; 195 local-timer-stop; 196 entry-latency-us = <60>; 197 exit-latency-us = <155>; 198 min-residency-us = <860>; 199 }; 200 cluster_sleep_b: cluster-sleep-b { 201 compatible = "arm,idle-state"; 202 arm,psci-suspend-param = <0x01010002>; 203 local-timer-stop; 204 entry-latency-us = <40>; 205 exit-latency-us = <155>; 206 min-residency-us = <780>; 207 }; 208 }; 209 }; 210 211 pmu-a55 { 212 compatible = "arm,cortex-a55-pmu"; 213 interrupt-parent = <&gic>; 214 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 215 }; 216 217 pmu-a76 { 218 compatible = "arm,cortex-a76-pmu"; 219 interrupt-parent = <&gic>; 220 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 221 }; 222 223 psci { 224 compatible = "arm,psci-1.0"; 225 method = "smc"; 226 }; 227 228 timer: timer { 229 compatible = "arm,armv8-timer"; 230 interrupt-parent = <&gic>; 231 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 232 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 233 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 234 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 235 clock-frequency = <13000000>; 236 }; 237 238 soc { 239 #address-cells = <2>; 240 #size-cells = <2>; 241 compatible = "simple-bus"; 242 ranges; 243 244 gic: interrupt-controller@c000000 { 245 compatible = "arm,gic-v3"; 246 #interrupt-cells = <4>; 247 #redistributor-regions = <1>; 248 interrupt-parent = <&gic>; 249 interrupt-controller; 250 reg = <0 0x0c000000 0 0x40000>, 251 <0 0x0c040000 0 0x200000>; 252 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 253 254 ppi-partitions { 255 ppi_cluster0: interrupt-partition-0 { 256 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 257 }; 258 ppi_cluster1: interrupt-partition-1 { 259 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 260 }; 261 }; 262 }; 263 264 topckgen: syscon@10000000 { 265 compatible = "mediatek,mt8192-topckgen", "syscon"; 266 reg = <0 0x10000000 0 0x1000>; 267 #clock-cells = <1>; 268 }; 269 270 infracfg: syscon@10001000 { 271 compatible = "mediatek,mt8192-infracfg", "syscon"; 272 reg = <0 0x10001000 0 0x1000>; 273 #clock-cells = <1>; 274 #reset-cells = <1>; 275 }; 276 277 pericfg: syscon@10003000 { 278 compatible = "mediatek,mt8192-pericfg", "syscon"; 279 reg = <0 0x10003000 0 0x1000>; 280 #clock-cells = <1>; 281 }; 282 283 pio: pinctrl@10005000 { 284 compatible = "mediatek,mt8192-pinctrl"; 285 reg = <0 0x10005000 0 0x1000>, 286 <0 0x11c20000 0 0x1000>, 287 <0 0x11d10000 0 0x1000>, 288 <0 0x11d30000 0 0x1000>, 289 <0 0x11d40000 0 0x1000>, 290 <0 0x11e20000 0 0x1000>, 291 <0 0x11e70000 0 0x1000>, 292 <0 0x11ea0000 0 0x1000>, 293 <0 0x11f20000 0 0x1000>, 294 <0 0x11f30000 0 0x1000>, 295 <0 0x1000b000 0 0x1000>; 296 reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", 297 "iocfg_bl", "iocfg_br", "iocfg_lm", 298 "iocfg_lb", "iocfg_rt", "iocfg_lt", 299 "iocfg_tl", "eint"; 300 gpio-controller; 301 #gpio-cells = <2>; 302 gpio-ranges = <&pio 0 0 220>; 303 interrupt-controller; 304 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; 305 #interrupt-cells = <2>; 306 }; 307 308 scpsys: syscon@10006000 { 309 compatible = "syscon", "simple-mfd"; 310 reg = <0 0x10006000 0 0x1000>; 311 #power-domain-cells = <1>; 312 313 /* System Power Manager */ 314 spm: power-controller { 315 compatible = "mediatek,mt8192-power-controller"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 #power-domain-cells = <1>; 319 320 /* power domain of the SoC */ 321 power-domain@MT8192_POWER_DOMAIN_AUDIO { 322 reg = <MT8192_POWER_DOMAIN_AUDIO>; 323 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 324 <&infracfg CLK_INFRA_AUDIO_26M_B>, 325 <&infracfg CLK_INFRA_AUDIO>; 326 clock-names = "audio", "audio1", "audio2"; 327 mediatek,infracfg = <&infracfg>; 328 #power-domain-cells = <0>; 329 }; 330 331 power-domain@MT8192_POWER_DOMAIN_CONN { 332 reg = <MT8192_POWER_DOMAIN_CONN>; 333 clocks = <&infracfg CLK_INFRA_PMIC_CONN>; 334 clock-names = "conn"; 335 mediatek,infracfg = <&infracfg>; 336 #power-domain-cells = <0>; 337 }; 338 339 power-domain@MT8192_POWER_DOMAIN_MFG0 { 340 reg = <MT8192_POWER_DOMAIN_MFG0>; 341 clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>; 342 clock-names = "mfg"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 #power-domain-cells = <1>; 346 347 power-domain@MT8192_POWER_DOMAIN_MFG1 { 348 reg = <MT8192_POWER_DOMAIN_MFG1>; 349 mediatek,infracfg = <&infracfg>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 #power-domain-cells = <1>; 353 354 power-domain@MT8192_POWER_DOMAIN_MFG2 { 355 reg = <MT8192_POWER_DOMAIN_MFG2>; 356 #power-domain-cells = <0>; 357 }; 358 359 power-domain@MT8192_POWER_DOMAIN_MFG3 { 360 reg = <MT8192_POWER_DOMAIN_MFG3>; 361 #power-domain-cells = <0>; 362 }; 363 364 power-domain@MT8192_POWER_DOMAIN_MFG4 { 365 reg = <MT8192_POWER_DOMAIN_MFG4>; 366 #power-domain-cells = <0>; 367 }; 368 369 power-domain@MT8192_POWER_DOMAIN_MFG5 { 370 reg = <MT8192_POWER_DOMAIN_MFG5>; 371 #power-domain-cells = <0>; 372 }; 373 374 power-domain@MT8192_POWER_DOMAIN_MFG6 { 375 reg = <MT8192_POWER_DOMAIN_MFG6>; 376 #power-domain-cells = <0>; 377 }; 378 }; 379 }; 380 381 power-domain@MT8192_POWER_DOMAIN_DISP { 382 reg = <MT8192_POWER_DOMAIN_DISP>; 383 clocks = <&topckgen CLK_TOP_DISP_SEL>, 384 <&mmsys CLK_MM_SMI_INFRA>, 385 <&mmsys CLK_MM_SMI_COMMON>, 386 <&mmsys CLK_MM_SMI_GALS>, 387 <&mmsys CLK_MM_SMI_IOMMU>; 388 clock-names = "disp", "disp-0", "disp-1", "disp-2", 389 "disp-3"; 390 mediatek,infracfg = <&infracfg>; 391 #address-cells = <1>; 392 #size-cells = <0>; 393 #power-domain-cells = <1>; 394 395 power-domain@MT8192_POWER_DOMAIN_IPE { 396 reg = <MT8192_POWER_DOMAIN_IPE>; 397 clocks = <&topckgen CLK_TOP_IPE_SEL>, 398 <&ipesys CLK_IPE_LARB19>, 399 <&ipesys CLK_IPE_LARB20>, 400 <&ipesys CLK_IPE_SMI_SUBCOM>, 401 <&ipesys CLK_IPE_GALS>; 402 clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2", 403 "ipe-3"; 404 mediatek,infracfg = <&infracfg>; 405 #power-domain-cells = <0>; 406 }; 407 408 power-domain@MT8192_POWER_DOMAIN_ISP { 409 reg = <MT8192_POWER_DOMAIN_ISP>; 410 clocks = <&topckgen CLK_TOP_IMG1_SEL>, 411 <&imgsys CLK_IMG_LARB9>, 412 <&imgsys CLK_IMG_GALS>; 413 clock-names = "isp", "isp-0", "isp-1"; 414 mediatek,infracfg = <&infracfg>; 415 #power-domain-cells = <0>; 416 }; 417 418 power-domain@MT8192_POWER_DOMAIN_ISP2 { 419 reg = <MT8192_POWER_DOMAIN_ISP2>; 420 clocks = <&topckgen CLK_TOP_IMG2_SEL>, 421 <&imgsys2 CLK_IMG2_LARB11>, 422 <&imgsys2 CLK_IMG2_GALS>; 423 clock-names = "isp2", "isp2-0", "isp2-1"; 424 mediatek,infracfg = <&infracfg>; 425 #power-domain-cells = <0>; 426 }; 427 428 power-domain@MT8192_POWER_DOMAIN_MDP { 429 reg = <MT8192_POWER_DOMAIN_MDP>; 430 clocks = <&topckgen CLK_TOP_MDP_SEL>, 431 <&mdpsys CLK_MDP_SMI0>; 432 clock-names = "mdp", "mdp-0"; 433 mediatek,infracfg = <&infracfg>; 434 #power-domain-cells = <0>; 435 }; 436 437 power-domain@MT8192_POWER_DOMAIN_VENC { 438 reg = <MT8192_POWER_DOMAIN_VENC>; 439 clocks = <&topckgen CLK_TOP_VENC_SEL>, 440 <&vencsys CLK_VENC_SET1_VENC>; 441 clock-names = "venc", "venc-0"; 442 mediatek,infracfg = <&infracfg>; 443 #power-domain-cells = <0>; 444 }; 445 446 power-domain@MT8192_POWER_DOMAIN_VDEC { 447 reg = <MT8192_POWER_DOMAIN_VDEC>; 448 clocks = <&topckgen CLK_TOP_VDEC_SEL>, 449 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 450 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 451 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 452 clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2"; 453 mediatek,infracfg = <&infracfg>; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 #power-domain-cells = <1>; 457 458 power-domain@MT8192_POWER_DOMAIN_VDEC2 { 459 reg = <MT8192_POWER_DOMAIN_VDEC2>; 460 clocks = <&vdecsys CLK_VDEC_VDEC>, 461 <&vdecsys CLK_VDEC_LAT>, 462 <&vdecsys CLK_VDEC_LARB1>; 463 clock-names = "vdec2-0", "vdec2-1", 464 "vdec2-2"; 465 #power-domain-cells = <0>; 466 }; 467 }; 468 469 power-domain@MT8192_POWER_DOMAIN_CAM { 470 reg = <MT8192_POWER_DOMAIN_CAM>; 471 clocks = <&topckgen CLK_TOP_CAM_SEL>, 472 <&camsys CLK_CAM_LARB13>, 473 <&camsys CLK_CAM_LARB14>, 474 <&camsys CLK_CAM_CCU_GALS>, 475 <&camsys CLK_CAM_CAM2MM_GALS>; 476 clock-names = "cam", "cam-0", "cam-1", "cam-2", 477 "cam-3"; 478 mediatek,infracfg = <&infracfg>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 #power-domain-cells = <1>; 482 483 power-domain@MT8192_POWER_DOMAIN_CAM_RAWA { 484 reg = <MT8192_POWER_DOMAIN_CAM_RAWA>; 485 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>; 486 clock-names = "cam_rawa-0"; 487 #power-domain-cells = <0>; 488 }; 489 490 power-domain@MT8192_POWER_DOMAIN_CAM_RAWB { 491 reg = <MT8192_POWER_DOMAIN_CAM_RAWB>; 492 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>; 493 clock-names = "cam_rawb-0"; 494 #power-domain-cells = <0>; 495 }; 496 497 power-domain@MT8192_POWER_DOMAIN_CAM_RAWC { 498 reg = <MT8192_POWER_DOMAIN_CAM_RAWC>; 499 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>; 500 clock-names = "cam_rawc-0"; 501 #power-domain-cells = <0>; 502 }; 503 }; 504 }; 505 }; 506 }; 507 508 watchdog: watchdog@10007000 { 509 compatible = "mediatek,mt8192-wdt"; 510 reg = <0 0x10007000 0 0x100>; 511 #reset-cells = <1>; 512 }; 513 514 apmixedsys: syscon@1000c000 { 515 compatible = "mediatek,mt8192-apmixedsys", "syscon"; 516 reg = <0 0x1000c000 0 0x1000>; 517 #clock-cells = <1>; 518 }; 519 520 systimer: timer@10017000 { 521 compatible = "mediatek,mt8192-timer", 522 "mediatek,mt6765-timer"; 523 reg = <0 0x10017000 0 0x1000>; 524 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; 525 clocks = <&topckgen CLK_TOP_CSW_F26M_D2>; 526 clock-names = "clk13m"; 527 }; 528 529 pwrap: pwrap@10026000 { 530 compatible = "mediatek,mt6873-pwrap"; 531 reg = <0 0x10026000 0 0x1000>; 532 reg-names = "pwrap"; 533 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; 534 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 535 <&infracfg CLK_INFRA_PMIC_TMR>; 536 clock-names = "spi", "wrap"; 537 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 538 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 539 }; 540 541 spmi: spmi@10027000 { 542 compatible = "mediatek,mt6873-spmi"; 543 reg = <0 0x10027000 0 0x000e00>, 544 <0 0x10029000 0 0x000100>; 545 reg-names = "pmif", "spmimst"; 546 clocks = <&infracfg CLK_INFRA_PMIC_AP>, 547 <&infracfg CLK_INFRA_PMIC_TMR>, 548 <&topckgen CLK_TOP_SPMI_MST_SEL>; 549 clock-names = "pmif_sys_ck", 550 "pmif_tmr_ck", 551 "spmimst_clk_mux"; 552 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; 553 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; 554 }; 555 556 scp_adsp: clock-controller@10720000 { 557 compatible = "mediatek,mt8192-scp_adsp"; 558 reg = <0 0x10720000 0 0x1000>; 559 #clock-cells = <1>; 560 }; 561 562 uart0: serial@11002000 { 563 compatible = "mediatek,mt8192-uart", 564 "mediatek,mt6577-uart"; 565 reg = <0 0x11002000 0 0x1000>; 566 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>; 567 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 568 clock-names = "baud", "bus"; 569 status = "disabled"; 570 }; 571 572 uart1: serial@11003000 { 573 compatible = "mediatek,mt8192-uart", 574 "mediatek,mt6577-uart"; 575 reg = <0 0x11003000 0 0x1000>; 576 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 577 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 578 clock-names = "baud", "bus"; 579 status = "disabled"; 580 }; 581 582 imp_iic_wrap_c: clock-controller@11007000 { 583 compatible = "mediatek,mt8192-imp_iic_wrap_c"; 584 reg = <0 0x11007000 0 0x1000>; 585 #clock-cells = <1>; 586 }; 587 588 spi0: spi@1100a000 { 589 compatible = "mediatek,mt8192-spi", 590 "mediatek,mt6765-spi"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 reg = <0 0x1100a000 0 0x1000>; 594 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>; 595 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 596 <&topckgen CLK_TOP_SPI_SEL>, 597 <&infracfg CLK_INFRA_SPI0>; 598 clock-names = "parent-clk", "sel-clk", "spi-clk"; 599 status = "disabled"; 600 }; 601 602 spi1: spi@11010000 { 603 compatible = "mediatek,mt8192-spi", 604 "mediatek,mt6765-spi"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 reg = <0 0x11010000 0 0x1000>; 608 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>; 609 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 610 <&topckgen CLK_TOP_SPI_SEL>, 611 <&infracfg CLK_INFRA_SPI1>; 612 clock-names = "parent-clk", "sel-clk", "spi-clk"; 613 status = "disabled"; 614 }; 615 616 spi2: spi@11012000 { 617 compatible = "mediatek,mt8192-spi", 618 "mediatek,mt6765-spi"; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 reg = <0 0x11012000 0 0x1000>; 622 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; 623 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 624 <&topckgen CLK_TOP_SPI_SEL>, 625 <&infracfg CLK_INFRA_SPI2>; 626 clock-names = "parent-clk", "sel-clk", "spi-clk"; 627 status = "disabled"; 628 }; 629 630 spi3: spi@11013000 { 631 compatible = "mediatek,mt8192-spi", 632 "mediatek,mt6765-spi"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 reg = <0 0x11013000 0 0x1000>; 636 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>; 637 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 638 <&topckgen CLK_TOP_SPI_SEL>, 639 <&infracfg CLK_INFRA_SPI3>; 640 clock-names = "parent-clk", "sel-clk", "spi-clk"; 641 status = "disabled"; 642 }; 643 644 spi4: spi@11018000 { 645 compatible = "mediatek,mt8192-spi", 646 "mediatek,mt6765-spi"; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 reg = <0 0x11018000 0 0x1000>; 650 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>; 651 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 652 <&topckgen CLK_TOP_SPI_SEL>, 653 <&infracfg CLK_INFRA_SPI4>; 654 clock-names = "parent-clk", "sel-clk", "spi-clk"; 655 status = "disabled"; 656 }; 657 658 spi5: spi@11019000 { 659 compatible = "mediatek,mt8192-spi", 660 "mediatek,mt6765-spi"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 reg = <0 0x11019000 0 0x1000>; 664 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>; 665 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 666 <&topckgen CLK_TOP_SPI_SEL>, 667 <&infracfg CLK_INFRA_SPI5>; 668 clock-names = "parent-clk", "sel-clk", "spi-clk"; 669 status = "disabled"; 670 }; 671 672 spi6: spi@1101d000 { 673 compatible = "mediatek,mt8192-spi", 674 "mediatek,mt6765-spi"; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 reg = <0 0x1101d000 0 0x1000>; 678 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>; 679 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 680 <&topckgen CLK_TOP_SPI_SEL>, 681 <&infracfg CLK_INFRA_SPI6>; 682 clock-names = "parent-clk", "sel-clk", "spi-clk"; 683 status = "disabled"; 684 }; 685 686 spi7: spi@1101e000 { 687 compatible = "mediatek,mt8192-spi", 688 "mediatek,mt6765-spi"; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 reg = <0 0x1101e000 0 0x1000>; 692 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>; 693 clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>, 694 <&topckgen CLK_TOP_SPI_SEL>, 695 <&infracfg CLK_INFRA_SPI7>; 696 clock-names = "parent-clk", "sel-clk", "spi-clk"; 697 status = "disabled"; 698 }; 699 700 scp: scp@10500000 { 701 compatible = "mediatek,mt8192-scp"; 702 reg = <0 0x10500000 0 0x100000>, 703 <0 0x10720000 0 0xe0000>, 704 <0 0x10700000 0 0x8000>; 705 reg-names = "sram", "cfg", "l1tcm"; 706 interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>; 707 clocks = <&infracfg CLK_INFRA_SCPSYS>; 708 clock-names = "main"; 709 status = "disabled"; 710 }; 711 712 xhci: usb@11200000 { 713 compatible = "mediatek,mt8192-xhci", 714 "mediatek,mtk-xhci"; 715 reg = <0 0x11200000 0 0x1000>, 716 <0 0x11203e00 0 0x0100>; 717 reg-names = "mac", "ippc"; 718 interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 719 interrupt-names = "host"; 720 phys = <&u2port0 PHY_TYPE_USB2>, 721 <&u3port0 PHY_TYPE_USB3>; 722 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, 723 <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; 724 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 725 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 726 clocks = <&infracfg CLK_INFRA_SSUSB>, 727 <&infracfg CLK_INFRA_SSUSB_XHCI>, 728 <&apmixedsys CLK_APMIXED_USBPLL>; 729 clock-names = "sys_ck", "xhci_ck", "ref_ck"; 730 wakeup-source; 731 mediatek,syscon-wakeup = <&pericfg 0x420 102>; 732 status = "disabled"; 733 }; 734 735 audsys: syscon@11210000 { 736 compatible = "mediatek,mt8192-audsys", "syscon"; 737 reg = <0 0x11210000 0 0x2000>; 738 #clock-cells = <1>; 739 740 afe: mt8192-afe-pcm { 741 compatible = "mediatek,mt8192-audio"; 742 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH 0>; 743 resets = <&watchdog 17>; 744 reset-names = "audiosys"; 745 mediatek,apmixedsys = <&apmixedsys>; 746 mediatek,infracfg = <&infracfg>; 747 mediatek,topckgen = <&topckgen>; 748 power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; 749 clocks = <&audsys CLK_AUD_AFE>, 750 <&audsys CLK_AUD_DAC>, 751 <&audsys CLK_AUD_DAC_PREDIS>, 752 <&audsys CLK_AUD_ADC>, 753 <&audsys CLK_AUD_ADDA6_ADC>, 754 <&audsys CLK_AUD_22M>, 755 <&audsys CLK_AUD_24M>, 756 <&audsys CLK_AUD_APLL_TUNER>, 757 <&audsys CLK_AUD_APLL2_TUNER>, 758 <&audsys CLK_AUD_TDM>, 759 <&audsys CLK_AUD_TML>, 760 <&audsys CLK_AUD_NLE>, 761 <&audsys CLK_AUD_DAC_HIRES>, 762 <&audsys CLK_AUD_ADC_HIRES>, 763 <&audsys CLK_AUD_ADC_HIRES_TML>, 764 <&audsys CLK_AUD_ADDA6_ADC_HIRES>, 765 <&audsys CLK_AUD_3RD_DAC>, 766 <&audsys CLK_AUD_3RD_DAC_PREDIS>, 767 <&audsys CLK_AUD_3RD_DAC_TML>, 768 <&audsys CLK_AUD_3RD_DAC_HIRES>, 769 <&infracfg CLK_INFRA_AUDIO>, 770 <&infracfg CLK_INFRA_AUDIO_26M_B>, 771 <&topckgen CLK_TOP_AUDIO_SEL>, 772 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 773 <&topckgen CLK_TOP_MAINPLL_D4_D4>, 774 <&topckgen CLK_TOP_AUD_1_SEL>, 775 <&topckgen CLK_TOP_APLL1>, 776 <&topckgen CLK_TOP_AUD_2_SEL>, 777 <&topckgen CLK_TOP_APLL2>, 778 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 779 <&topckgen CLK_TOP_APLL1_D4>, 780 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 781 <&topckgen CLK_TOP_APLL2_D4>, 782 <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, 783 <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, 784 <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, 785 <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, 786 <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, 787 <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, 788 <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, 789 <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, 790 <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, 791 <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, 792 <&topckgen CLK_TOP_APLL12_DIV0>, 793 <&topckgen CLK_TOP_APLL12_DIV1>, 794 <&topckgen CLK_TOP_APLL12_DIV2>, 795 <&topckgen CLK_TOP_APLL12_DIV3>, 796 <&topckgen CLK_TOP_APLL12_DIV4>, 797 <&topckgen CLK_TOP_APLL12_DIVB>, 798 <&topckgen CLK_TOP_APLL12_DIV5>, 799 <&topckgen CLK_TOP_APLL12_DIV6>, 800 <&topckgen CLK_TOP_APLL12_DIV7>, 801 <&topckgen CLK_TOP_APLL12_DIV8>, 802 <&topckgen CLK_TOP_APLL12_DIV9>, 803 <&topckgen CLK_TOP_AUDIO_H_SEL>, 804 <&clk26m>; 805 clock-names = "aud_afe_clk", 806 "aud_dac_clk", 807 "aud_dac_predis_clk", 808 "aud_adc_clk", 809 "aud_adda6_adc_clk", 810 "aud_apll22m_clk", 811 "aud_apll24m_clk", 812 "aud_apll1_tuner_clk", 813 "aud_apll2_tuner_clk", 814 "aud_tdm_clk", 815 "aud_tml_clk", 816 "aud_nle", 817 "aud_dac_hires_clk", 818 "aud_adc_hires_clk", 819 "aud_adc_hires_tml", 820 "aud_adda6_adc_hires_clk", 821 "aud_3rd_dac_clk", 822 "aud_3rd_dac_predis_clk", 823 "aud_3rd_dac_tml", 824 "aud_3rd_dac_hires_clk", 825 "aud_infra_clk", 826 "aud_infra_26m_clk", 827 "top_mux_audio", 828 "top_mux_audio_int", 829 "top_mainpll_d4_d4", 830 "top_mux_aud_1", 831 "top_apll1_ck", 832 "top_mux_aud_2", 833 "top_apll2_ck", 834 "top_mux_aud_eng1", 835 "top_apll1_d4", 836 "top_mux_aud_eng2", 837 "top_apll2_d4", 838 "top_i2s0_m_sel", 839 "top_i2s1_m_sel", 840 "top_i2s2_m_sel", 841 "top_i2s3_m_sel", 842 "top_i2s4_m_sel", 843 "top_i2s5_m_sel", 844 "top_i2s6_m_sel", 845 "top_i2s7_m_sel", 846 "top_i2s8_m_sel", 847 "top_i2s9_m_sel", 848 "top_apll12_div0", 849 "top_apll12_div1", 850 "top_apll12_div2", 851 "top_apll12_div3", 852 "top_apll12_div4", 853 "top_apll12_divb", 854 "top_apll12_div5", 855 "top_apll12_div6", 856 "top_apll12_div7", 857 "top_apll12_div8", 858 "top_apll12_div9", 859 "top_mux_audio_h", 860 "top_clk26m_clk"; 861 }; 862 }; 863 864 pcie: pcie@11230000 { 865 compatible = "mediatek,mt8192-pcie"; 866 device_type = "pci"; 867 reg = <0 0x11230000 0 0x2000>; 868 reg-names = "pcie-mac"; 869 #address-cells = <3>; 870 #size-cells = <2>; 871 clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, 872 <&infracfg CLK_INFRA_PCIE_TL_26M>, 873 <&infracfg CLK_INFRA_PCIE_TL_96M>, 874 <&infracfg CLK_INFRA_PCIE_TL_32K>, 875 <&infracfg CLK_INFRA_PCIE_PERI_26M>, 876 <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; 877 clock-names = "pl_250m", "tl_26m", "tl_96m", 878 "tl_32k", "peri_26m", "top_133m"; 879 assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; 880 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; 881 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>; 882 bus-range = <0x00 0xff>; 883 ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, 884 <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; 885 #interrupt-cells = <1>; 886 interrupt-map-mask = <0 0 0 7>; 887 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 888 <0 0 0 2 &pcie_intc0 1>, 889 <0 0 0 3 &pcie_intc0 2>, 890 <0 0 0 4 &pcie_intc0 3>; 891 892 pcie_intc0: interrupt-controller { 893 interrupt-controller; 894 #address-cells = <0>; 895 #interrupt-cells = <1>; 896 }; 897 }; 898 899 nor_flash: spi@11234000 { 900 compatible = "mediatek,mt8192-nor"; 901 reg = <0 0x11234000 0 0xe0>; 902 interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>; 903 clocks = <&topckgen CLK_TOP_SFLASH_SEL>, 904 <&infracfg CLK_INFRA_FLASHIF_SFLASH>, 905 <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>; 906 clock-names = "spi", "sf", "axi"; 907 assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>; 908 assigned-clock-parents = <&clk26m>; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 efuse: efuse@11c10000 { 915 compatible = "mediatek,mt8192-efuse", "mediatek,efuse"; 916 reg = <0 0x11c10000 0 0x1000>; 917 #address-cells = <1>; 918 #size-cells = <1>; 919 920 lvts_e_data1: data1@1c0 { 921 reg = <0x1c0 0x58>; 922 }; 923 924 svs_calibration: calib@580 { 925 reg = <0x580 0x68>; 926 }; 927 }; 928 929 i2c3: i2c@11cb0000 { 930 compatible = "mediatek,mt8192-i2c"; 931 reg = <0 0x11cb0000 0 0x1000>, 932 <0 0x10217300 0 0x80>; 933 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 934 clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>, 935 <&infracfg CLK_INFRA_AP_DMA>; 936 clock-names = "main", "dma"; 937 clock-div = <1>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 status = "disabled"; 941 }; 942 943 imp_iic_wrap_e: clock-controller@11cb1000 { 944 compatible = "mediatek,mt8192-imp_iic_wrap_e"; 945 reg = <0 0x11cb1000 0 0x1000>; 946 #clock-cells = <1>; 947 }; 948 949 i2c7: i2c@11d00000 { 950 compatible = "mediatek,mt8192-i2c"; 951 reg = <0 0x11d00000 0 0x1000>, 952 <0 0x10217600 0 0x180>; 953 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 954 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 955 <&infracfg CLK_INFRA_AP_DMA>; 956 clock-names = "main", "dma"; 957 clock-div = <1>; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 status = "disabled"; 961 }; 962 963 i2c8: i2c@11d01000 { 964 compatible = "mediatek,mt8192-i2c"; 965 reg = <0 0x11d01000 0 0x1000>, 966 <0 0x10217780 0 0x180>; 967 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 968 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>, 969 <&infracfg CLK_INFRA_AP_DMA>; 970 clock-names = "main", "dma"; 971 clock-div = <1>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 i2c9: i2c@11d02000 { 978 compatible = "mediatek,mt8192-i2c"; 979 reg = <0 0x11d02000 0 0x1000>, 980 <0 0x10217900 0 0x180>; 981 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>; 982 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>, 983 <&infracfg CLK_INFRA_AP_DMA>; 984 clock-names = "main", "dma"; 985 clock-div = <1>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 imp_iic_wrap_s: clock-controller@11d03000 { 992 compatible = "mediatek,mt8192-imp_iic_wrap_s"; 993 reg = <0 0x11d03000 0 0x1000>; 994 #clock-cells = <1>; 995 }; 996 997 i2c1: i2c@11d20000 { 998 compatible = "mediatek,mt8192-i2c"; 999 reg = <0 0x11d20000 0 0x1000>, 1000 <0 0x10217100 0 0x80>; 1001 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1002 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>, 1003 <&infracfg CLK_INFRA_AP_DMA>; 1004 clock-names = "main", "dma"; 1005 clock-div = <1>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 status = "disabled"; 1009 }; 1010 1011 i2c2: i2c@11d21000 { 1012 compatible = "mediatek,mt8192-i2c"; 1013 reg = <0 0x11d21000 0 0x1000>, 1014 <0 0x10217180 0 0x180>; 1015 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; 1016 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>, 1017 <&infracfg CLK_INFRA_AP_DMA>; 1018 clock-names = "main", "dma"; 1019 clock-div = <1>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 i2c4: i2c@11d22000 { 1026 compatible = "mediatek,mt8192-i2c"; 1027 reg = <0 0x11d22000 0 0x1000>, 1028 <0 0x10217380 0 0x180>; 1029 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1030 clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>, 1031 <&infracfg CLK_INFRA_AP_DMA>; 1032 clock-names = "main", "dma"; 1033 clock-div = <1>; 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 status = "disabled"; 1037 }; 1038 1039 imp_iic_wrap_ws: clock-controller@11d23000 { 1040 compatible = "mediatek,mt8192-imp_iic_wrap_ws"; 1041 reg = <0 0x11d23000 0 0x1000>; 1042 #clock-cells = <1>; 1043 }; 1044 1045 i2c5: i2c@11e00000 { 1046 compatible = "mediatek,mt8192-i2c"; 1047 reg = <0 0x11e00000 0 0x1000>, 1048 <0 0x10217500 0 0x80>; 1049 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1050 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>, 1051 <&infracfg CLK_INFRA_AP_DMA>; 1052 clock-names = "main", "dma"; 1053 clock-div = <1>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 imp_iic_wrap_w: clock-controller@11e01000 { 1060 compatible = "mediatek,mt8192-imp_iic_wrap_w"; 1061 reg = <0 0x11e01000 0 0x1000>; 1062 #clock-cells = <1>; 1063 }; 1064 1065 u3phy0: t-phy@11e40000 { 1066 compatible = "mediatek,mt8192-tphy", 1067 "mediatek,generic-tphy-v2"; 1068 #address-cells = <1>; 1069 #size-cells = <1>; 1070 ranges = <0x0 0x0 0x11e40000 0x1000>; 1071 1072 u2port0: usb-phy@0 { 1073 reg = <0x0 0x700>; 1074 clocks = <&clk26m>; 1075 clock-names = "ref"; 1076 #phy-cells = <1>; 1077 }; 1078 1079 u3port0: usb-phy@700 { 1080 reg = <0x700 0x900>; 1081 clocks = <&clk26m>; 1082 clock-names = "ref"; 1083 #phy-cells = <1>; 1084 }; 1085 }; 1086 1087 i2c0: i2c@11f00000 { 1088 compatible = "mediatek,mt8192-i2c"; 1089 reg = <0 0x11f00000 0 0x1000>, 1090 <0 0x10217080 0 0x80>; 1091 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>; 1092 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>, 1093 <&infracfg CLK_INFRA_AP_DMA>; 1094 clock-names = "main", "dma"; 1095 clock-div = <1>; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 i2c6: i2c@11f01000 { 1102 compatible = "mediatek,mt8192-i2c"; 1103 reg = <0 0x11f01000 0 0x1000>, 1104 <0 0x10217580 0 0x80>; 1105 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1106 clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>, 1107 <&infracfg CLK_INFRA_AP_DMA>; 1108 clock-names = "main", "dma"; 1109 clock-div = <1>; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 imp_iic_wrap_n: clock-controller@11f02000 { 1116 compatible = "mediatek,mt8192-imp_iic_wrap_n"; 1117 reg = <0 0x11f02000 0 0x1000>; 1118 #clock-cells = <1>; 1119 }; 1120 1121 msdc_top: clock-controller@11f10000 { 1122 compatible = "mediatek,mt8192-msdc_top"; 1123 reg = <0 0x11f10000 0 0x1000>; 1124 #clock-cells = <1>; 1125 }; 1126 1127 mmc0: mmc@11f60000 { 1128 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1129 reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; 1130 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 1131 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 1132 <&msdc_top CLK_MSDC_TOP_H_MST_0P>, 1133 <&msdc_top CLK_MSDC_TOP_SRC_0P>, 1134 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1135 <&msdc_top CLK_MSDC_TOP_P_MSDC0>, 1136 <&msdc_top CLK_MSDC_TOP_AXI>, 1137 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1138 clock-names = "source", "hclk", "source_cg", "sys_cg", 1139 "pclk_cg", "axi_cg", "ahb_cg"; 1140 status = "disabled"; 1141 }; 1142 1143 mmc1: mmc@11f70000 { 1144 compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; 1145 reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; 1146 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>; 1147 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 1148 <&msdc_top CLK_MSDC_TOP_H_MST_1P>, 1149 <&msdc_top CLK_MSDC_TOP_SRC_1P>, 1150 <&msdc_top CLK_MSDC_TOP_P_CFG>, 1151 <&msdc_top CLK_MSDC_TOP_P_MSDC1>, 1152 <&msdc_top CLK_MSDC_TOP_AXI>, 1153 <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; 1154 clock-names = "source", "hclk", "source_cg", "sys_cg", 1155 "pclk_cg", "axi_cg", "ahb_cg"; 1156 status = "disabled"; 1157 }; 1158 1159 mfgcfg: clock-controller@13fbf000 { 1160 compatible = "mediatek,mt8192-mfgcfg"; 1161 reg = <0 0x13fbf000 0 0x1000>; 1162 #clock-cells = <1>; 1163 }; 1164 1165 mmsys: syscon@14000000 { 1166 compatible = "mediatek,mt8192-mmsys", "syscon"; 1167 reg = <0 0x14000000 0 0x1000>; 1168 #clock-cells = <1>; 1169 }; 1170 1171 smi_common: smi@14002000 { 1172 compatible = "mediatek,mt8192-smi-common"; 1173 reg = <0 0x14002000 0 0x1000>; 1174 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1175 <&mmsys CLK_MM_SMI_INFRA>, 1176 <&mmsys CLK_MM_SMI_GALS>, 1177 <&mmsys CLK_MM_SMI_GALS>; 1178 clock-names = "apb", "smi", "gals0", "gals1"; 1179 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1180 }; 1181 1182 larb0: larb@14003000 { 1183 compatible = "mediatek,mt8192-smi-larb"; 1184 reg = <0 0x14003000 0 0x1000>; 1185 mediatek,larb-id = <0>; 1186 mediatek,smi = <&smi_common>; 1187 clocks = <&clk26m>, <&clk26m>; 1188 clock-names = "apb", "smi"; 1189 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1190 }; 1191 1192 larb1: larb@14004000 { 1193 compatible = "mediatek,mt8192-smi-larb"; 1194 reg = <0 0x14004000 0 0x1000>; 1195 mediatek,larb-id = <1>; 1196 mediatek,smi = <&smi_common>; 1197 clocks = <&clk26m>, <&clk26m>; 1198 clock-names = "apb", "smi"; 1199 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1200 }; 1201 1202 dpi0: dpi@14016000 { 1203 compatible = "mediatek,mt8192-dpi"; 1204 reg = <0 0x14016000 0 0x1000>; 1205 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>; 1206 clocks = <&mmsys CLK_MM_DPI_DPI0>, 1207 <&mmsys CLK_MM_DISP_DPI0>, 1208 <&apmixedsys CLK_APMIXED_TVDPLL>; 1209 clock-names = "pixel", "engine", "pll"; 1210 status = "disabled"; 1211 }; 1212 1213 iommu0: m4u@1401d000 { 1214 compatible = "mediatek,mt8192-m4u"; 1215 reg = <0 0x1401d000 0 0x1000>; 1216 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 1217 <&larb4>, <&larb5>, <&larb7>, 1218 <&larb9>, <&larb11>, <&larb13>, 1219 <&larb14>, <&larb16>, <&larb17>, 1220 <&larb18>, <&larb19>, <&larb20>; 1221 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; 1222 clocks = <&mmsys CLK_MM_SMI_IOMMU>; 1223 clock-names = "bclk"; 1224 power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; 1225 #iommu-cells = <1>; 1226 }; 1227 1228 imgsys: clock-controller@15020000 { 1229 compatible = "mediatek,mt8192-imgsys"; 1230 reg = <0 0x15020000 0 0x1000>; 1231 #clock-cells = <1>; 1232 }; 1233 1234 larb9: larb@1502e000 { 1235 compatible = "mediatek,mt8192-smi-larb"; 1236 reg = <0 0x1502e000 0 0x1000>; 1237 mediatek,larb-id = <9>; 1238 mediatek,smi = <&smi_common>; 1239 clocks = <&imgsys CLK_IMG_LARB9>, 1240 <&imgsys CLK_IMG_LARB9>; 1241 clock-names = "apb", "smi"; 1242 power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; 1243 }; 1244 1245 imgsys2: clock-controller@15820000 { 1246 compatible = "mediatek,mt8192-imgsys2"; 1247 reg = <0 0x15820000 0 0x1000>; 1248 #clock-cells = <1>; 1249 }; 1250 1251 larb11: larb@1582e000 { 1252 compatible = "mediatek,mt8192-smi-larb"; 1253 reg = <0 0x1582e000 0 0x1000>; 1254 mediatek,larb-id = <11>; 1255 mediatek,smi = <&smi_common>; 1256 clocks = <&imgsys2 CLK_IMG2_LARB11>, 1257 <&imgsys2 CLK_IMG2_LARB11>; 1258 clock-names = "apb", "smi"; 1259 power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; 1260 }; 1261 1262 larb5: larb@1600d000 { 1263 compatible = "mediatek,mt8192-smi-larb"; 1264 reg = <0 0x1600d000 0 0x1000>; 1265 mediatek,larb-id = <5>; 1266 mediatek,smi = <&smi_common>; 1267 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 1268 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 1269 clock-names = "apb", "smi"; 1270 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 1271 }; 1272 1273 vdecsys_soc: clock-controller@1600f000 { 1274 compatible = "mediatek,mt8192-vdecsys_soc"; 1275 reg = <0 0x1600f000 0 0x1000>; 1276 #clock-cells = <1>; 1277 }; 1278 1279 larb4: larb@1602e000 { 1280 compatible = "mediatek,mt8192-smi-larb"; 1281 reg = <0 0x1602e000 0 0x1000>; 1282 mediatek,larb-id = <4>; 1283 mediatek,smi = <&smi_common>; 1284 clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, 1285 <&vdecsys CLK_VDEC_SOC_LARB1>; 1286 clock-names = "apb", "smi"; 1287 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 1288 }; 1289 1290 vdecsys: clock-controller@1602f000 { 1291 compatible = "mediatek,mt8192-vdecsys"; 1292 reg = <0 0x1602f000 0 0x1000>; 1293 #clock-cells = <1>; 1294 }; 1295 1296 vencsys: clock-controller@17000000 { 1297 compatible = "mediatek,mt8192-vencsys"; 1298 reg = <0 0x17000000 0 0x1000>; 1299 #clock-cells = <1>; 1300 }; 1301 1302 larb7: larb@17010000 { 1303 compatible = "mediatek,mt8192-smi-larb"; 1304 reg = <0 0x17010000 0 0x1000>; 1305 mediatek,larb-id = <7>; 1306 mediatek,smi = <&smi_common>; 1307 clocks = <&vencsys CLK_VENC_SET0_LARB>, 1308 <&vencsys CLK_VENC_SET1_VENC>; 1309 clock-names = "apb", "smi"; 1310 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1311 }; 1312 1313 vcodec_enc: vcodec@17020000 { 1314 compatible = "mediatek,mt8192-vcodec-enc"; 1315 reg = <0 0x17020000 0 0x2000>; 1316 iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, 1317 <&iommu0 M4U_PORT_L7_VENC_REC>, 1318 <&iommu0 M4U_PORT_L7_VENC_BSDMA>, 1319 <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, 1320 <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, 1321 <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, 1322 <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, 1323 <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, 1324 <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, 1325 <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, 1326 <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; 1327 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH 0>; 1328 mediatek,scp = <&scp>; 1329 power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; 1330 clocks = <&vencsys CLK_VENC_SET1_VENC>; 1331 clock-names = "venc-set1"; 1332 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1333 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 1334 }; 1335 1336 camsys: clock-controller@1a000000 { 1337 compatible = "mediatek,mt8192-camsys"; 1338 reg = <0 0x1a000000 0 0x1000>; 1339 #clock-cells = <1>; 1340 }; 1341 1342 larb13: larb@1a001000 { 1343 compatible = "mediatek,mt8192-smi-larb"; 1344 reg = <0 0x1a001000 0 0x1000>; 1345 mediatek,larb-id = <13>; 1346 mediatek,smi = <&smi_common>; 1347 clocks = <&camsys CLK_CAM_CAM>, 1348 <&camsys CLK_CAM_LARB13>; 1349 clock-names = "apb", "smi"; 1350 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1351 }; 1352 1353 larb14: larb@1a002000 { 1354 compatible = "mediatek,mt8192-smi-larb"; 1355 reg = <0 0x1a002000 0 0x1000>; 1356 mediatek,larb-id = <14>; 1357 mediatek,smi = <&smi_common>; 1358 clocks = <&camsys CLK_CAM_CAM>, 1359 <&camsys CLK_CAM_LARB14>; 1360 clock-names = "apb", "smi"; 1361 power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; 1362 }; 1363 1364 larb16: larb@1a00f000 { 1365 compatible = "mediatek,mt8192-smi-larb"; 1366 reg = <0 0x1a00f000 0 0x1000>; 1367 mediatek,larb-id = <16>; 1368 mediatek,smi = <&smi_common>; 1369 clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, 1370 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 1371 clock-names = "apb", "smi"; 1372 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; 1373 }; 1374 1375 larb17: larb@1a010000 { 1376 compatible = "mediatek,mt8192-smi-larb"; 1377 reg = <0 0x1a010000 0 0x1000>; 1378 mediatek,larb-id = <17>; 1379 mediatek,smi = <&smi_common>; 1380 clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, 1381 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 1382 clock-names = "apb", "smi"; 1383 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; 1384 }; 1385 1386 larb18: larb@1a011000 { 1387 compatible = "mediatek,mt8192-smi-larb"; 1388 reg = <0 0x1a011000 0 0x1000>; 1389 mediatek,larb-id = <18>; 1390 mediatek,smi = <&smi_common>; 1391 clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, 1392 <&camsys_rawc CLK_CAM_RAWC_CAM>; 1393 clock-names = "apb", "smi"; 1394 power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; 1395 }; 1396 1397 camsys_rawa: clock-controller@1a04f000 { 1398 compatible = "mediatek,mt8192-camsys_rawa"; 1399 reg = <0 0x1a04f000 0 0x1000>; 1400 #clock-cells = <1>; 1401 }; 1402 1403 camsys_rawb: clock-controller@1a06f000 { 1404 compatible = "mediatek,mt8192-camsys_rawb"; 1405 reg = <0 0x1a06f000 0 0x1000>; 1406 #clock-cells = <1>; 1407 }; 1408 1409 camsys_rawc: clock-controller@1a08f000 { 1410 compatible = "mediatek,mt8192-camsys_rawc"; 1411 reg = <0 0x1a08f000 0 0x1000>; 1412 #clock-cells = <1>; 1413 }; 1414 1415 ipesys: clock-controller@1b000000 { 1416 compatible = "mediatek,mt8192-ipesys"; 1417 reg = <0 0x1b000000 0 0x1000>; 1418 #clock-cells = <1>; 1419 }; 1420 1421 larb20: larb@1b00f000 { 1422 compatible = "mediatek,mt8192-smi-larb"; 1423 reg = <0 0x1b00f000 0 0x1000>; 1424 mediatek,larb-id = <20>; 1425 mediatek,smi = <&smi_common>; 1426 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1427 <&ipesys CLK_IPE_LARB20>; 1428 clock-names = "apb", "smi"; 1429 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1430 }; 1431 1432 larb19: larb@1b10f000 { 1433 compatible = "mediatek,mt8192-smi-larb"; 1434 reg = <0 0x1b10f000 0 0x1000>; 1435 mediatek,larb-id = <19>; 1436 mediatek,smi = <&smi_common>; 1437 clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, 1438 <&ipesys CLK_IPE_LARB19>; 1439 clock-names = "apb", "smi"; 1440 power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; 1441 }; 1442 1443 mdpsys: clock-controller@1f000000 { 1444 compatible = "mediatek,mt8192-mdpsys"; 1445 reg = <0 0x1f000000 0 0x1000>; 1446 #clock-cells = <1>; 1447 }; 1448 1449 larb2: larb@1f002000 { 1450 compatible = "mediatek,mt8192-smi-larb"; 1451 reg = <0 0x1f002000 0 0x1000>; 1452 mediatek,larb-id = <2>; 1453 mediatek,smi = <&smi_common>; 1454 clocks = <&mdpsys CLK_MDP_SMI0>, 1455 <&mdpsys CLK_MDP_SMI0>; 1456 clock-names = "apb", "smi"; 1457 power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; 1458 }; 1459 }; 1460 };
Cache object: 2c67ae131642410866ffea44f26247f5
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