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sys/contrib/device-tree/src/arm64/nvidia/tegra234.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <dt-bindings/clock/tegra234-clock.h> 4 #include <dt-bindings/gpio/tegra234-gpio.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/mailbox/tegra186-hsp.h> 7 #include <dt-bindings/memory/tegra234-mc.h> 8 #include <dt-bindings/power/tegra234-powergate.h> 9 #include <dt-bindings/reset/tegra234-reset.h> 10 11 / { 12 compatible = "nvidia,tegra234"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 bus@0 { 18 compatible = "simple-bus"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 ranges = <0x0 0x0 0x0 0x40000000>; 23 24 gpcdma: dma-controller@2600000 { 25 compatible = "nvidia,tegra234-gpcdma", 26 "nvidia,tegra194-gpcdma", 27 "nvidia,tegra186-gpcdma"; 28 reg = <0x2600000 0x210000>; 29 resets = <&bpmp TEGRA234_RESET_GPCDMA>; 30 reset-names = "gpcdma"; 31 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 32 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 34 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 35 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 36 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 37 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 38 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 39 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 40 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 41 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 42 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 43 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 47 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 48 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 51 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 52 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 62 #dma-cells = <1>; 63 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; 64 dma-coherent; 65 }; 66 67 aconnect@2900000 { 68 compatible = "nvidia,tegra234-aconnect", 69 "nvidia,tegra210-aconnect"; 70 clocks = <&bpmp TEGRA234_CLK_APE>, 71 <&bpmp TEGRA234_CLK_APB2APE>; 72 clock-names = "ape", "apb2ape"; 73 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0x02900000 0x02900000 0x200000>; 77 status = "disabled"; 78 79 tegra_ahub: ahub@2900800 { 80 compatible = "nvidia,tegra234-ahub"; 81 reg = <0x02900800 0x800>; 82 clocks = <&bpmp TEGRA234_CLK_AHUB>; 83 clock-names = "ahub"; 84 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; 85 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 ranges = <0x02900800 0x02900800 0x11800>; 89 status = "disabled"; 90 91 tegra_i2s1: i2s@2901000 { 92 compatible = "nvidia,tegra234-i2s", 93 "nvidia,tegra210-i2s"; 94 reg = <0x2901000 0x100>; 95 clocks = <&bpmp TEGRA234_CLK_I2S1>, 96 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; 97 clock-names = "i2s", "sync_input"; 98 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>; 99 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 100 assigned-clock-rates = <1536000>; 101 sound-name-prefix = "I2S1"; 102 status = "disabled"; 103 }; 104 105 tegra_i2s2: i2s@2901100 { 106 compatible = "nvidia,tegra234-i2s", 107 "nvidia,tegra210-i2s"; 108 reg = <0x2901100 0x100>; 109 clocks = <&bpmp TEGRA234_CLK_I2S2>, 110 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; 111 clock-names = "i2s", "sync_input"; 112 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>; 113 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 114 assigned-clock-rates = <1536000>; 115 sound-name-prefix = "I2S2"; 116 status = "disabled"; 117 }; 118 119 tegra_i2s3: i2s@2901200 { 120 compatible = "nvidia,tegra234-i2s", 121 "nvidia,tegra210-i2s"; 122 reg = <0x2901200 0x100>; 123 clocks = <&bpmp TEGRA234_CLK_I2S3>, 124 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; 125 clock-names = "i2s", "sync_input"; 126 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>; 127 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 128 assigned-clock-rates = <1536000>; 129 sound-name-prefix = "I2S3"; 130 status = "disabled"; 131 }; 132 133 tegra_i2s4: i2s@2901300 { 134 compatible = "nvidia,tegra234-i2s", 135 "nvidia,tegra210-i2s"; 136 reg = <0x2901300 0x100>; 137 clocks = <&bpmp TEGRA234_CLK_I2S4>, 138 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; 139 clock-names = "i2s", "sync_input"; 140 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>; 141 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 142 assigned-clock-rates = <1536000>; 143 sound-name-prefix = "I2S4"; 144 status = "disabled"; 145 }; 146 147 tegra_i2s5: i2s@2901400 { 148 compatible = "nvidia,tegra234-i2s", 149 "nvidia,tegra210-i2s"; 150 reg = <0x2901400 0x100>; 151 clocks = <&bpmp TEGRA234_CLK_I2S5>, 152 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; 153 clock-names = "i2s", "sync_input"; 154 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>; 155 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 156 assigned-clock-rates = <1536000>; 157 sound-name-prefix = "I2S5"; 158 status = "disabled"; 159 }; 160 161 tegra_i2s6: i2s@2901500 { 162 compatible = "nvidia,tegra234-i2s", 163 "nvidia,tegra210-i2s"; 164 reg = <0x2901500 0x100>; 165 clocks = <&bpmp TEGRA234_CLK_I2S6>, 166 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; 167 clock-names = "i2s", "sync_input"; 168 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>; 169 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 170 assigned-clock-rates = <1536000>; 171 sound-name-prefix = "I2S6"; 172 status = "disabled"; 173 }; 174 175 tegra_sfc1: sfc@2902000 { 176 compatible = "nvidia,tegra234-sfc", 177 "nvidia,tegra210-sfc"; 178 reg = <0x2902000 0x200>; 179 sound-name-prefix = "SFC1"; 180 status = "disabled"; 181 }; 182 183 tegra_sfc2: sfc@2902200 { 184 compatible = "nvidia,tegra234-sfc", 185 "nvidia,tegra210-sfc"; 186 reg = <0x2902200 0x200>; 187 sound-name-prefix = "SFC2"; 188 status = "disabled"; 189 }; 190 191 tegra_sfc3: sfc@2902400 { 192 compatible = "nvidia,tegra234-sfc", 193 "nvidia,tegra210-sfc"; 194 reg = <0x2902400 0x200>; 195 sound-name-prefix = "SFC3"; 196 status = "disabled"; 197 }; 198 199 tegra_sfc4: sfc@2902600 { 200 compatible = "nvidia,tegra234-sfc", 201 "nvidia,tegra210-sfc"; 202 reg = <0x2902600 0x200>; 203 sound-name-prefix = "SFC4"; 204 status = "disabled"; 205 }; 206 207 tegra_amx1: amx@2903000 { 208 compatible = "nvidia,tegra234-amx", 209 "nvidia,tegra194-amx"; 210 reg = <0x2903000 0x100>; 211 sound-name-prefix = "AMX1"; 212 status = "disabled"; 213 }; 214 215 tegra_amx2: amx@2903100 { 216 compatible = "nvidia,tegra234-amx", 217 "nvidia,tegra194-amx"; 218 reg = <0x2903100 0x100>; 219 sound-name-prefix = "AMX2"; 220 status = "disabled"; 221 }; 222 223 tegra_amx3: amx@2903200 { 224 compatible = "nvidia,tegra234-amx", 225 "nvidia,tegra194-amx"; 226 reg = <0x2903200 0x100>; 227 sound-name-prefix = "AMX3"; 228 status = "disabled"; 229 }; 230 231 tegra_amx4: amx@2903300 { 232 compatible = "nvidia,tegra234-amx", 233 "nvidia,tegra194-amx"; 234 reg = <0x2903300 0x100>; 235 sound-name-prefix = "AMX4"; 236 status = "disabled"; 237 }; 238 239 tegra_adx1: adx@2903800 { 240 compatible = "nvidia,tegra234-adx", 241 "nvidia,tegra210-adx"; 242 reg = <0x2903800 0x100>; 243 sound-name-prefix = "ADX1"; 244 status = "disabled"; 245 }; 246 247 tegra_adx2: adx@2903900 { 248 compatible = "nvidia,tegra234-adx", 249 "nvidia,tegra210-adx"; 250 reg = <0x2903900 0x100>; 251 sound-name-prefix = "ADX2"; 252 status = "disabled"; 253 }; 254 255 tegra_adx3: adx@2903a00 { 256 compatible = "nvidia,tegra234-adx", 257 "nvidia,tegra210-adx"; 258 reg = <0x2903a00 0x100>; 259 sound-name-prefix = "ADX3"; 260 status = "disabled"; 261 }; 262 263 tegra_adx4: adx@2903b00 { 264 compatible = "nvidia,tegra234-adx", 265 "nvidia,tegra210-adx"; 266 reg = <0x2903b00 0x100>; 267 sound-name-prefix = "ADX4"; 268 status = "disabled"; 269 }; 270 271 272 tegra_dmic1: dmic@2904000 { 273 compatible = "nvidia,tegra234-dmic", 274 "nvidia,tegra210-dmic"; 275 reg = <0x2904000 0x100>; 276 clocks = <&bpmp TEGRA234_CLK_DMIC1>; 277 clock-names = "dmic"; 278 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; 279 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 280 assigned-clock-rates = <3072000>; 281 sound-name-prefix = "DMIC1"; 282 status = "disabled"; 283 }; 284 285 tegra_dmic2: dmic@2904100 { 286 compatible = "nvidia,tegra234-dmic", 287 "nvidia,tegra210-dmic"; 288 reg = <0x2904100 0x100>; 289 clocks = <&bpmp TEGRA234_CLK_DMIC2>; 290 clock-names = "dmic"; 291 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; 292 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 293 assigned-clock-rates = <3072000>; 294 sound-name-prefix = "DMIC2"; 295 status = "disabled"; 296 }; 297 298 tegra_dmic3: dmic@2904200 { 299 compatible = "nvidia,tegra234-dmic", 300 "nvidia,tegra210-dmic"; 301 reg = <0x2904200 0x100>; 302 clocks = <&bpmp TEGRA234_CLK_DMIC3>; 303 clock-names = "dmic"; 304 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; 305 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 306 assigned-clock-rates = <3072000>; 307 sound-name-prefix = "DMIC3"; 308 status = "disabled"; 309 }; 310 311 tegra_dmic4: dmic@2904300 { 312 compatible = "nvidia,tegra234-dmic", 313 "nvidia,tegra210-dmic"; 314 reg = <0x2904300 0x100>; 315 clocks = <&bpmp TEGRA234_CLK_DMIC4>; 316 clock-names = "dmic"; 317 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; 318 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 319 assigned-clock-rates = <3072000>; 320 sound-name-prefix = "DMIC4"; 321 status = "disabled"; 322 }; 323 324 tegra_dspk1: dspk@2905000 { 325 compatible = "nvidia,tegra234-dspk", 326 "nvidia,tegra186-dspk"; 327 reg = <0x2905000 0x100>; 328 clocks = <&bpmp TEGRA234_CLK_DSPK1>; 329 clock-names = "dspk"; 330 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; 331 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 332 assigned-clock-rates = <12288000>; 333 sound-name-prefix = "DSPK1"; 334 status = "disabled"; 335 }; 336 337 tegra_dspk2: dspk@2905100 { 338 compatible = "nvidia,tegra234-dspk", 339 "nvidia,tegra186-dspk"; 340 reg = <0x2905100 0x100>; 341 clocks = <&bpmp TEGRA234_CLK_DSPK2>; 342 clock-names = "dspk"; 343 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; 344 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; 345 assigned-clock-rates = <12288000>; 346 sound-name-prefix = "DSPK2"; 347 status = "disabled"; 348 }; 349 350 tegra_ope1: processing-engine@2908000 { 351 compatible = "nvidia,tegra234-ope", 352 "nvidia,tegra210-ope"; 353 reg = <0x2908000 0x100>; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges; 357 sound-name-prefix = "OPE1"; 358 status = "disabled"; 359 360 equalizer@2908100 { 361 compatible = "nvidia,tegra234-peq", 362 "nvidia,tegra210-peq"; 363 reg = <0x2908100 0x100>; 364 }; 365 366 dynamic-range-compressor@2908200 { 367 compatible = "nvidia,tegra234-mbdrc", 368 "nvidia,tegra210-mbdrc"; 369 reg = <0x2908200 0x200>; 370 }; 371 }; 372 373 tegra_mvc1: mvc@290a000 { 374 compatible = "nvidia,tegra234-mvc", 375 "nvidia,tegra210-mvc"; 376 reg = <0x290a000 0x200>; 377 sound-name-prefix = "MVC1"; 378 status = "disabled"; 379 }; 380 381 tegra_mvc2: mvc@290a200 { 382 compatible = "nvidia,tegra234-mvc", 383 "nvidia,tegra210-mvc"; 384 reg = <0x290a200 0x200>; 385 sound-name-prefix = "MVC2"; 386 status = "disabled"; 387 }; 388 389 tegra_amixer: amixer@290bb00 { 390 compatible = "nvidia,tegra234-amixer", 391 "nvidia,tegra210-amixer"; 392 reg = <0x290bb00 0x800>; 393 sound-name-prefix = "MIXER1"; 394 status = "disabled"; 395 }; 396 397 tegra_admaif: admaif@290f000 { 398 compatible = "nvidia,tegra234-admaif", 399 "nvidia,tegra186-admaif"; 400 reg = <0x0290f000 0x1000>; 401 dmas = <&adma 1>, <&adma 1>, 402 <&adma 2>, <&adma 2>, 403 <&adma 3>, <&adma 3>, 404 <&adma 4>, <&adma 4>, 405 <&adma 5>, <&adma 5>, 406 <&adma 6>, <&adma 6>, 407 <&adma 7>, <&adma 7>, 408 <&adma 8>, <&adma 8>, 409 <&adma 9>, <&adma 9>, 410 <&adma 10>, <&adma 10>, 411 <&adma 11>, <&adma 11>, 412 <&adma 12>, <&adma 12>, 413 <&adma 13>, <&adma 13>, 414 <&adma 14>, <&adma 14>, 415 <&adma 15>, <&adma 15>, 416 <&adma 16>, <&adma 16>, 417 <&adma 17>, <&adma 17>, 418 <&adma 18>, <&adma 18>, 419 <&adma 19>, <&adma 19>, 420 <&adma 20>, <&adma 20>; 421 dma-names = "rx1", "tx1", 422 "rx2", "tx2", 423 "rx3", "tx3", 424 "rx4", "tx4", 425 "rx5", "tx5", 426 "rx6", "tx6", 427 "rx7", "tx7", 428 "rx8", "tx8", 429 "rx9", "tx9", 430 "rx10", "tx10", 431 "rx11", "tx11", 432 "rx12", "tx12", 433 "rx13", "tx13", 434 "rx14", "tx14", 435 "rx15", "tx15", 436 "rx16", "tx16", 437 "rx17", "tx17", 438 "rx18", "tx18", 439 "rx19", "tx19", 440 "rx20", "tx20"; 441 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>, 442 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>; 443 interconnect-names = "dma-mem", "write"; 444 iommus = <&smmu_niso0 TEGRA234_SID_APE>; 445 status = "disabled"; 446 }; 447 448 tegra_asrc: asrc@2910000 { 449 compatible = "nvidia,tegra234-asrc", 450 "nvidia,tegra186-asrc"; 451 reg = <0x2910000 0x2000>; 452 sound-name-prefix = "ASRC1"; 453 status = "disabled"; 454 }; 455 }; 456 457 adma: dma-controller@2930000 { 458 compatible = "nvidia,tegra234-adma", 459 "nvidia,tegra186-adma"; 460 reg = <0x02930000 0x20000>; 461 interrupt-parent = <&agic>; 462 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 494 #dma-cells = <1>; 495 clocks = <&bpmp TEGRA234_CLK_AHUB>; 496 clock-names = "d_audio"; 497 status = "disabled"; 498 }; 499 500 agic: interrupt-controller@2a40000 { 501 compatible = "nvidia,tegra234-agic", 502 "nvidia,tegra210-agic"; 503 #interrupt-cells = <3>; 504 interrupt-controller; 505 reg = <0x02a41000 0x1000>, 506 <0x02a42000 0x2000>; 507 interrupts = <GIC_SPI 145 508 (GIC_CPU_MASK_SIMPLE(4) | 509 IRQ_TYPE_LEVEL_HIGH)>; 510 clocks = <&bpmp TEGRA234_CLK_APE>; 511 clock-names = "clk"; 512 status = "disabled"; 513 }; 514 }; 515 516 misc@100000 { 517 compatible = "nvidia,tegra234-misc"; 518 reg = <0x00100000 0xf000>, 519 <0x0010f000 0x1000>; 520 status = "okay"; 521 }; 522 523 timer@2080000 { 524 compatible = "nvidia,tegra234-timer"; 525 reg = <0x02080000 0x00121000>; 526 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 542 status = "okay"; 543 }; 544 545 host1x@13e00000 { 546 compatible = "nvidia,tegra234-host1x"; 547 reg = <0x13e00000 0x10000>, 548 <0x13e10000 0x10000>, 549 <0x13e40000 0x10000>; 550 reg-names = "common", "hypervisor", "vm"; 551 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4", 561 "syncpt5", "syncpt6", "syncpt7", "host1x"; 562 clocks = <&bpmp TEGRA234_CLK_HOST1X>; 563 clock-names = "host1x"; 564 565 #address-cells = <1>; 566 #size-cells = <1>; 567 568 ranges = <0x15000000 0x15000000 0x01000000>; 569 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>; 570 interconnect-names = "dma-mem"; 571 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>; 572 573 vic@15340000 { 574 compatible = "nvidia,tegra234-vic"; 575 reg = <0x15340000 0x00040000>; 576 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&bpmp TEGRA234_CLK_VIC>; 578 clock-names = "vic"; 579 resets = <&bpmp TEGRA234_RESET_VIC>; 580 reset-names = "vic"; 581 582 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>; 583 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>, 584 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>; 585 interconnect-names = "dma-mem", "write"; 586 iommus = <&smmu_niso1 TEGRA234_SID_VIC>; 587 dma-coherent; 588 }; 589 }; 590 591 gpio: gpio@2200000 { 592 compatible = "nvidia,tegra234-gpio"; 593 reg-names = "security", "gpio"; 594 reg = <0x02200000 0x10000>, 595 <0x02210000 0x10000>; 596 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 644 #interrupt-cells = <2>; 645 interrupt-controller; 646 #gpio-cells = <2>; 647 gpio-controller; 648 }; 649 650 mc: memory-controller@2c00000 { 651 compatible = "nvidia,tegra234-mc"; 652 reg = <0x02c00000 0x10000>, /* MC-SID */ 653 <0x02c10000 0x10000>, /* MC Broadcast*/ 654 <0x02c20000 0x10000>, /* MC0 */ 655 <0x02c30000 0x10000>, /* MC1 */ 656 <0x02c40000 0x10000>, /* MC2 */ 657 <0x02c50000 0x10000>, /* MC3 */ 658 <0x02b80000 0x10000>, /* MC4 */ 659 <0x02b90000 0x10000>, /* MC5 */ 660 <0x02ba0000 0x10000>, /* MC6 */ 661 <0x02bb0000 0x10000>, /* MC7 */ 662 <0x01700000 0x10000>, /* MC8 */ 663 <0x01710000 0x10000>, /* MC9 */ 664 <0x01720000 0x10000>, /* MC10 */ 665 <0x01730000 0x10000>, /* MC11 */ 666 <0x01740000 0x10000>, /* MC12 */ 667 <0x01750000 0x10000>, /* MC13 */ 668 <0x01760000 0x10000>, /* MC14 */ 669 <0x01770000 0x10000>; /* MC15 */ 670 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", 671 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", 672 "ch11", "ch12", "ch13", "ch14", "ch15"; 673 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 674 #interconnect-cells = <1>; 675 status = "okay"; 676 677 #address-cells = <2>; 678 #size-cells = <2>; 679 680 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, 681 <0x02b80000 0x0 0x02b80000 0x0 0x040000>, 682 <0x02c00000 0x0 0x02c00000 0x0 0x100000>; 683 684 /* 685 * Bit 39 of addresses passing through the memory 686 * controller selects the XBAR format used when memory 687 * is accessed. This is used to transparently access 688 * memory in the XBAR format used by the discrete GPU 689 * (bit 39 set) or Tegra (bit 39 clear). 690 * 691 * As a consequence, the operating system must ensure 692 * that bit 39 is never used implicitly, for example 693 * via an I/O virtual address mapping of an IOMMU. If 694 * devices require access to the XBAR switch, their 695 * drivers must set this bit explicitly. 696 * 697 * Limit the DMA range for memory clients to [38:0]. 698 */ 699 dma-ranges = <0x0 0x0 0x0 0x80 0x0>; 700 701 emc: external-memory-controller@2c60000 { 702 compatible = "nvidia,tegra234-emc"; 703 reg = <0x0 0x02c60000 0x0 0x90000>, 704 <0x0 0x01780000 0x0 0x80000>; 705 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&bpmp TEGRA234_CLK_EMC>; 707 clock-names = "emc"; 708 status = "okay"; 709 710 #interconnect-cells = <0>; 711 712 nvidia,bpmp = <&bpmp>; 713 }; 714 }; 715 716 uarta: serial@3100000 { 717 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; 718 reg = <0x03100000 0x10000>; 719 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&bpmp TEGRA234_CLK_UARTA>; 721 clock-names = "serial"; 722 resets = <&bpmp TEGRA234_RESET_UARTA>; 723 reset-names = "serial"; 724 status = "disabled"; 725 }; 726 727 gen1_i2c: i2c@3160000 { 728 compatible = "nvidia,tegra194-i2c"; 729 reg = <0x3160000 0x100>; 730 status = "disabled"; 731 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 732 clock-frequency = <400000>; 733 clocks = <&bpmp TEGRA234_CLK_I2C1 734 &bpmp TEGRA234_CLK_PLLP_OUT0>; 735 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>; 736 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 737 clock-names = "div-clk", "parent"; 738 resets = <&bpmp TEGRA234_RESET_I2C1>; 739 reset-names = "i2c"; 740 }; 741 742 cam_i2c: i2c@3180000 { 743 compatible = "nvidia,tegra194-i2c"; 744 reg = <0x3180000 0x100>; 745 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 746 status = "disabled"; 747 clock-frequency = <400000>; 748 clocks = <&bpmp TEGRA234_CLK_I2C3 749 &bpmp TEGRA234_CLK_PLLP_OUT0>; 750 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>; 751 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 752 clock-names = "div-clk", "parent"; 753 resets = <&bpmp TEGRA234_RESET_I2C3>; 754 reset-names = "i2c"; 755 }; 756 757 dp_aux_ch1_i2c: i2c@3190000 { 758 compatible = "nvidia,tegra194-i2c"; 759 reg = <0x3190000 0x100>; 760 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 761 status = "disabled"; 762 clock-frequency = <100000>; 763 clocks = <&bpmp TEGRA234_CLK_I2C4 764 &bpmp TEGRA234_CLK_PLLP_OUT0>; 765 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>; 766 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 767 clock-names = "div-clk", "parent"; 768 resets = <&bpmp TEGRA234_RESET_I2C4>; 769 reset-names = "i2c"; 770 }; 771 772 dp_aux_ch0_i2c: i2c@31b0000 { 773 compatible = "nvidia,tegra194-i2c"; 774 reg = <0x31b0000 0x100>; 775 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 776 status = "disabled"; 777 clock-frequency = <100000>; 778 clocks = <&bpmp TEGRA234_CLK_I2C6 779 &bpmp TEGRA234_CLK_PLLP_OUT0>; 780 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>; 781 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 782 clock-names = "div-clk", "parent"; 783 resets = <&bpmp TEGRA234_RESET_I2C6>; 784 reset-names = "i2c"; 785 }; 786 787 dp_aux_ch2_i2c: i2c@31c0000 { 788 compatible = "nvidia,tegra194-i2c"; 789 reg = <0x31c0000 0x100>; 790 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 791 status = "disabled"; 792 clock-frequency = <100000>; 793 clocks = <&bpmp TEGRA234_CLK_I2C7 794 &bpmp TEGRA234_CLK_PLLP_OUT0>; 795 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>; 796 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 797 clock-names = "div-clk", "parent"; 798 resets = <&bpmp TEGRA234_RESET_I2C7>; 799 reset-names = "i2c"; 800 }; 801 802 dp_aux_ch3_i2c: i2c@31e0000 { 803 compatible = "nvidia,tegra194-i2c"; 804 reg = <0x31e0000 0x100>; 805 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 806 status = "disabled"; 807 clock-frequency = <100000>; 808 clocks = <&bpmp TEGRA234_CLK_I2C9 809 &bpmp TEGRA234_CLK_PLLP_OUT0>; 810 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>; 811 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 812 clock-names = "div-clk", "parent"; 813 resets = <&bpmp TEGRA234_RESET_I2C9>; 814 reset-names = "i2c"; 815 }; 816 817 spi@3270000 { 818 compatible = "nvidia,tegra234-qspi"; 819 reg = <0x3270000 0x1000>; 820 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, 824 <&bpmp TEGRA234_CLK_QSPI0_PM>; 825 clock-names = "qspi", "qspi_out"; 826 resets = <&bpmp TEGRA234_RESET_QSPI0>; 827 reset-names = "qspi"; 828 status = "disabled"; 829 }; 830 831 pwm1: pwm@3280000 { 832 compatible = "nvidia,tegra194-pwm", 833 "nvidia,tegra186-pwm"; 834 reg = <0x3280000 0x10000>; 835 clocks = <&bpmp TEGRA234_CLK_PWM1>; 836 clock-names = "pwm"; 837 resets = <&bpmp TEGRA234_RESET_PWM1>; 838 reset-names = "pwm"; 839 status = "disabled"; 840 #pwm-cells = <2>; 841 }; 842 843 spi@3300000 { 844 compatible = "nvidia,tegra234-qspi"; 845 reg = <0x3300000 0x1000>; 846 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, 850 <&bpmp TEGRA234_CLK_QSPI1_PM>; 851 clock-names = "qspi", "qspi_out"; 852 resets = <&bpmp TEGRA234_RESET_QSPI1>; 853 reset-names = "qspi"; 854 status = "disabled"; 855 }; 856 857 mmc@3460000 { 858 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; 859 reg = <0x03460000 0x20000>; 860 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 862 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>; 863 clock-names = "sdhci", "tmclk"; 864 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>, 865 <&bpmp TEGRA234_CLK_PLLC4>; 866 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>; 867 resets = <&bpmp TEGRA234_RESET_SDMMC4>; 868 reset-names = "sdhci"; 869 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>, 870 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>; 871 interconnect-names = "dma-mem", "write"; 872 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>; 873 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>; 874 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>; 875 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>; 876 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>; 877 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>; 878 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>; 879 nvidia,default-tap = <0x8>; 880 nvidia,default-trim = <0x14>; 881 nvidia,dqs-trim = <40>; 882 supports-cqe; 883 status = "disabled"; 884 }; 885 886 hda@3510000 { 887 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda"; 888 reg = <0x3510000 0x10000>; 889 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 890 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>, 891 <&bpmp TEGRA234_CLK_AZA_2XBIT>; 892 clock-names = "hda", "hda2codec_2x"; 893 resets = <&bpmp TEGRA234_RESET_HDA>, 894 <&bpmp TEGRA234_RESET_HDACODEC>; 895 reset-names = "hda", "hda2codec_2x"; 896 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; 897 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>, 898 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>; 899 interconnect-names = "dma-mem", "write"; 900 status = "disabled"; 901 }; 902 903 fuse@3810000 { 904 compatible = "nvidia,tegra234-efuse"; 905 reg = <0x03810000 0x10000>; 906 clocks = <&bpmp TEGRA234_CLK_FUSE>; 907 clock-names = "fuse"; 908 }; 909 910 hsp_top0: hsp@3c00000 { 911 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 912 reg = <0x03c00000 0xa0000>; 913 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 922 interrupt-names = "doorbell", "shared0", "shared1", "shared2", 923 "shared3", "shared4", "shared5", "shared6", 924 "shared7"; 925 #mbox-cells = <2>; 926 }; 927 928 smmu_niso1: iommu@8000000 { 929 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 930 reg = <0x8000000 0x1000000>, 931 <0x7000000 0x1000000>; 932 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1008 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1062 stream-match-mask = <0x7f80>; 1063 #global-interrupts = <2>; 1064 #iommu-cells = <1>; 1065 1066 nvidia,memory-controller = <&mc>; 1067 status = "okay"; 1068 }; 1069 1070 sce-fabric@b600000 { 1071 compatible = "nvidia,tegra234-sce-fabric"; 1072 reg = <0xb600000 0x40000>; 1073 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1074 status = "okay"; 1075 }; 1076 1077 rce-fabric@be00000 { 1078 compatible = "nvidia,tegra234-rce-fabric"; 1079 reg = <0xbe00000 0x40000>; 1080 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1081 status = "okay"; 1082 }; 1083 1084 hsp_aon: hsp@c150000 { 1085 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; 1086 reg = <0x0c150000 0x90000>; 1087 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1091 /* 1092 * Shared interrupt 0 is routed only to AON/SPE, so 1093 * we only have 4 shared interrupts for the CCPLEX. 1094 */ 1095 interrupt-names = "shared1", "shared2", "shared3", "shared4"; 1096 #mbox-cells = <2>; 1097 }; 1098 1099 gen2_i2c: i2c@c240000 { 1100 compatible = "nvidia,tegra194-i2c"; 1101 reg = <0xc240000 0x100>; 1102 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1103 status = "disabled"; 1104 clock-frequency = <100000>; 1105 clocks = <&bpmp TEGRA234_CLK_I2C2 1106 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1107 clock-names = "div-clk", "parent"; 1108 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>; 1109 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1110 resets = <&bpmp TEGRA234_RESET_I2C2>; 1111 reset-names = "i2c"; 1112 }; 1113 1114 gen8_i2c: i2c@c250000 { 1115 compatible = "nvidia,tegra194-i2c"; 1116 reg = <0xc250000 0x100>; 1117 nvidia,hw-instance-id = <0x7>; 1118 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1119 status = "disabled"; 1120 clock-frequency = <400000>; 1121 clocks = <&bpmp TEGRA234_CLK_I2C8 1122 &bpmp TEGRA234_CLK_PLLP_OUT0>; 1123 clock-names = "div-clk", "parent"; 1124 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>; 1125 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; 1126 resets = <&bpmp TEGRA234_RESET_I2C8>; 1127 reset-names = "i2c"; 1128 }; 1129 1130 rtc@c2a0000 { 1131 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; 1132 reg = <0x0c2a0000 0x10000>; 1133 interrupt-parent = <&pmc>; 1134 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 1135 clocks = <&bpmp TEGRA234_CLK_CLK_32K>; 1136 clock-names = "rtc"; 1137 status = "disabled"; 1138 }; 1139 1140 gpio_aon: gpio@c2f0000 { 1141 compatible = "nvidia,tegra234-gpio-aon"; 1142 reg-names = "security", "gpio"; 1143 reg = <0x0c2f0000 0x1000>, 1144 <0x0c2f1000 0x1000>; 1145 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1146 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1147 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 1149 #interrupt-cells = <2>; 1150 interrupt-controller; 1151 #gpio-cells = <2>; 1152 gpio-controller; 1153 }; 1154 1155 pmc: pmc@c360000 { 1156 compatible = "nvidia,tegra234-pmc"; 1157 reg = <0x0c360000 0x10000>, 1158 <0x0c370000 0x10000>, 1159 <0x0c380000 0x10000>, 1160 <0x0c390000 0x10000>, 1161 <0x0c3a0000 0x10000>; 1162 reg-names = "pmc", "wake", "aotag", "scratch", "misc"; 1163 1164 #interrupt-cells = <2>; 1165 interrupt-controller; 1166 }; 1167 1168 aon-fabric@c600000 { 1169 compatible = "nvidia,tegra234-aon-fabric"; 1170 reg = <0xc600000 0x40000>; 1171 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1172 status = "okay"; 1173 }; 1174 1175 bpmp-fabric@d600000 { 1176 compatible = "nvidia,tegra234-bpmp-fabric"; 1177 reg = <0xd600000 0x40000>; 1178 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1179 status = "okay"; 1180 }; 1181 1182 dce-fabric@de00000 { 1183 compatible = "nvidia,tegra234-sce-fabric"; 1184 reg = <0xde00000 0x40000>; 1185 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>; 1186 status = "okay"; 1187 }; 1188 1189 gic: interrupt-controller@f400000 { 1190 compatible = "arm,gic-v3"; 1191 reg = <0x0f400000 0x010000>, /* GICD */ 1192 <0x0f440000 0x200000>; /* GICR */ 1193 interrupt-parent = <&gic>; 1194 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1195 1196 #redistributor-regions = <1>; 1197 #interrupt-cells = <3>; 1198 interrupt-controller; 1199 }; 1200 1201 smmu_iso: iommu@10000000{ 1202 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1203 reg = <0x10000000 0x1000000>; 1204 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1261 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1262 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1287 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1288 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1316 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1317 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1318 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1319 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1320 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1321 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1322 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1323 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1324 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1326 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1327 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1328 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1329 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1333 stream-match-mask = <0x7f80>; 1334 #global-interrupts = <1>; 1335 #iommu-cells = <1>; 1336 1337 nvidia,memory-controller = <&mc>; 1338 status = "okay"; 1339 }; 1340 1341 smmu_niso0: iommu@12000000 { 1342 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500"; 1343 reg = <0x12000000 0x1000000>, 1344 <0x11000000 0x1000000>; 1345 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 1475 stream-match-mask = <0x7f80>; 1476 #global-interrupts = <2>; 1477 #iommu-cells = <1>; 1478 1479 nvidia,memory-controller = <&mc>; 1480 status = "okay"; 1481 }; 1482 1483 cbb-fabric@13a00000 { 1484 compatible = "nvidia,tegra234-cbb-fabric"; 1485 reg = <0x13a00000 0x400000>; 1486 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1487 status = "okay"; 1488 }; 1489 }; 1490 1491 ccplex@e000000 { 1492 compatible = "nvidia,tegra234-ccplex-cluster"; 1493 reg = <0x0 0x0e000000 0x0 0x5ffff>; 1494 nvidia,bpmp = <&bpmp>; 1495 status = "okay"; 1496 }; 1497 1498 sram@40000000 { 1499 compatible = "nvidia,tegra234-sysram", "mmio-sram"; 1500 reg = <0x0 0x40000000 0x0 0x80000>; 1501 #address-cells = <1>; 1502 #size-cells = <1>; 1503 ranges = <0x0 0x0 0x40000000 0x80000>; 1504 no-memory-wc; 1505 1506 cpu_bpmp_tx: sram@70000 { 1507 reg = <0x70000 0x1000>; 1508 label = "cpu-bpmp-tx"; 1509 pool; 1510 }; 1511 1512 cpu_bpmp_rx: sram@71000 { 1513 reg = <0x71000 0x1000>; 1514 label = "cpu-bpmp-rx"; 1515 pool; 1516 }; 1517 }; 1518 1519 bpmp: bpmp { 1520 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; 1521 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB 1522 TEGRA_HSP_DB_MASTER_BPMP>; 1523 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; 1524 #clock-cells = <1>; 1525 #reset-cells = <1>; 1526 #power-domain-cells = <1>; 1527 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>, 1528 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>, 1529 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>, 1530 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>; 1531 interconnect-names = "read", "write", "dma-mem", "dma-write"; 1532 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>; 1533 1534 bpmp_i2c: i2c { 1535 compatible = "nvidia,tegra186-bpmp-i2c"; 1536 nvidia,bpmp-bus-id = <5>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 }; 1540 }; 1541 1542 cpus { 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 1546 cpu0_0: cpu@0 { 1547 compatible = "arm,cortex-a78"; 1548 device_type = "cpu"; 1549 reg = <0x00000>; 1550 1551 enable-method = "psci"; 1552 1553 i-cache-size = <65536>; 1554 i-cache-line-size = <64>; 1555 i-cache-sets = <256>; 1556 d-cache-size = <65536>; 1557 d-cache-line-size = <64>; 1558 d-cache-sets = <256>; 1559 next-level-cache = <&l2c0_0>; 1560 }; 1561 1562 cpu0_1: cpu@100 { 1563 compatible = "arm,cortex-a78"; 1564 device_type = "cpu"; 1565 reg = <0x00100>; 1566 1567 enable-method = "psci"; 1568 1569 i-cache-size = <65536>; 1570 i-cache-line-size = <64>; 1571 i-cache-sets = <256>; 1572 d-cache-size = <65536>; 1573 d-cache-line-size = <64>; 1574 d-cache-sets = <256>; 1575 next-level-cache = <&l2c0_1>; 1576 }; 1577 1578 cpu0_2: cpu@200 { 1579 compatible = "arm,cortex-a78"; 1580 device_type = "cpu"; 1581 reg = <0x00200>; 1582 1583 enable-method = "psci"; 1584 1585 i-cache-size = <65536>; 1586 i-cache-line-size = <64>; 1587 i-cache-sets = <256>; 1588 d-cache-size = <65536>; 1589 d-cache-line-size = <64>; 1590 d-cache-sets = <256>; 1591 next-level-cache = <&l2c0_2>; 1592 }; 1593 1594 cpu0_3: cpu@300 { 1595 compatible = "arm,cortex-a78"; 1596 device_type = "cpu"; 1597 reg = <0x00300>; 1598 1599 enable-method = "psci"; 1600 1601 i-cache-size = <65536>; 1602 i-cache-line-size = <64>; 1603 i-cache-sets = <256>; 1604 d-cache-size = <65536>; 1605 d-cache-line-size = <64>; 1606 d-cache-sets = <256>; 1607 next-level-cache = <&l2c0_3>; 1608 }; 1609 1610 cpu1_0: cpu@10000 { 1611 compatible = "arm,cortex-a78"; 1612 device_type = "cpu"; 1613 reg = <0x10000>; 1614 1615 enable-method = "psci"; 1616 1617 i-cache-size = <65536>; 1618 i-cache-line-size = <64>; 1619 i-cache-sets = <256>; 1620 d-cache-size = <65536>; 1621 d-cache-line-size = <64>; 1622 d-cache-sets = <256>; 1623 next-level-cache = <&l2c1_0>; 1624 }; 1625 1626 cpu1_1: cpu@10100 { 1627 compatible = "arm,cortex-a78"; 1628 device_type = "cpu"; 1629 reg = <0x10100>; 1630 1631 enable-method = "psci"; 1632 1633 i-cache-size = <65536>; 1634 i-cache-line-size = <64>; 1635 i-cache-sets = <256>; 1636 d-cache-size = <65536>; 1637 d-cache-line-size = <64>; 1638 d-cache-sets = <256>; 1639 next-level-cache = <&l2c1_1>; 1640 }; 1641 1642 cpu1_2: cpu@10200 { 1643 compatible = "arm,cortex-a78"; 1644 device_type = "cpu"; 1645 reg = <0x10200>; 1646 1647 enable-method = "psci"; 1648 1649 i-cache-size = <65536>; 1650 i-cache-line-size = <64>; 1651 i-cache-sets = <256>; 1652 d-cache-size = <65536>; 1653 d-cache-line-size = <64>; 1654 d-cache-sets = <256>; 1655 next-level-cache = <&l2c1_2>; 1656 }; 1657 1658 cpu1_3: cpu@10300 { 1659 compatible = "arm,cortex-a78"; 1660 device_type = "cpu"; 1661 reg = <0x10300>; 1662 1663 enable-method = "psci"; 1664 1665 i-cache-size = <65536>; 1666 i-cache-line-size = <64>; 1667 i-cache-sets = <256>; 1668 d-cache-size = <65536>; 1669 d-cache-line-size = <64>; 1670 d-cache-sets = <256>; 1671 next-level-cache = <&l2c1_3>; 1672 }; 1673 1674 cpu2_0: cpu@20000 { 1675 compatible = "arm,cortex-a78"; 1676 device_type = "cpu"; 1677 reg = <0x20000>; 1678 1679 enable-method = "psci"; 1680 1681 i-cache-size = <65536>; 1682 i-cache-line-size = <64>; 1683 i-cache-sets = <256>; 1684 d-cache-size = <65536>; 1685 d-cache-line-size = <64>; 1686 d-cache-sets = <256>; 1687 next-level-cache = <&l2c2_0>; 1688 }; 1689 1690 cpu2_1: cpu@20100 { 1691 compatible = "arm,cortex-a78"; 1692 device_type = "cpu"; 1693 reg = <0x20100>; 1694 1695 enable-method = "psci"; 1696 1697 i-cache-size = <65536>; 1698 i-cache-line-size = <64>; 1699 i-cache-sets = <256>; 1700 d-cache-size = <65536>; 1701 d-cache-line-size = <64>; 1702 d-cache-sets = <256>; 1703 next-level-cache = <&l2c2_1>; 1704 }; 1705 1706 cpu2_2: cpu@20200 { 1707 compatible = "arm,cortex-a78"; 1708 device_type = "cpu"; 1709 reg = <0x20200>; 1710 1711 enable-method = "psci"; 1712 1713 i-cache-size = <65536>; 1714 i-cache-line-size = <64>; 1715 i-cache-sets = <256>; 1716 d-cache-size = <65536>; 1717 d-cache-line-size = <64>; 1718 d-cache-sets = <256>; 1719 next-level-cache = <&l2c2_2>; 1720 }; 1721 1722 cpu2_3: cpu@20300 { 1723 compatible = "arm,cortex-a78"; 1724 device_type = "cpu"; 1725 reg = <0x20300>; 1726 1727 enable-method = "psci"; 1728 1729 i-cache-size = <65536>; 1730 i-cache-line-size = <64>; 1731 i-cache-sets = <256>; 1732 d-cache-size = <65536>; 1733 d-cache-line-size = <64>; 1734 d-cache-sets = <256>; 1735 next-level-cache = <&l2c2_3>; 1736 }; 1737 1738 cpu-map { 1739 cluster0 { 1740 core0 { 1741 cpu = <&cpu0_0>; 1742 }; 1743 1744 core1 { 1745 cpu = <&cpu0_1>; 1746 }; 1747 1748 core2 { 1749 cpu = <&cpu0_2>; 1750 }; 1751 1752 core3 { 1753 cpu = <&cpu0_3>; 1754 }; 1755 }; 1756 1757 cluster1 { 1758 core0 { 1759 cpu = <&cpu1_0>; 1760 }; 1761 1762 core1 { 1763 cpu = <&cpu1_1>; 1764 }; 1765 1766 core2 { 1767 cpu = <&cpu1_2>; 1768 }; 1769 1770 core3 { 1771 cpu = <&cpu1_3>; 1772 }; 1773 }; 1774 1775 cluster2 { 1776 core0 { 1777 cpu = <&cpu2_0>; 1778 }; 1779 1780 core1 { 1781 cpu = <&cpu2_1>; 1782 }; 1783 1784 core2 { 1785 cpu = <&cpu2_2>; 1786 }; 1787 1788 core3 { 1789 cpu = <&cpu2_3>; 1790 }; 1791 }; 1792 }; 1793 1794 l2c0_0: l2-cache00 { 1795 cache-size = <262144>; 1796 cache-line-size = <64>; 1797 cache-sets = <512>; 1798 cache-unified; 1799 next-level-cache = <&l3c0>; 1800 }; 1801 1802 l2c0_1: l2-cache01 { 1803 cache-size = <262144>; 1804 cache-line-size = <64>; 1805 cache-sets = <512>; 1806 cache-unified; 1807 next-level-cache = <&l3c0>; 1808 }; 1809 1810 l2c0_2: l2-cache02 { 1811 cache-size = <262144>; 1812 cache-line-size = <64>; 1813 cache-sets = <512>; 1814 cache-unified; 1815 next-level-cache = <&l3c0>; 1816 }; 1817 1818 l2c0_3: l2-cache03 { 1819 cache-size = <262144>; 1820 cache-line-size = <64>; 1821 cache-sets = <512>; 1822 cache-unified; 1823 next-level-cache = <&l3c0>; 1824 }; 1825 1826 l2c1_0: l2-cache10 { 1827 cache-size = <262144>; 1828 cache-line-size = <64>; 1829 cache-sets = <512>; 1830 cache-unified; 1831 next-level-cache = <&l3c1>; 1832 }; 1833 1834 l2c1_1: l2-cache11 { 1835 cache-size = <262144>; 1836 cache-line-size = <64>; 1837 cache-sets = <512>; 1838 cache-unified; 1839 next-level-cache = <&l3c1>; 1840 }; 1841 1842 l2c1_2: l2-cache12 { 1843 cache-size = <262144>; 1844 cache-line-size = <64>; 1845 cache-sets = <512>; 1846 cache-unified; 1847 next-level-cache = <&l3c1>; 1848 }; 1849 1850 l2c1_3: l2-cache13 { 1851 cache-size = <262144>; 1852 cache-line-size = <64>; 1853 cache-sets = <512>; 1854 cache-unified; 1855 next-level-cache = <&l3c1>; 1856 }; 1857 1858 l2c2_0: l2-cache20 { 1859 cache-size = <262144>; 1860 cache-line-size = <64>; 1861 cache-sets = <512>; 1862 cache-unified; 1863 next-level-cache = <&l3c2>; 1864 }; 1865 1866 l2c2_1: l2-cache21 { 1867 cache-size = <262144>; 1868 cache-line-size = <64>; 1869 cache-sets = <512>; 1870 cache-unified; 1871 next-level-cache = <&l3c2>; 1872 }; 1873 1874 l2c2_2: l2-cache22 { 1875 cache-size = <262144>; 1876 cache-line-size = <64>; 1877 cache-sets = <512>; 1878 cache-unified; 1879 next-level-cache = <&l3c2>; 1880 }; 1881 1882 l2c2_3: l2-cache23 { 1883 cache-size = <262144>; 1884 cache-line-size = <64>; 1885 cache-sets = <512>; 1886 cache-unified; 1887 next-level-cache = <&l3c2>; 1888 }; 1889 1890 l3c0: l3-cache0 { 1891 cache-size = <2097152>; 1892 cache-line-size = <64>; 1893 cache-sets = <2048>; 1894 }; 1895 1896 l3c1: l3-cache1 { 1897 cache-size = <2097152>; 1898 cache-line-size = <64>; 1899 cache-sets = <2048>; 1900 }; 1901 1902 l3c2: l3-cache2 { 1903 cache-size = <2097152>; 1904 cache-line-size = <64>; 1905 cache-sets = <2048>; 1906 }; 1907 }; 1908 1909 pmu { 1910 compatible = "arm,cortex-a78-pmu"; 1911 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 1912 status = "okay"; 1913 }; 1914 1915 psci { 1916 compatible = "arm,psci-1.0"; 1917 status = "okay"; 1918 method = "smc"; 1919 }; 1920 1921 tcu: serial { 1922 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu"; 1923 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>, 1924 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>; 1925 mbox-names = "rx", "tx"; 1926 status = "disabled"; 1927 }; 1928 1929 sound { 1930 status = "disabled"; 1931 1932 clocks = <&bpmp TEGRA234_CLK_PLLA>, 1933 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1934 clock-names = "pll_a", "plla_out0"; 1935 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>, 1936 <&bpmp TEGRA234_CLK_PLLA_OUT0>, 1937 <&bpmp TEGRA234_CLK_AUD_MCLK>; 1938 assigned-clock-parents = <0>, 1939 <&bpmp TEGRA234_CLK_PLLA>, 1940 <&bpmp TEGRA234_CLK_PLLA_OUT0>; 1941 }; 1942 1943 timer { 1944 compatible = "arm,armv8-timer"; 1945 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1946 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1947 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1948 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1949 interrupt-parent = <&gic>; 1950 always-on; 1951 }; 1952 };
Cache object: 1ce80d1247b3a84b8227e5d0227da130
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