ipq6018.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
    2 /*
    3  * IPQ6018 SoC device tree source
    4  *
    5  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
    6  */
    7 
    8 #include <dt-bindings/interrupt-controller/arm-gic.h>
    9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
   10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
   11 #include <dt-bindings/clock/qcom,apss-ipq.h>
   12 
   13 / {
   14         #address-cells = <2>;
   15         #size-cells = <2>;
   16         interrupt-parent = <&intc>;
   17 
   18         clocks {
   19                 sleep_clk: sleep-clk {
   20                         compatible = "fixed-clock";
   21                         clock-frequency = <32000>;
   22                         #clock-cells = <0>;
   23                 };
   24 
   25                 xo: xo {
   26                         compatible = "fixed-clock";
   27                         clock-frequency = <24000000>;
   28                         #clock-cells = <0>;
   29                 };
   30         };
   31 
   32         cpus: cpus {
   33                 #address-cells = <1>;
   34                 #size-cells = <0>;
   35 
   36                 CPU0: cpu@0 {
   37                         device_type = "cpu";
   38                         compatible = "arm,cortex-a53";
   39                         reg = <0x0>;
   40                         enable-method = "psci";
   41                         next-level-cache = <&L2_0>;
   42                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
   43                         clock-names = "cpu";
   44                         operating-points-v2 = <&cpu_opp_table>;
   45                         cpu-supply = <&ipq6018_s2>;
   46                 };
   47 
   48                 CPU1: cpu@1 {
   49                         device_type = "cpu";
   50                         compatible = "arm,cortex-a53";
   51                         enable-method = "psci";
   52                         reg = <0x1>;
   53                         next-level-cache = <&L2_0>;
   54                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
   55                         clock-names = "cpu";
   56                         operating-points-v2 = <&cpu_opp_table>;
   57                         cpu-supply = <&ipq6018_s2>;
   58                 };
   59 
   60                 CPU2: cpu@2 {
   61                         device_type = "cpu";
   62                         compatible = "arm,cortex-a53";
   63                         enable-method = "psci";
   64                         reg = <0x2>;
   65                         next-level-cache = <&L2_0>;
   66                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
   67                         clock-names = "cpu";
   68                         operating-points-v2 = <&cpu_opp_table>;
   69                         cpu-supply = <&ipq6018_s2>;
   70                 };
   71 
   72                 CPU3: cpu@3 {
   73                         device_type = "cpu";
   74                         compatible = "arm,cortex-a53";
   75                         enable-method = "psci";
   76                         reg = <0x3>;
   77                         next-level-cache = <&L2_0>;
   78                         clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
   79                         clock-names = "cpu";
   80                         operating-points-v2 = <&cpu_opp_table>;
   81                         cpu-supply = <&ipq6018_s2>;
   82                 };
   83 
   84                 L2_0: l2-cache {
   85                         compatible = "cache";
   86                         cache-level = <0x2>;
   87                 };
   88         };
   89 
   90         cpu_opp_table: opp-table-cpu {
   91                 compatible = "operating-points-v2";
   92                 opp-shared;
   93 
   94                 opp-864000000 {
   95                         opp-hz = /bits/ 64 <864000000>;
   96                         opp-microvolt = <725000>;
   97                         clock-latency-ns = <200000>;
   98                 };
   99                 opp-1056000000 {
  100                         opp-hz = /bits/ 64 <1056000000>;
  101                         opp-microvolt = <787500>;
  102                         clock-latency-ns = <200000>;
  103                 };
  104                 opp-1320000000 {
  105                         opp-hz = /bits/ 64 <1320000000>;
  106                         opp-microvolt = <862500>;
  107                         clock-latency-ns = <200000>;
  108                 };
  109                 opp-1440000000 {
  110                         opp-hz = /bits/ 64 <1440000000>;
  111                         opp-microvolt = <925000>;
  112                         clock-latency-ns = <200000>;
  113                 };
  114                 opp-1608000000 {
  115                         opp-hz = /bits/ 64 <1608000000>;
  116                         opp-microvolt = <987500>;
  117                         clock-latency-ns = <200000>;
  118                 };
  119                 opp-1800000000 {
  120                         opp-hz = /bits/ 64 <1800000000>;
  121                         opp-microvolt = <1062500>;
  122                         clock-latency-ns = <200000>;
  123                 };
  124         };
  125 
  126         firmware {
  127                 scm {
  128                         compatible = "qcom,scm-ipq6018", "qcom,scm";
  129                 };
  130         };
  131 
  132         tcsr_mutex: hwlock {
  133                 compatible = "qcom,tcsr-mutex";
  134                 syscon = <&tcsr_mutex_regs 0 0x80>;
  135                 #hwlock-cells = <1>;
  136         };
  137 
  138         pmuv8: pmu {
  139                 compatible = "arm,cortex-a53-pmu";
  140                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
  141                                          IRQ_TYPE_LEVEL_HIGH)>;
  142         };
  143 
  144         psci: psci {
  145                 compatible = "arm,psci-1.0";
  146                 method = "smc";
  147         };
  148 
  149         reserved-memory {
  150                 #address-cells = <2>;
  151                 #size-cells = <2>;
  152                 ranges;
  153 
  154                 rpm_msg_ram: memory@60000 {
  155                         reg = <0x0 0x60000 0x0 0x6000>;
  156                         no-map;
  157                 };
  158 
  159                 tz: memory@4a600000 {
  160                         reg = <0x0 0x4a600000 0x0 0x00400000>;
  161                         no-map;
  162                 };
  163 
  164                 smem_region: memory@4aa00000 {
  165                         reg = <0x0 0x4aa00000 0x0 0x00100000>;
  166                         no-map;
  167                 };
  168 
  169                 q6_region: memory@4ab00000 {
  170                         reg = <0x0 0x4ab00000 0x0 0x05500000>;
  171                         no-map;
  172                 };
  173         };
  174 
  175         smem {
  176                 compatible = "qcom,smem";
  177                 memory-region = <&smem_region>;
  178                 hwlocks = <&tcsr_mutex 0>;
  179         };
  180 
  181         soc: soc {
  182                 #address-cells = <2>;
  183                 #size-cells = <2>;
  184                 ranges = <0 0 0 0 0x0 0xffffffff>;
  185                 dma-ranges;
  186                 compatible = "simple-bus";
  187 
  188                 prng: qrng@e1000 {
  189                         compatible = "qcom,prng-ee";
  190                         reg = <0x0 0xe3000 0x0 0x1000>;
  191                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  192                         clock-names = "core";
  193                 };
  194 
  195                 cryptobam: dma-controller@704000 {
  196                         compatible = "qcom,bam-v1.7.0";
  197                         reg = <0x0 0x00704000 0x0 0x20000>;
  198                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
  199                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
  200                         clock-names = "bam_clk";
  201                         #dma-cells = <1>;
  202                         qcom,ee = <1>;
  203                         qcom,controlled-remotely;
  204                 };
  205 
  206                 crypto: crypto@73a000 {
  207                         compatible = "qcom,crypto-v5.1";
  208                         reg = <0x0 0x0073a000 0x0 0x6000>;
  209                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
  210                                 <&gcc GCC_CRYPTO_AXI_CLK>,
  211                                 <&gcc GCC_CRYPTO_CLK>;
  212                         clock-names = "iface", "bus", "core";
  213                         dmas = <&cryptobam 2>, <&cryptobam 3>;
  214                         dma-names = "rx", "tx";
  215                 };
  216 
  217                 tlmm: pinctrl@1000000 {
  218                         compatible = "qcom,ipq6018-pinctrl";
  219                         reg = <0x0 0x01000000 0x0 0x300000>;
  220                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  221                         gpio-controller;
  222                         #gpio-cells = <2>;
  223                         gpio-ranges = <&tlmm 0 0 80>;
  224                         interrupt-controller;
  225                         #interrupt-cells = <2>;
  226 
  227                         serial_3_pins: serial3-pinmux {
  228                                 pins = "gpio44", "gpio45";
  229                                 function = "blsp2_uart";
  230                                 drive-strength = <8>;
  231                                 bias-pull-down;
  232                         };
  233 
  234                         qpic_pins: qpic-pins {
  235                                 pins = "gpio1", "gpio3", "gpio4",
  236                                         "gpio5", "gpio6", "gpio7",
  237                                         "gpio8", "gpio10", "gpio11",
  238                                         "gpio12", "gpio13", "gpio14",
  239                                         "gpio15", "gpio17";
  240                                 function = "qpic_pad";
  241                                 drive-strength = <8>;
  242                                 bias-disable;
  243                         };
  244                 };
  245 
  246                 gcc: gcc@1800000 {
  247                         compatible = "qcom,gcc-ipq6018";
  248                         reg = <0x0 0x01800000 0x0 0x80000>;
  249                         clocks = <&xo>, <&sleep_clk>;
  250                         clock-names = "xo", "sleep_clk";
  251                         #clock-cells = <1>;
  252                         #reset-cells = <1>;
  253                 };
  254 
  255                 tcsr_mutex_regs: syscon@1905000 {
  256                         compatible = "syscon";
  257                         reg = <0x0 0x01905000 0x0 0x8000>;
  258                 };
  259 
  260                 tcsr: syscon@1937000 {
  261                         compatible = "syscon";
  262                         reg = <0x0 0x01937000 0x0 0x21000>;
  263                 };
  264 
  265                 blsp_dma: dma-controller@7884000 {
  266                         compatible = "qcom,bam-v1.7.0";
  267                         reg = <0x0 0x07884000 0x0 0x2b000>;
  268                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
  269                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
  270                         clock-names = "bam_clk";
  271                         #dma-cells = <1>;
  272                         qcom,ee = <0>;
  273                 };
  274 
  275                 blsp1_uart3: serial@78b1000 {
  276                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  277                         reg = <0x0 0x078b1000 0x0 0x200>;
  278                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
  279                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
  280                                 <&gcc GCC_BLSP1_AHB_CLK>;
  281                         clock-names = "core", "iface";
  282                         status = "disabled";
  283                 };
  284 
  285                 blsp1_spi1: spi@78b5000 {
  286                         compatible = "qcom,spi-qup-v2.2.1";
  287                         #address-cells = <1>;
  288                         #size-cells = <0>;
  289                         reg = <0x0 0x078b5000 0x0 0x600>;
  290                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  291                         spi-max-frequency = <50000000>;
  292                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
  293                                 <&gcc GCC_BLSP1_AHB_CLK>;
  294                         clock-names = "core", "iface";
  295                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
  296                         dma-names = "tx", "rx";
  297                         status = "disabled";
  298                 };
  299 
  300                 blsp1_spi2: spi@78b6000 {
  301                         compatible = "qcom,spi-qup-v2.2.1";
  302                         #address-cells = <1>;
  303                         #size-cells = <0>;
  304                         reg = <0x0 0x078b6000 0x0 0x600>;
  305                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  306                         spi-max-frequency = <50000000>;
  307                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
  308                                 <&gcc GCC_BLSP1_AHB_CLK>;
  309                         clock-names = "core", "iface";
  310                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
  311                         dma-names = "tx", "rx";
  312                         status = "disabled";
  313                 };
  314 
  315                 blsp1_i2c2: i2c@78b6000 {
  316                         compatible = "qcom,i2c-qup-v2.2.1";
  317                         #address-cells = <1>;
  318                         #size-cells = <0>;
  319                         reg = <0x0 0x078b6000 0x0 0x600>;
  320                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  321                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
  322                                  <&gcc GCC_BLSP1_AHB_CLK>;
  323                         clock-names = "core", "iface";
  324                         clock-frequency = <400000>;
  325                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
  326                         dma-names = "tx", "rx";
  327                         status = "disabled";
  328                 };
  329 
  330                 blsp1_i2c3: i2c@78b7000 {
  331                         compatible = "qcom,i2c-qup-v2.2.1";
  332                         #address-cells = <1>;
  333                         #size-cells = <0>;
  334                         reg = <0x0 0x078b7000 0x0 0x600>;
  335                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  336                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
  337                                  <&gcc GCC_BLSP1_AHB_CLK>;
  338                         clock-names = "core", "iface";
  339                         clock-frequency = <400000>;
  340                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
  341                         dma-names = "tx", "rx";
  342                         status = "disabled";
  343                 };
  344 
  345                 qpic_bam: dma-controller@7984000 {
  346                         compatible = "qcom,bam-v1.7.0";
  347                         reg = <0x0 0x07984000 0x0 0x1a000>;
  348                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  349                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
  350                         clock-names = "bam_clk";
  351                         #dma-cells = <1>;
  352                         qcom,ee = <0>;
  353                         status = "disabled";
  354                 };
  355 
  356                 qpic_nand: nand@79b0000 {
  357                         compatible = "qcom,ipq6018-nand";
  358                         reg = <0x0 0x079b0000 0x0 0x10000>;
  359                         #address-cells = <1>;
  360                         #size-cells = <0>;
  361                         clocks = <&gcc GCC_QPIC_CLK>,
  362                                  <&gcc GCC_QPIC_AHB_CLK>;
  363                         clock-names = "core", "aon";
  364 
  365                         dmas = <&qpic_bam 0>,
  366                                 <&qpic_bam 1>,
  367                                 <&qpic_bam 2>;
  368                         dma-names = "tx", "rx", "cmd";
  369                         pinctrl-0 = <&qpic_pins>;
  370                         pinctrl-names = "default";
  371                         status = "disabled";
  372                 };
  373 
  374                 intc: interrupt-controller@b000000 {
  375                         compatible = "qcom,msm-qgic2";
  376                         #address-cells = <2>;
  377                         #size-cells = <2>;
  378                         interrupt-controller;
  379                         #interrupt-cells = <0x3>;
  380                         reg =   <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
  381                                 <0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
  382                                 <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
  383                                 <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
  384                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  385                         ranges = <0 0 0 0xb00a000 0 0xffd>;
  386 
  387                         v2m@0 {
  388                                 compatible = "arm,gic-v2m-frame";
  389                                 msi-controller;
  390                                 reg = <0x0 0x0 0x0 0xffd>;
  391                         };
  392                 };
  393 
  394                 pcie_phy: phy@84000 {
  395                         compatible = "qcom,ipq6018-qmp-pcie-phy";
  396                         reg = <0x0 0x84000 0x0 0x1bc>; /* Serdes PLL */
  397                         status = "disabled";
  398                         #address-cells = <2>;
  399                         #size-cells = <2>;
  400                         ranges;
  401 
  402                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
  403                                 <&gcc GCC_PCIE0_AHB_CLK>;
  404                         clock-names = "aux", "cfg_ahb";
  405 
  406                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
  407                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
  408                         reset-names = "phy",
  409                                       "common";
  410 
  411                         pcie_phy0: phy@84200 {
  412                                 reg = <0x0 0x84200 0x0 0x16c>, /* Serdes Tx */
  413                                       <0x0 0x84400 0x0 0x200>, /* Serdes Rx */
  414                                       <0x0 0x84800 0x0 0x4f4>; /* PCS: Lane0, COM, PCIE */
  415                                 #phy-cells = <0>;
  416 
  417                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  418                                 clock-names = "pipe0";
  419                                 clock-output-names = "gcc_pcie0_pipe_clk_src";
  420                                 #clock-cells = <0>;
  421                         };
  422                 };
  423 
  424                 pcie0: pci@20000000 {
  425                         compatible = "qcom,pcie-ipq6018";
  426                         reg = <0x0 0x20000000 0x0 0xf1d>,
  427                               <0x0 0x20000f20 0x0 0xa8>,
  428                               <0x0 0x20001000 0x0 0x1000>,
  429                               <0x0 0x80000 0x0 0x4000>,
  430                               <0x0 0x20100000 0x0 0x1000>;
  431                         reg-names = "dbi", "elbi", "atu", "parf", "config";
  432 
  433                         device_type = "pci";
  434                         linux,pci-domain = <0>;
  435                         bus-range = <0x00 0xff>;
  436                         num-lanes = <1>;
  437                         max-link-speed = <3>;
  438                         #address-cells = <3>;
  439                         #size-cells = <2>;
  440 
  441                         phys = <&pcie_phy0>;
  442                         phy-names = "pciephy";
  443 
  444                         ranges = <0x81000000 0 0x20200000 0 0x20200000
  445                                   0 0x10000>, /* downstream I/O */
  446                                  <0x82000000 0 0x20220000 0 0x20220000
  447                                   0 0xfde0000>; /* non-prefetchable memory */
  448 
  449                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  450                         interrupt-names = "msi";
  451 
  452                         #interrupt-cells = <1>;
  453                         interrupt-map-mask = <0 0 0 0x7>;
  454                         interrupt-map = <0 0 0 1 &intc 0 75
  455                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  456                                         <0 0 0 2 &intc 0 78
  457                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  458                                         <0 0 0 3 &intc 0 79
  459                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  460                                         <0 0 0 4 &intc 0 83
  461                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  462 
  463                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
  464                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
  465                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
  466                                  <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
  467                                  <&gcc PCIE0_RCHNG_CLK>;
  468                         clock-names = "iface",
  469                                       "axi_m",
  470                                       "axi_s",
  471                                       "axi_bridge",
  472                                       "rchng";
  473 
  474                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
  475                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
  476                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
  477                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
  478                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
  479                                  <&gcc GCC_PCIE0_AHB_ARES>,
  480                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
  481                                  <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
  482                         reset-names = "pipe",
  483                                       "sleep",
  484                                       "sticky",
  485                                       "axi_m",
  486                                       "axi_s",
  487                                       "ahb",
  488                                       "axi_m_sticky",
  489                                       "axi_s_sticky";
  490 
  491                         status = "disabled";
  492                 };
  493 
  494                 watchdog@b017000 {
  495                         compatible = "qcom,kpss-wdt";
  496                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  497                         reg = <0x0 0x0b017000 0x0 0x40>;
  498                         clocks = <&sleep_clk>;
  499                         timeout-sec = <10>;
  500                 };
  501 
  502                 apcs_glb: mailbox@b111000 {
  503                         compatible = "qcom,ipq6018-apcs-apps-global";
  504                         reg = <0x0 0x0b111000 0x0 0x1000>;
  505                         #clock-cells = <1>;
  506                         clocks = <&a53pll>, <&xo>;
  507                         clock-names = "pll", "xo";
  508                         #mbox-cells = <1>;
  509                 };
  510 
  511                 a53pll: clock@b116000 {
  512                         compatible = "qcom,ipq6018-a53pll";
  513                         reg = <0x0 0x0b116000 0x0 0x40>;
  514                         #clock-cells = <0>;
  515                         clocks = <&xo>;
  516                         clock-names = "xo";
  517                 };
  518 
  519                 timer {
  520                         compatible = "arm,armv8-timer";
  521                         interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  522                                      <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  523                                      <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  524                                      <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  525                 };
  526 
  527                 timer@b120000 {
  528                         #address-cells = <1>;
  529                         #size-cells = <1>;
  530                         ranges = <0 0 0 0x10000000>;
  531                         compatible = "arm,armv7-timer-mem";
  532                         reg = <0x0 0x0b120000 0x0 0x1000>;
  533 
  534                         frame@b120000 {
  535                                 frame-number = <0>;
  536                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  537                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  538                                 reg = <0x0b121000 0x1000>,
  539                                       <0x0b122000 0x1000>;
  540                         };
  541 
  542                         frame@b123000 {
  543                                 frame-number = <1>;
  544                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  545                                 reg = <0x0b123000 0x1000>;
  546                                 status = "disabled";
  547                         };
  548 
  549                         frame@b124000 {
  550                                 frame-number = <2>;
  551                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  552                                 reg = <0x0b124000 0x1000>;
  553                                 status = "disabled";
  554                         };
  555 
  556                         frame@b125000 {
  557                                 frame-number = <3>;
  558                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  559                                 reg = <0x0b125000 0x1000>;
  560                                 status = "disabled";
  561                         };
  562 
  563                         frame@b126000 {
  564                                 frame-number = <4>;
  565                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  566                                 reg = <0x0b126000 0x1000>;
  567                                 status = "disabled";
  568                         };
  569 
  570                         frame@b127000 {
  571                                 frame-number = <5>;
  572                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  573                                 reg = <0x0b127000 0x1000>;
  574                                 status = "disabled";
  575                         };
  576 
  577                         frame@b128000 {
  578                                 frame-number = <6>;
  579                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  580                                 reg = <0x0b128000 0x1000>;
  581                                 status = "disabled";
  582                         };
  583                 };
  584 
  585                 q6v5_wcss: remoteproc@cd00000 {
  586                         compatible = "qcom,ipq6018-wcss-pil";
  587                         reg = <0x0 0x0cd00000 0x0 0x4040>,
  588                               <0x0 0x004ab000 0x0 0x20>;
  589                         reg-names = "qdsp6",
  590                                     "rmb";
  591                         interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
  592                                               <&wcss_smp2p_in 0 0>,
  593                                               <&wcss_smp2p_in 1 0>,
  594                                               <&wcss_smp2p_in 2 0>,
  595                                               <&wcss_smp2p_in 3 0>;
  596                         interrupt-names = "wdog",
  597                                           "fatal",
  598                                           "ready",
  599                                           "handover",
  600                                           "stop-ack";
  601 
  602                         resets = <&gcc GCC_WCSSAON_RESET>,
  603                                  <&gcc GCC_WCSS_BCR>,
  604                                  <&gcc GCC_WCSS_Q6_BCR>;
  605 
  606                         reset-names = "wcss_aon_reset",
  607                                       "wcss_reset",
  608                                       "wcss_q6_reset";
  609 
  610                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  611                         clock-names = "prng";
  612 
  613                         qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
  614 
  615                         qcom,smem-states = <&wcss_smp2p_out 0>,
  616                                            <&wcss_smp2p_out 1>;
  617                         qcom,smem-state-names = "shutdown",
  618                                                 "stop";
  619 
  620                         memory-region = <&q6_region>;
  621 
  622                         glink-edge {
  623                                 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
  624                                 label = "rtr";
  625                                 qcom,remote-pid = <1>;
  626                                 mboxes = <&apcs_glb 8>;
  627 
  628                                 qrtr_requests {
  629                                         qcom,glink-channels = "IPCRTR";
  630                                 };
  631                         };
  632                 };
  633 
  634                 mdio: mdio@90000 {
  635                         #address-cells = <1>;
  636                         #size-cells = <0>;
  637                         compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
  638                         reg = <0x0 0x90000 0x0 0x64>;
  639                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
  640                         clock-names = "gcc_mdio_ahb_clk";
  641                         status = "disabled";
  642                 };
  643 
  644                 qusb_phy_1: qusb@59000 {
  645                         compatible = "qcom,ipq6018-qusb2-phy";
  646                         reg = <0x0 0x059000 0x0 0x180>;
  647                         #phy-cells = <0>;
  648 
  649                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
  650                                  <&xo>;
  651                         clock-names = "cfg_ahb", "ref";
  652 
  653                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
  654                         status = "disabled";
  655                 };
  656 
  657                 usb2: usb@70f8800 {
  658                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
  659                         reg = <0x0 0x070F8800 0x0 0x400>;
  660                         #address-cells = <2>;
  661                         #size-cells = <2>;
  662                         ranges;
  663                         clocks = <&gcc GCC_USB1_MASTER_CLK>,
  664                                  <&gcc GCC_USB1_SLEEP_CLK>,
  665                                  <&gcc GCC_USB1_MOCK_UTMI_CLK>;
  666                         clock-names = "core",
  667                                       "sleep",
  668                                       "mock_utmi";
  669 
  670                         assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
  671                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
  672                         assigned-clock-rates = <133330000>,
  673                                                <24000000>;
  674                         resets = <&gcc GCC_USB1_BCR>;
  675                         status = "disabled";
  676 
  677                         dwc_1: usb@7000000 {
  678                                compatible = "snps,dwc3";
  679                                reg = <0x0 0x7000000 0x0 0xcd00>;
  680                                interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
  681                                phys = <&qusb_phy_1>;
  682                                phy-names = "usb2-phy";
  683                                tx-fifo-resize;
  684                                snps,is-utmi-l1-suspend;
  685                                snps,hird-threshold = /bits/ 8 <0x0>;
  686                                snps,dis_u2_susphy_quirk;
  687                                snps,dis_u3_susphy_quirk;
  688                                dr_mode = "host";
  689                         };
  690                 };
  691 
  692                 ssphy_0: ssphy@78000 {
  693                         compatible = "qcom,ipq6018-qmp-usb3-phy";
  694                         reg = <0x0 0x78000 0x0 0x1C4>;
  695                         #address-cells = <2>;
  696                         #size-cells = <2>;
  697                         ranges;
  698 
  699                         clocks = <&gcc GCC_USB0_AUX_CLK>,
  700                                  <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>;
  701                         clock-names = "aux", "cfg_ahb", "ref";
  702 
  703                         resets = <&gcc GCC_USB0_PHY_BCR>,
  704                                  <&gcc GCC_USB3PHY_0_PHY_BCR>;
  705                         reset-names = "phy","common";
  706                         status = "disabled";
  707 
  708                         usb0_ssphy: phy@78200 {
  709                                 reg = <0x0 0x00078200 0x0 0x130>, /* Tx */
  710                                       <0x0 0x00078400 0x0 0x200>, /* Rx */
  711                                       <0x0 0x00078800 0x0 0x1F8>, /* PCS */
  712                                       <0x0 0x00078600 0x0 0x044>; /* PCS misc */
  713                                 #phy-cells = <0>;
  714                                 #clock-cells = <0>;
  715                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
  716                                 clock-names = "pipe0";
  717                                 clock-output-names = "gcc_usb0_pipe_clk_src";
  718                         };
  719                 };
  720 
  721                 qusb_phy_0: qusb@79000 {
  722                         compatible = "qcom,ipq6018-qusb2-phy";
  723                         reg = <0x0 0x079000 0x0 0x180>;
  724                         #phy-cells = <0>;
  725 
  726                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
  727                                 <&xo>;
  728                         clock-names = "cfg_ahb", "ref";
  729 
  730                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
  731                         status = "disabled";
  732                 };
  733 
  734                 usb3: usb@8af8800 {
  735                         compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
  736                         reg = <0x0 0x8AF8800 0x0 0x400>;
  737                         #address-cells = <2>;
  738                         #size-cells = <2>;
  739                         ranges;
  740 
  741                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
  742                                 <&gcc GCC_USB0_MASTER_CLK>,
  743                                 <&gcc GCC_USB0_SLEEP_CLK>,
  744                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
  745                         clock-names = "cfg_noc",
  746                                 "core",
  747                                 "sleep",
  748                                 "mock_utmi";
  749 
  750                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
  751                                           <&gcc GCC_USB0_MASTER_CLK>,
  752                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
  753                         assigned-clock-rates = <133330000>,
  754                                                <133330000>,
  755                                                <20000000>;
  756 
  757                         resets = <&gcc GCC_USB0_BCR>;
  758                         status = "disabled";
  759 
  760                         dwc_0: usb@8a00000 {
  761                                 compatible = "snps,dwc3";
  762                                 reg = <0x0 0x8A00000 0x0 0xcd00>;
  763                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  764                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
  765                                 phy-names = "usb2-phy", "usb3-phy";
  766                                 clocks = <&xo>;
  767                                 clock-names = "ref";
  768                                 tx-fifo-resize;
  769                                 snps,is-utmi-l1-suspend;
  770                                 snps,hird-threshold = /bits/ 8 <0x0>;
  771                                 snps,dis_u2_susphy_quirk;
  772                                 snps,dis_u3_susphy_quirk;
  773                                 dr_mode = "host";
  774                         };
  775                 };
  776         };
  777 
  778         wcss: wcss-smp2p {
  779                 compatible = "qcom,smp2p";
  780                 qcom,smem = <435>, <428>;
  781 
  782                 interrupt-parent = <&intc>;
  783                 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
  784 
  785                 mboxes = <&apcs_glb 9>;
  786 
  787                 qcom,local-pid = <0>;
  788                 qcom,remote-pid = <1>;
  789 
  790                 wcss_smp2p_out: master-kernel {
  791                         qcom,entry-name = "master-kernel";
  792                         #qcom,smem-state-cells = <1>;
  793                 };
  794 
  795                 wcss_smp2p_in: slave-kernel {
  796                         qcom,entry-name = "slave-kernel";
  797                         interrupt-controller;
  798                         #interrupt-cells = <2>;
  799                 };
  800         };
  801 
  802         rpm-glink {
  803                 compatible = "qcom,glink-rpm";
  804                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  805                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
  806                 mboxes = <&apcs_glb 0>;
  807 
  808                 rpm_requests: glink-channel {
  809                         compatible = "qcom,rpm-ipq6018";
  810                         qcom,glink-channels = "rpm_requests";
  811 
  812                         regulators {
  813                                 compatible = "qcom,rpm-mp5496-regulators";
  814 
  815                                 ipq6018_s2: s2 {
  816                                         regulator-min-microvolt = <725000>;
  817                                         regulator-max-microvolt = <1062500>;
  818                                         regulator-always-on;
  819                                 };
  820                         };
  821                 };
  822         };
  823 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/ipq6018.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/ipq6018.dtsi
