ipq8074.dtsi

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
    4  */
    5 
    6 #include <dt-bindings/interrupt-controller/arm-gic.h>
    7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
    8 
    9 / {
   10         #address-cells = <2>;
   11         #size-cells = <2>;
   12 
   13         model = "Qualcomm Technologies, Inc. IPQ8074";
   14         compatible = "qcom,ipq8074";
   15         interrupt-parent = <&intc>;
   16 
   17         clocks {
   18                 sleep_clk: sleep_clk {
   19                         compatible = "fixed-clock";
   20                         clock-frequency = <32768>;
   21                         #clock-cells = <0>;
   22                 };
   23 
   24                 xo: xo {
   25                         compatible = "fixed-clock";
   26                         clock-frequency = <19200000>;
   27                         #clock-cells = <0>;
   28                 };
   29         };
   30 
   31         cpus {
   32                 #address-cells = <0x1>;
   33                 #size-cells = <0x0>;
   34 
   35                 CPU0: cpu@0 {
   36                         device_type = "cpu";
   37                         compatible = "arm,cortex-a53";
   38                         reg = <0x0>;
   39                         next-level-cache = <&L2_0>;
   40                         enable-method = "psci";
   41                 };
   42 
   43                 CPU1: cpu@1 {
   44                         device_type = "cpu";
   45                         compatible = "arm,cortex-a53";
   46                         enable-method = "psci";
   47                         reg = <0x1>;
   48                         next-level-cache = <&L2_0>;
   49                 };
   50 
   51                 CPU2: cpu@2 {
   52                         device_type = "cpu";
   53                         compatible = "arm,cortex-a53";
   54                         enable-method = "psci";
   55                         reg = <0x2>;
   56                         next-level-cache = <&L2_0>;
   57                 };
   58 
   59                 CPU3: cpu@3 {
   60                         device_type = "cpu";
   61                         compatible = "arm,cortex-a53";
   62                         enable-method = "psci";
   63                         reg = <0x3>;
   64                         next-level-cache = <&L2_0>;
   65                 };
   66 
   67                 L2_0: l2-cache {
   68                         compatible = "cache";
   69                         cache-level = <0x2>;
   70                 };
   71         };
   72 
   73         pmu {
   74                 compatible = "arm,cortex-a53-pmu";
   75                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
   76         };
   77 
   78         psci {
   79                 compatible = "arm,psci-1.0";
   80                 method = "smc";
   81         };
   82 
   83         reserved-memory {
   84                 #address-cells = <2>;
   85                 #size-cells = <2>;
   86                 ranges;
   87 
   88                 smem@4ab00000 {
   89                         compatible = "qcom,smem";
   90                         reg = <0x0 0x4ab00000 0x0 0x00100000>;
   91                         no-map;
   92 
   93                         hwlocks = <&tcsr_mutex 0>;
   94                 };
   95 
   96                 memory@4ac00000 {
   97                         no-map;
   98                         reg = <0x0 0x4ac00000 0x0 0x00400000>;
   99                 };
  100         };
  101 
  102         firmware {
  103                 scm {
  104                         compatible = "qcom,scm-ipq8074", "qcom,scm";
  105                 };
  106         };
  107 
  108         soc: soc {
  109                 #address-cells = <0x1>;
  110                 #size-cells = <0x1>;
  111                 ranges = <0 0 0 0xffffffff>;
  112                 compatible = "simple-bus";
  113 
  114                 ssphy_1: phy@58000 {
  115                         compatible = "qcom,ipq8074-qmp-usb3-phy";
  116                         reg = <0x00058000 0x1c4>;
  117                         #address-cells = <1>;
  118                         #size-cells = <1>;
  119                         ranges;
  120 
  121                         clocks = <&gcc GCC_USB1_AUX_CLK>,
  122                                 <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
  123                                 <&xo>;
  124                         clock-names = "aux", "cfg_ahb", "ref";
  125 
  126                         resets = <&gcc GCC_USB1_PHY_BCR>,
  127                                 <&gcc GCC_USB3PHY_1_PHY_BCR>;
  128                         reset-names = "phy","common";
  129                         status = "disabled";
  130 
  131                         usb1_ssphy: phy@58200 {
  132                                 reg = <0x00058200 0x130>,       /* Tx */
  133                                       <0x00058400 0x200>,     /* Rx */
  134                                       <0x00058800 0x1f8>,     /* PCS  */
  135                                       <0x00058600 0x044>;     /* PCS misc*/
  136                                 #phy-cells = <0>;
  137                                 #clock-cells = <0>;
  138                                 clocks = <&gcc GCC_USB1_PIPE_CLK>;
  139                                 clock-names = "pipe0";
  140                                 clock-output-names = "gcc_usb1_pipe_clk_src";
  141                         };
  142                 };
  143 
  144                 qusb_phy_1: phy@59000 {
  145                         compatible = "qcom,ipq8074-qusb2-phy";
  146                         reg = <0x00059000 0x180>;
  147                         #phy-cells = <0>;
  148 
  149                         clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>,
  150                                  <&xo>;
  151                         clock-names = "cfg_ahb", "ref";
  152 
  153                         resets = <&gcc GCC_QUSB2_1_PHY_BCR>;
  154                         status = "disabled";
  155                 };
  156 
  157                 ssphy_0: phy@78000 {
  158                         compatible = "qcom,ipq8074-qmp-usb3-phy";
  159                         reg = <0x00078000 0x1c4>;
  160                         #address-cells = <1>;
  161                         #size-cells = <1>;
  162                         ranges;
  163 
  164                         clocks = <&gcc GCC_USB0_AUX_CLK>,
  165                                 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
  166                                 <&xo>;
  167                         clock-names = "aux", "cfg_ahb", "ref";
  168 
  169                         resets = <&gcc GCC_USB0_PHY_BCR>,
  170                                 <&gcc GCC_USB3PHY_0_PHY_BCR>;
  171                         reset-names = "phy","common";
  172                         status = "disabled";
  173 
  174                         usb0_ssphy: phy@78200 {
  175                                 reg = <0x00078200 0x130>,       /* Tx */
  176                                       <0x00078400 0x200>,     /* Rx */
  177                                       <0x00078800 0x1f8>,     /* PCS  */
  178                                       <0x00078600 0x044>;     /* PCS misc*/
  179                                 #phy-cells = <0>;
  180                                 #clock-cells = <0>;
  181                                 clocks = <&gcc GCC_USB0_PIPE_CLK>;
  182                                 clock-names = "pipe0";
  183                                 clock-output-names = "gcc_usb0_pipe_clk_src";
  184                         };
  185                 };
  186 
  187                 qusb_phy_0: phy@79000 {
  188                         compatible = "qcom,ipq8074-qusb2-phy";
  189                         reg = <0x00079000 0x180>;
  190                         #phy-cells = <0>;
  191 
  192                         clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
  193                                  <&xo>;
  194                         clock-names = "cfg_ahb", "ref";
  195 
  196                         resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
  197                         status = "disabled";
  198                 };
  199 
  200                 pcie_qmp0: phy@86000 {
  201                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  202                         reg = <0x00086000 0x1000>;
  203                         #address-cells = <1>;
  204                         #size-cells = <1>;
  205                         ranges;
  206 
  207                         clocks = <&gcc GCC_PCIE0_AUX_CLK>,
  208                                 <&gcc GCC_PCIE0_AHB_CLK>;
  209                         clock-names = "aux", "cfg_ahb";
  210                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
  211                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
  212                         reset-names = "phy",
  213                                       "common";
  214                         status = "disabled";
  215 
  216                         pcie_phy0: phy@86200 {
  217                                 reg = <0x86200 0x16c>,
  218                                       <0x86400 0x200>,
  219                                       <0x86800 0x4f4>;
  220                                 #phy-cells = <0>;
  221                                 #clock-cells = <0>;
  222                                 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  223                                 clock-names = "pipe0";
  224                                 clock-output-names = "pcie_0_pipe_clk";
  225                         };
  226                 };
  227 
  228                 pcie_qmp1: phy@8e000 {
  229                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  230                         reg = <0x0008e000 0x1000>;
  231                         #address-cells = <1>;
  232                         #size-cells = <1>;
  233                         ranges;
  234 
  235                         clocks = <&gcc GCC_PCIE1_AUX_CLK>,
  236                                 <&gcc GCC_PCIE1_AHB_CLK>;
  237                         clock-names = "aux", "cfg_ahb";
  238                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
  239                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
  240                         reset-names = "phy",
  241                                       "common";
  242                         status = "disabled";
  243 
  244                         pcie_phy1: phy@8e200 {
  245                                 reg = <0x8e200 0x16c>,
  246                                       <0x8e400 0x200>,
  247                                       <0x8e800 0x4f4>;
  248                                 #phy-cells = <0>;
  249                                 #clock-cells = <0>;
  250                                 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
  251                                 clock-names = "pipe0";
  252                                 clock-output-names = "pcie_1_pipe_clk";
  253                         };
  254                 };
  255 
  256                 mdio: mdio@90000 {
  257                         compatible = "qcom,ipq4019-mdio";
  258                         reg = <0x00090000 0x64>;
  259                         #address-cells = <1>;
  260                         #size-cells = <0>;
  261 
  262                         clocks = <&gcc GCC_MDIO_AHB_CLK>;
  263                         clock-names = "gcc_mdio_ahb_clk";
  264 
  265                         status = "disabled";
  266                 };
  267 
  268                 prng: rng@e3000 {
  269                         compatible = "qcom,prng-ee";
  270                         reg = <0x000e3000 0x1000>;
  271                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  272                         clock-names = "core";
  273                         status = "disabled";
  274                 };
  275 
  276                 cryptobam: dma-controller@704000 {
  277                         compatible = "qcom,bam-v1.7.0";
  278                         reg = <0x00704000 0x20000>;
  279                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
  280                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
  281                         clock-names = "bam_clk";
  282                         #dma-cells = <1>;
  283                         qcom,ee = <1>;
  284                         qcom,controlled-remotely;
  285                         status = "disabled";
  286                 };
  287 
  288                 crypto: crypto@73a000 {
  289                         compatible = "qcom,crypto-v5.1";
  290                         reg = <0x0073a000 0x6000>;
  291                         clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
  292                                  <&gcc GCC_CRYPTO_AXI_CLK>,
  293                                  <&gcc GCC_CRYPTO_CLK>;
  294                         clock-names = "iface", "bus", "core";
  295                         dmas = <&cryptobam 2>, <&cryptobam 3>;
  296                         dma-names = "rx", "tx";
  297                         status = "disabled";
  298                 };
  299 
  300                 tlmm: pinctrl@1000000 {
  301                         compatible = "qcom,ipq8074-pinctrl";
  302                         reg = <0x01000000 0x300000>;
  303                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  304                         gpio-controller;
  305                         gpio-ranges = <&tlmm 0 0 70>;
  306                         #gpio-cells = <0x2>;
  307                         interrupt-controller;
  308                         #interrupt-cells = <0x2>;
  309 
  310                         serial_4_pins: serial4-pinmux {
  311                                 pins = "gpio23", "gpio24";
  312                                 function = "blsp4_uart1";
  313                                 drive-strength = <8>;
  314                                 bias-disable;
  315                         };
  316 
  317                         i2c_0_pins: i2c-0-pinmux {
  318                                 pins = "gpio42", "gpio43";
  319                                 function = "blsp1_i2c";
  320                                 drive-strength = <8>;
  321                                 bias-disable;
  322                         };
  323 
  324                         spi_0_pins: spi-0-pins {
  325                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
  326                                 function = "blsp0_spi";
  327                                 drive-strength = <8>;
  328                                 bias-disable;
  329                         };
  330 
  331                         hsuart_pins: hsuart-pins {
  332                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
  333                                 function = "blsp2_uart";
  334                                 drive-strength = <8>;
  335                                 bias-disable;
  336                         };
  337 
  338                         qpic_pins: qpic-pins {
  339                                 pins = "gpio1", "gpio3", "gpio4",
  340                                        "gpio5", "gpio6", "gpio7",
  341                                        "gpio8", "gpio10", "gpio11",
  342                                        "gpio12", "gpio13", "gpio14",
  343                                        "gpio15", "gpio16", "gpio17";
  344                                 function = "qpic";
  345                                 drive-strength = <8>;
  346                                 bias-disable;
  347                         };
  348                 };
  349 
  350                 gcc: gcc@1800000 {
  351                         compatible = "qcom,gcc-ipq8074";
  352                         reg = <0x01800000 0x80000>;
  353                         #clock-cells = <0x1>;
  354                         #power-domain-cells = <1>;
  355                         #reset-cells = <0x1>;
  356                 };
  357 
  358                 tcsr_mutex: hwlock@1905000 {
  359                         compatible = "qcom,tcsr-mutex";
  360                         reg = <0x01905000 0x20000>;
  361                         #hwlock-cells = <1>;
  362                 };
  363 
  364                 spmi_bus: spmi@200f000 {
  365                         compatible = "qcom,spmi-pmic-arb";
  366                         reg = <0x0200f000 0x001000>,
  367                               <0x02400000 0x800000>,
  368                               <0x02c00000 0x800000>,
  369                               <0x03800000 0x200000>,
  370                               <0x0200a000 0x000700>;
  371                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
  372                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  373                         interrupt-names = "periph_irq";
  374                         qcom,ee = <0>;
  375                         qcom,channel = <0>;
  376                         #address-cells = <2>;
  377                         #size-cells = <0>;
  378                         interrupt-controller;
  379                         #interrupt-cells = <4>;
  380                         cell-index = <0>;
  381                 };
  382 
  383                 sdhc_1: mmc@7824900 {
  384                         compatible = "qcom,sdhci-msm-v4";
  385                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
  386                         reg-names = "hc_mem", "core_mem";
  387 
  388                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  389                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  390                         interrupt-names = "hc_irq", "pwr_irq";
  391 
  392                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
  393                                  <&gcc GCC_SDCC1_APPS_CLK>,
  394                                  <&xo>;
  395                         clock-names = "iface", "core", "xo";
  396                         resets = <&gcc GCC_SDCC1_BCR>;
  397                         max-frequency = <384000000>;
  398                         mmc-ddr-1_8v;
  399                         mmc-hs200-1_8v;
  400                         mmc-hs400-1_8v;
  401                         bus-width = <8>;
  402 
  403                         status = "disabled";
  404                 };
  405 
  406                 blsp_dma: dma-controller@7884000 {
  407                         compatible = "qcom,bam-v1.7.0";
  408                         reg = <0x07884000 0x2b000>;
  409                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
  410                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
  411                         clock-names = "bam_clk";
  412                         #dma-cells = <1>;
  413                         qcom,ee = <0>;
  414                 };
  415 
  416                 blsp1_uart1: serial@78af000 {
  417                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  418                         reg = <0x078af000 0x200>;
  419                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  420                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
  421                                  <&gcc GCC_BLSP1_AHB_CLK>;
  422                         clock-names = "core", "iface";
  423                         status = "disabled";
  424                 };
  425 
  426                 blsp1_uart3: serial@78b1000 {
  427                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  428                         reg = <0x078b1000 0x200>;
  429                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
  430                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
  431                                 <&gcc GCC_BLSP1_AHB_CLK>;
  432                         clock-names = "core", "iface";
  433                         dmas = <&blsp_dma 4>,
  434                                 <&blsp_dma 5>;
  435                         dma-names = "tx", "rx";
  436                         pinctrl-0 = <&hsuart_pins>;
  437                         pinctrl-names = "default";
  438                         status = "disabled";
  439                 };
  440 
  441                 blsp1_uart5: serial@78b3000 {
  442                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  443                         reg = <0x078b3000 0x200>;
  444                         interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
  445                         clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
  446                                  <&gcc GCC_BLSP1_AHB_CLK>;
  447                         clock-names = "core", "iface";
  448                         pinctrl-0 = <&serial_4_pins>;
  449                         pinctrl-names = "default";
  450                         status = "disabled";
  451                 };
  452 
  453                 blsp1_spi1: spi@78b5000 {
  454                         compatible = "qcom,spi-qup-v2.2.1";
  455                         #address-cells = <1>;
  456                         #size-cells = <0>;
  457                         reg = <0x078b5000 0x600>;
  458                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  459                         spi-max-frequency = <50000000>;
  460                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
  461                                 <&gcc GCC_BLSP1_AHB_CLK>;
  462                         clock-names = "core", "iface";
  463                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
  464                         dma-names = "tx", "rx";
  465                         pinctrl-0 = <&spi_0_pins>;
  466                         pinctrl-names = "default";
  467                         status = "disabled";
  468                 };
  469 
  470                 blsp1_i2c2: i2c@78b6000 {
  471                         compatible = "qcom,i2c-qup-v2.2.1";
  472                         #address-cells = <1>;
  473                         #size-cells = <0>;
  474                         reg = <0x078b6000 0x600>;
  475                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  476                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
  477                                  <&gcc GCC_BLSP1_AHB_CLK>;
  478                         clock-names = "core", "iface";
  479                         clock-frequency = <400000>;
  480                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
  481                         dma-names = "tx", "rx";
  482                         pinctrl-0 = <&i2c_0_pins>;
  483                         pinctrl-names = "default";
  484                         status = "disabled";
  485                 };
  486 
  487                 blsp1_i2c3: i2c@78b7000 {
  488                         compatible = "qcom,i2c-qup-v2.2.1";
  489                         #address-cells = <1>;
  490                         #size-cells = <0>;
  491                         reg = <0x078b7000 0x600>;
  492                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  493                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
  494                                  <&gcc GCC_BLSP1_AHB_CLK>;
  495                         clock-names = "core", "iface";
  496                         clock-frequency = <100000>;
  497                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
  498                         dma-names = "tx", "rx";
  499                         status = "disabled";
  500                 };
  501 
  502                 blsp1_i2c5: i2c@78b9000 {
  503                         compatible = "qcom,i2c-qup-v2.2.1";
  504                         #address-cells = <1>;
  505                         #size-cells = <0>;
  506                         reg = <0x78b9000 0x600>;
  507                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
  508                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
  509                                  <&gcc GCC_BLSP1_AHB_CLK>;
  510                         clock-names = "core", "iface";
  511                         clock-frequency = <400000>;
  512                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
  513                         dma-names = "tx", "rx";
  514                         status = "disabled";
  515                 };
  516 
  517                 blsp1_i2c6: i2c@78ba000 {
  518                         compatible = "qcom,i2c-qup-v2.2.1";
  519                         #address-cells = <1>;
  520                         #size-cells = <0>;
  521                         reg = <0x078ba000 0x600>;
  522                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
  523                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
  524                                  <&gcc GCC_BLSP1_AHB_CLK>;
  525                         clock-names = "core", "iface";
  526                         clock-frequency = <100000>;
  527                         dmas = <&blsp_dma 22>, <&blsp_dma 23>;
  528                         dma-names = "tx", "rx";
  529                         status = "disabled";
  530                 };
  531 
  532                 qpic_bam: dma-controller@7984000 {
  533                         compatible = "qcom,bam-v1.7.0";
  534                         reg = <0x07984000 0x1a000>;
  535                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
  536                         clocks = <&gcc GCC_QPIC_AHB_CLK>;
  537                         clock-names = "bam_clk";
  538                         #dma-cells = <1>;
  539                         qcom,ee = <0>;
  540                         status = "disabled";
  541                 };
  542 
  543                 qpic_nand: nand-controller@79b0000 {
  544                         compatible = "qcom,ipq8074-nand";
  545                         reg = <0x079b0000 0x10000>;
  546                         #address-cells = <1>;
  547                         #size-cells = <0>;
  548                         clocks = <&gcc GCC_QPIC_CLK>,
  549                                  <&gcc GCC_QPIC_AHB_CLK>;
  550                         clock-names = "core", "aon";
  551 
  552                         dmas = <&qpic_bam 0>,
  553                                <&qpic_bam 1>,
  554                                <&qpic_bam 2>;
  555                         dma-names = "tx", "rx", "cmd";
  556                         pinctrl-0 = <&qpic_pins>;
  557                         pinctrl-names = "default";
  558                         status = "disabled";
  559                 };
  560 
  561                 usb_0: usb@8af8800 {
  562                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
  563                         reg = <0x08af8800 0x400>;
  564                         #address-cells = <1>;
  565                         #size-cells = <1>;
  566                         ranges;
  567 
  568                         clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
  569                                 <&gcc GCC_USB0_MASTER_CLK>,
  570                                 <&gcc GCC_USB0_SLEEP_CLK>,
  571                                 <&gcc GCC_USB0_MOCK_UTMI_CLK>;
  572                         clock-names = "cfg_noc",
  573                                 "core",
  574                                 "sleep",
  575                                 "mock_utmi";
  576 
  577                         assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
  578                                           <&gcc GCC_USB0_MASTER_CLK>,
  579                                           <&gcc GCC_USB0_MOCK_UTMI_CLK>;
  580                         assigned-clock-rates = <133330000>,
  581                                                 <133330000>,
  582                                                 <19200000>;
  583 
  584                         power-domains = <&gcc USB0_GDSC>;
  585 
  586                         resets = <&gcc GCC_USB0_BCR>;
  587                         status = "disabled";
  588 
  589                         dwc_0: usb@8a00000 {
  590                                 compatible = "snps,dwc3";
  591                                 reg = <0x8a00000 0xcd00>;
  592                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  593                                 phys = <&qusb_phy_0>, <&usb0_ssphy>;
  594                                 phy-names = "usb2-phy", "usb3-phy";
  595                                 snps,is-utmi-l1-suspend;
  596                                 snps,hird-threshold = /bits/ 8 <0x0>;
  597                                 snps,dis_u2_susphy_quirk;
  598                                 snps,dis_u3_susphy_quirk;
  599                                 dr_mode = "host";
  600                         };
  601                 };
  602 
  603                 usb_1: usb@8cf8800 {
  604                         compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
  605                         reg = <0x08cf8800 0x400>;
  606                         #address-cells = <1>;
  607                         #size-cells = <1>;
  608                         ranges;
  609 
  610                         clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
  611                                 <&gcc GCC_USB1_MASTER_CLK>,
  612                                 <&gcc GCC_USB1_SLEEP_CLK>,
  613                                 <&gcc GCC_USB1_MOCK_UTMI_CLK>;
  614                         clock-names = "cfg_noc",
  615                                 "core",
  616                                 "sleep",
  617                                 "mock_utmi";
  618 
  619                         assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>,
  620                                           <&gcc GCC_USB1_MASTER_CLK>,
  621                                           <&gcc GCC_USB1_MOCK_UTMI_CLK>;
  622                         assigned-clock-rates = <133330000>,
  623                                                 <133330000>,
  624                                                 <19200000>;
  625 
  626                         power-domains = <&gcc USB1_GDSC>;
  627 
  628                         resets = <&gcc GCC_USB1_BCR>;
  629                         status = "disabled";
  630 
  631                         dwc_1: usb@8c00000 {
  632                                 compatible = "snps,dwc3";
  633                                 reg = <0x8c00000 0xcd00>;
  634                                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
  635                                 phys = <&qusb_phy_1>, <&usb1_ssphy>;
  636                                 phy-names = "usb2-phy", "usb3-phy";
  637                                 snps,is-utmi-l1-suspend;
  638                                 snps,hird-threshold = /bits/ 8 <0x0>;
  639                                 snps,dis_u2_susphy_quirk;
  640                                 snps,dis_u3_susphy_quirk;
  641                                 dr_mode = "host";
  642                         };
  643                 };
  644 
  645                 intc: interrupt-controller@b000000 {
  646                         compatible = "qcom,msm-qgic2";
  647                         #address-cells = <1>;
  648                         #size-cells = <1>;
  649                         interrupt-controller;
  650                         #interrupt-cells = <0x3>;
  651                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
  652                         ranges = <0 0xb00a000 0xffd>;
  653 
  654                         v2m@0 {
  655                                 compatible = "arm,gic-v2m-frame";
  656                                 msi-controller;
  657                                 reg = <0x0 0xffd>;
  658                         };
  659                 };
  660 
  661                 watchdog: watchdog@b017000 {
  662                         compatible = "qcom,kpss-wdt";
  663                         reg = <0xb017000 0x1000>;
  664                         interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
  665                         clocks = <&sleep_clk>;
  666                         timeout-sec = <30>;
  667                 };
  668 
  669                 apcs_glb: mailbox@b111000 {
  670                         compatible = "qcom,ipq8074-apcs-apps-global";
  671                         reg = <0x0b111000 0x6000>;
  672 
  673                         #clock-cells = <1>;
  674                         #mbox-cells = <1>;
  675                 };
  676 
  677                 timer@b120000 {
  678                         #address-cells = <1>;
  679                         #size-cells = <1>;
  680                         ranges;
  681                         compatible = "arm,armv7-timer-mem";
  682                         reg = <0x0b120000 0x1000>;
  683 
  684                         frame@b120000 {
  685                                 frame-number = <0>;
  686                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  687                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  688                                 reg = <0x0b121000 0x1000>,
  689                                       <0x0b122000 0x1000>;
  690                         };
  691 
  692                         frame@b123000 {
  693                                 frame-number = <1>;
  694                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  695                                 reg = <0x0b123000 0x1000>;
  696                                 status = "disabled";
  697                         };
  698 
  699                         frame@b124000 {
  700                                 frame-number = <2>;
  701                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
  702                                 reg = <0x0b124000 0x1000>;
  703                                 status = "disabled";
  704                         };
  705 
  706                         frame@b125000 {
  707                                 frame-number = <3>;
  708                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  709                                 reg = <0x0b125000 0x1000>;
  710                                 status = "disabled";
  711                         };
  712 
  713                         frame@b126000 {
  714                                 frame-number = <4>;
  715                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
  716                                 reg = <0x0b126000 0x1000>;
  717                                 status = "disabled";
  718                         };
  719 
  720                         frame@b127000 {
  721                                 frame-number = <5>;
  722                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
  723                                 reg = <0x0b127000 0x1000>;
  724                                 status = "disabled";
  725                         };
  726 
  727                         frame@b128000 {
  728                                 frame-number = <6>;
  729                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
  730                                 reg = <0x0b128000 0x1000>;
  731                                 status = "disabled";
  732                         };
  733                 };
  734 
  735                 pcie1: pci@10000000 {
  736                         compatible = "qcom,pcie-ipq8074";
  737                         reg =  <0x10000000 0xf1d>,
  738                                <0x10000f20 0xa8>,
  739                                <0x00088000 0x2000>,
  740                                <0x10100000 0x1000>;
  741                         reg-names = "dbi", "elbi", "parf", "config";
  742                         device_type = "pci";
  743                         linux,pci-domain = <1>;
  744                         bus-range = <0x00 0xff>;
  745                         num-lanes = <1>;
  746                         #address-cells = <3>;
  747                         #size-cells = <2>;
  748 
  749                         phys = <&pcie_phy1>;
  750                         phy-names = "pciephy";
  751 
  752                         ranges = <0x81000000 0 0x10200000 0x10200000
  753                                   0 0x100000   /* downstream I/O */
  754                                   0x82000000 0 0x10300000 0x10300000
  755                                   0 0xd00000>; /* non-prefetchable memory */
  756 
  757                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
  758                         interrupt-names = "msi";
  759                         #interrupt-cells = <1>;
  760                         interrupt-map-mask = <0 0 0 0x7>;
  761                         interrupt-map = <0 0 0 1 &intc 0 142
  762                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  763                                         <0 0 0 2 &intc 0 143
  764                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  765                                         <0 0 0 3 &intc 0 144
  766                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  767                                         <0 0 0 4 &intc 0 145
  768                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  769 
  770                         clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
  771                                  <&gcc GCC_PCIE1_AXI_M_CLK>,
  772                                  <&gcc GCC_PCIE1_AXI_S_CLK>,
  773                                  <&gcc GCC_PCIE1_AHB_CLK>,
  774                                  <&gcc GCC_PCIE1_AUX_CLK>;
  775                         clock-names = "iface",
  776                                       "axi_m",
  777                                       "axi_s",
  778                                       "ahb",
  779                                       "aux";
  780                         resets = <&gcc GCC_PCIE1_PIPE_ARES>,
  781                                  <&gcc GCC_PCIE1_SLEEP_ARES>,
  782                                  <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
  783                                  <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
  784                                  <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
  785                                  <&gcc GCC_PCIE1_AHB_ARES>,
  786                                  <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
  787                         reset-names = "pipe",
  788                                       "sleep",
  789                                       "sticky",
  790                                       "axi_m",
  791                                       "axi_s",
  792                                       "ahb",
  793                                       "axi_m_sticky";
  794                         status = "disabled";
  795                 };
  796 
  797                 pcie0: pci@20000000 {
  798                         compatible = "qcom,pcie-ipq8074";
  799                         reg = <0x20000000 0xf1d>,
  800                               <0x20000f20 0xa8>,
  801                               <0x00080000 0x2000>,
  802                               <0x20100000 0x1000>;
  803                         reg-names = "dbi", "elbi", "parf", "config";
  804                         device_type = "pci";
  805                         linux,pci-domain = <0>;
  806                         bus-range = <0x00 0xff>;
  807                         num-lanes = <1>;
  808                         #address-cells = <3>;
  809                         #size-cells = <2>;
  810 
  811                         phys = <&pcie_phy0>;
  812                         phy-names = "pciephy";
  813 
  814                         ranges = <0x81000000 0 0x20200000 0x20200000
  815                                   0 0x100000   /* downstream I/O */
  816                                   0x82000000 0 0x20300000 0x20300000
  817                                   0 0xd00000>; /* non-prefetchable memory */
  818 
  819                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  820                         interrupt-names = "msi";
  821                         #interrupt-cells = <1>;
  822                         interrupt-map-mask = <0 0 0 0x7>;
  823                         interrupt-map = <0 0 0 1 &intc 0 75
  824                                          IRQ_TYPE_LEVEL_HIGH>, /* int_a */
  825                                         <0 0 0 2 &intc 0 78
  826                                          IRQ_TYPE_LEVEL_HIGH>, /* int_b */
  827                                         <0 0 0 3 &intc 0 79
  828                                          IRQ_TYPE_LEVEL_HIGH>, /* int_c */
  829                                         <0 0 0 4 &intc 0 83
  830                                          IRQ_TYPE_LEVEL_HIGH>; /* int_d */
  831 
  832                         clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
  833                                  <&gcc GCC_PCIE0_AXI_M_CLK>,
  834                                  <&gcc GCC_PCIE0_AXI_S_CLK>,
  835                                  <&gcc GCC_PCIE0_AHB_CLK>,
  836                                  <&gcc GCC_PCIE0_AUX_CLK>;
  837 
  838                         clock-names = "iface",
  839                                       "axi_m",
  840                                       "axi_s",
  841                                       "ahb",
  842                                       "aux";
  843                         resets = <&gcc GCC_PCIE0_PIPE_ARES>,
  844                                  <&gcc GCC_PCIE0_SLEEP_ARES>,
  845                                  <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
  846                                  <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
  847                                  <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
  848                                  <&gcc GCC_PCIE0_AHB_ARES>,
  849                                  <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
  850                         reset-names = "pipe",
  851                                       "sleep",
  852                                       "sticky",
  853                                       "axi_m",
  854                                       "axi_s",
  855                                       "ahb",
  856                                       "axi_m_sticky";
  857                         status = "disabled";
  858                 };
  859         };
  860 
  861         timer {
  862                 compatible = "arm,armv8-timer";
  863                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  864                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  865                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  866                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  867         };
  868 };
Cache object: bf88f4a934d7c9ade58404ec99687428
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.
FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/ipq8074.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/ipq8074.dtsi
