msm8916.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
    4  */
    5 
    6 #include <dt-bindings/arm/coresight-cti-dt.h>
    7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
    8 #include <dt-bindings/clock/qcom,rpmcc.h>
    9 #include <dt-bindings/interconnect/qcom,msm8916.h>
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 #include <dt-bindings/power/qcom-rpmpd.h>
   12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
   13 #include <dt-bindings/thermal/thermal.h>
   14 
   15 / {
   16         interrupt-parent = <&intc>;
   17 
   18         #address-cells = <2>;
   19         #size-cells = <2>;
   20 
   21         aliases {
   22                 mmc0 = &sdhc_1; /* SDC1 eMMC slot */
   23                 mmc1 = &sdhc_2; /* SDC2 SD card slot */
   24         };
   25 
   26         chosen { };
   27 
   28         memory@80000000 {
   29                 device_type = "memory";
   30                 /* We expect the bootloader to fill in the reg */
   31                 reg = <0 0x80000000 0 0>;
   32         };
   33 
   34         reserved-memory {
   35                 #address-cells = <2>;
   36                 #size-cells = <2>;
   37                 ranges;
   38 
   39                 tz-apps@86000000 {
   40                         reg = <0x0 0x86000000 0x0 0x300000>;
   41                         no-map;
   42                 };
   43 
   44                 smem@86300000 {
   45                         compatible = "qcom,smem";
   46                         reg = <0x0 0x86300000 0x0 0x100000>;
   47                         no-map;
   48 
   49                         hwlocks = <&tcsr_mutex 3>;
   50                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
   51                 };
   52 
   53                 hypervisor@86400000 {
   54                         reg = <0x0 0x86400000 0x0 0x100000>;
   55                         no-map;
   56                 };
   57 
   58                 tz@86500000 {
   59                         reg = <0x0 0x86500000 0x0 0x180000>;
   60                         no-map;
   61                 };
   62 
   63                 reserved@86680000 {
   64                         reg = <0x0 0x86680000 0x0 0x80000>;
   65                         no-map;
   66                 };
   67 
   68                 rmtfs@86700000 {
   69                         compatible = "qcom,rmtfs-mem";
   70                         reg = <0x0 0x86700000 0x0 0xe0000>;
   71                         no-map;
   72 
   73                         qcom,client-id = <1>;
   74                 };
   75 
   76                 rfsa@867e0000 {
   77                         reg = <0x0 0x867e0000 0x0 0x20000>;
   78                         no-map;
   79                 };
   80 
   81                 mpss_mem: mpss@86800000 {
   82                         reg = <0x0 0x86800000 0x0 0x2b00000>;
   83                         no-map;
   84                 };
   85 
   86                 wcnss_mem: wcnss@89300000 {
   87                         reg = <0x0 0x89300000 0x0 0x600000>;
   88                         no-map;
   89                 };
   90 
   91                 venus_mem: venus@89900000 {
   92                         reg = <0x0 0x89900000 0x0 0x600000>;
   93                         no-map;
   94                 };
   95 
   96                 mba_mem: mba@8ea00000 {
   97                         no-map;
   98                         reg = <0 0x8ea00000 0 0x100000>;
   99                 };
  100         };
  101 
  102         clocks {
  103                 xo_board: xo-board {
  104                         compatible = "fixed-clock";
  105                         #clock-cells = <0>;
  106                         clock-frequency = <19200000>;
  107                 };
  108 
  109                 sleep_clk: sleep-clk {
  110                         compatible = "fixed-clock";
  111                         #clock-cells = <0>;
  112                         clock-frequency = <32768>;
  113                 };
  114         };
  115 
  116         cpus {
  117                 #address-cells = <1>;
  118                 #size-cells = <0>;
  119 
  120                 CPU0: cpu@0 {
  121                         device_type = "cpu";
  122                         compatible = "arm,cortex-a53";
  123                         reg = <0x0>;
  124                         next-level-cache = <&L2_0>;
  125                         enable-method = "psci";
  126                         clocks = <&apcs>;
  127                         operating-points-v2 = <&cpu_opp_table>;
  128                         #cooling-cells = <2>;
  129                         power-domains = <&CPU_PD0>;
  130                         power-domain-names = "psci";
  131                         qcom,acc = <&cpu0_acc>;
  132                         qcom,saw = <&cpu0_saw>;
  133                 };
  134 
  135                 CPU1: cpu@1 {
  136                         device_type = "cpu";
  137                         compatible = "arm,cortex-a53";
  138                         reg = <0x1>;
  139                         next-level-cache = <&L2_0>;
  140                         enable-method = "psci";
  141                         clocks = <&apcs>;
  142                         operating-points-v2 = <&cpu_opp_table>;
  143                         #cooling-cells = <2>;
  144                         power-domains = <&CPU_PD1>;
  145                         power-domain-names = "psci";
  146                         qcom,acc = <&cpu1_acc>;
  147                         qcom,saw = <&cpu1_saw>;
  148                 };
  149 
  150                 CPU2: cpu@2 {
  151                         device_type = "cpu";
  152                         compatible = "arm,cortex-a53";
  153                         reg = <0x2>;
  154                         next-level-cache = <&L2_0>;
  155                         enable-method = "psci";
  156                         clocks = <&apcs>;
  157                         operating-points-v2 = <&cpu_opp_table>;
  158                         #cooling-cells = <2>;
  159                         power-domains = <&CPU_PD2>;
  160                         power-domain-names = "psci";
  161                         qcom,acc = <&cpu2_acc>;
  162                         qcom,saw = <&cpu2_saw>;
  163                 };
  164 
  165                 CPU3: cpu@3 {
  166                         device_type = "cpu";
  167                         compatible = "arm,cortex-a53";
  168                         reg = <0x3>;
  169                         next-level-cache = <&L2_0>;
  170                         enable-method = "psci";
  171                         clocks = <&apcs>;
  172                         operating-points-v2 = <&cpu_opp_table>;
  173                         #cooling-cells = <2>;
  174                         power-domains = <&CPU_PD3>;
  175                         power-domain-names = "psci";
  176                         qcom,acc = <&cpu3_acc>;
  177                         qcom,saw = <&cpu3_saw>;
  178                 };
  179 
  180                 L2_0: l2-cache {
  181                         compatible = "cache";
  182                         cache-level = <2>;
  183                 };
  184 
  185                 idle-states {
  186                         entry-method = "psci";
  187 
  188                         CPU_SLEEP_0: cpu-sleep-0 {
  189                                 compatible = "arm,idle-state";
  190                                 idle-state-name = "standalone-power-collapse";
  191                                 arm,psci-suspend-param = <0x40000002>;
  192                                 entry-latency-us = <130>;
  193                                 exit-latency-us = <150>;
  194                                 min-residency-us = <2000>;
  195                                 local-timer-stop;
  196                         };
  197                 };
  198 
  199                 domain-idle-states {
  200 
  201                         CLUSTER_RET: cluster-retention {
  202                                 compatible = "domain-idle-state";
  203                                 arm,psci-suspend-param = <0x41000012>;
  204                                 entry-latency-us = <500>;
  205                                 exit-latency-us = <500>;
  206                                 min-residency-us = <2000>;
  207                         };
  208 
  209                         CLUSTER_PWRDN: cluster-gdhs {
  210                                 compatible = "domain-idle-state";
  211                                 arm,psci-suspend-param = <0x41000032>;
  212                                 entry-latency-us = <2000>;
  213                                 exit-latency-us = <2000>;
  214                                 min-residency-us = <6000>;
  215                         };
  216                 };
  217         };
  218 
  219         cpu_opp_table: opp-table-cpu {
  220                 compatible = "operating-points-v2";
  221                 opp-shared;
  222 
  223                 opp-200000000 {
  224                         opp-hz = /bits/ 64 <200000000>;
  225                 };
  226                 opp-400000000 {
  227                         opp-hz = /bits/ 64 <400000000>;
  228                 };
  229                 opp-800000000 {
  230                         opp-hz = /bits/ 64 <800000000>;
  231                 };
  232                 opp-998400000 {
  233                         opp-hz = /bits/ 64 <998400000>;
  234                 };
  235         };
  236 
  237         firmware {
  238                 scm: scm {
  239                         compatible = "qcom,scm-msm8916", "qcom,scm";
  240                         clocks = <&gcc GCC_CRYPTO_CLK>,
  241                                  <&gcc GCC_CRYPTO_AXI_CLK>,
  242                                  <&gcc GCC_CRYPTO_AHB_CLK>;
  243                         clock-names = "core", "bus", "iface";
  244                         #reset-cells = <1>;
  245 
  246                         qcom,dload-mode = <&tcsr 0x6100>;
  247                 };
  248         };
  249 
  250         pmu {
  251                 compatible = "arm,cortex-a53-pmu";
  252                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  253         };
  254 
  255         psci {
  256                 compatible = "arm,psci-1.0";
  257                 method = "smc";
  258 
  259                 CPU_PD0: power-domain-cpu0 {
  260                         #power-domain-cells = <0>;
  261                         power-domains = <&CLUSTER_PD>;
  262                         domain-idle-states = <&CPU_SLEEP_0>;
  263                 };
  264 
  265                 CPU_PD1: power-domain-cpu1 {
  266                         #power-domain-cells = <0>;
  267                         power-domains = <&CLUSTER_PD>;
  268                         domain-idle-states = <&CPU_SLEEP_0>;
  269                 };
  270 
  271                 CPU_PD2: power-domain-cpu2 {
  272                         #power-domain-cells = <0>;
  273                         power-domains = <&CLUSTER_PD>;
  274                         domain-idle-states = <&CPU_SLEEP_0>;
  275                 };
  276 
  277                 CPU_PD3: power-domain-cpu3 {
  278                         #power-domain-cells = <0>;
  279                         power-domains = <&CLUSTER_PD>;
  280                         domain-idle-states = <&CPU_SLEEP_0>;
  281                 };
  282 
  283                 CLUSTER_PD: power-domain-cluster {
  284                         #power-domain-cells = <0>;
  285                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
  286                 };
  287         };
  288 
  289         smd {
  290                 compatible = "qcom,smd";
  291 
  292                 rpm {
  293                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  294                         qcom,ipc = <&apcs 8 0>;
  295                         qcom,smd-edge = <15>;
  296 
  297                         rpm_requests: rpm-requests {
  298                                 compatible = "qcom,rpm-msm8916";
  299                                 qcom,smd-channels = "rpm_requests";
  300 
  301                                 rpmcc: clock-controller {
  302                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
  303                                         #clock-cells = <1>;
  304                                         clocks = <&xo_board>;
  305                                         clock-names = "xo";
  306                                 };
  307 
  308                                 rpmpd: power-controller {
  309                                         compatible = "qcom,msm8916-rpmpd";
  310                                         #power-domain-cells = <1>;
  311                                         operating-points-v2 = <&rpmpd_opp_table>;
  312 
  313                                         rpmpd_opp_table: opp-table {
  314                                                 compatible = "operating-points-v2";
  315 
  316                                                 rpmpd_opp_ret: opp1 {
  317                                                         opp-level = <1>;
  318                                                 };
  319                                                 rpmpd_opp_svs_krait: opp2 {
  320                                                         opp-level = <2>;
  321                                                 };
  322                                                 rpmpd_opp_svs_soc: opp3 {
  323                                                         opp-level = <3>;
  324                                                 };
  325                                                 rpmpd_opp_nom: opp4 {
  326                                                         opp-level = <4>;
  327                                                 };
  328                                                 rpmpd_opp_turbo: opp5 {
  329                                                         opp-level = <5>;
  330                                                 };
  331                                                 rpmpd_opp_super_turbo: opp6 {
  332                                                         opp-level = <6>;
  333                                                 };
  334                                         };
  335                                 };
  336                         };
  337                 };
  338         };
  339 
  340         smp2p-hexagon {
  341                 compatible = "qcom,smp2p";
  342                 qcom,smem = <435>, <428>;
  343 
  344                 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
  345 
  346                 qcom,ipc = <&apcs 8 14>;
  347 
  348                 qcom,local-pid = <0>;
  349                 qcom,remote-pid = <1>;
  350 
  351                 hexagon_smp2p_out: master-kernel {
  352                         qcom,entry-name = "master-kernel";
  353 
  354                         #qcom,smem-state-cells = <1>;
  355                 };
  356 
  357                 hexagon_smp2p_in: slave-kernel {
  358                         qcom,entry-name = "slave-kernel";
  359 
  360                         interrupt-controller;
  361                         #interrupt-cells = <2>;
  362                 };
  363         };
  364 
  365         smp2p-wcnss {
  366                 compatible = "qcom,smp2p";
  367                 qcom,smem = <451>, <431>;
  368 
  369                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
  370 
  371                 qcom,ipc = <&apcs 8 18>;
  372 
  373                 qcom,local-pid = <0>;
  374                 qcom,remote-pid = <4>;
  375 
  376                 wcnss_smp2p_out: master-kernel {
  377                         qcom,entry-name = "master-kernel";
  378 
  379                         #qcom,smem-state-cells = <1>;
  380                 };
  381 
  382                 wcnss_smp2p_in: slave-kernel {
  383                         qcom,entry-name = "slave-kernel";
  384 
  385                         interrupt-controller;
  386                         #interrupt-cells = <2>;
  387                 };
  388         };
  389 
  390         smsm {
  391                 compatible = "qcom,smsm";
  392 
  393                 #address-cells = <1>;
  394                 #size-cells = <0>;
  395 
  396                 qcom,ipc-1 = <&apcs 8 13>;
  397                 qcom,ipc-3 = <&apcs 8 19>;
  398 
  399                 apps_smsm: apps@0 {
  400                         reg = <0>;
  401 
  402                         #qcom,smem-state-cells = <1>;
  403                 };
  404 
  405                 hexagon_smsm: hexagon@1 {
  406                         reg = <1>;
  407                         interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
  408 
  409                         interrupt-controller;
  410                         #interrupt-cells = <2>;
  411                 };
  412 
  413                 wcnss_smsm: wcnss@6 {
  414                         reg = <6>;
  415                         interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
  416 
  417                         interrupt-controller;
  418                         #interrupt-cells = <2>;
  419                 };
  420         };
  421 
  422         soc: soc@0 {
  423                 #address-cells = <1>;
  424                 #size-cells = <1>;
  425                 ranges = <0 0 0 0xffffffff>;
  426                 compatible = "simple-bus";
  427 
  428                 rng@22000 {
  429                         compatible = "qcom,prng";
  430                         reg = <0x00022000 0x200>;
  431                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  432                         clock-names = "core";
  433                 };
  434 
  435                 restart@4ab000 {
  436                         compatible = "qcom,pshold";
  437                         reg = <0x004ab000 0x4>;
  438                 };
  439 
  440                 qfprom: qfprom@5c000 {
  441                         compatible = "qcom,msm8916-qfprom", "qcom,qfprom";
  442                         reg = <0x0005c000 0x1000>;
  443                         #address-cells = <1>;
  444                         #size-cells = <1>;
  445                         tsens_caldata: caldata@d0 {
  446                                 reg = <0xd0 0x8>;
  447                         };
  448                         tsens_calsel: calsel@ec {
  449                                 reg = <0xec 0x4>;
  450                         };
  451                 };
  452 
  453                 rpm_msg_ram: sram@60000 {
  454                         compatible = "qcom,rpm-msg-ram";
  455                         reg = <0x00060000 0x8000>;
  456                 };
  457 
  458                 sram@290000 {
  459                         compatible = "qcom,msm8916-rpm-stats";
  460                         reg = <0x00290000 0x10000>;
  461                 };
  462 
  463                 bimc: interconnect@400000 {
  464                         compatible = "qcom,msm8916-bimc";
  465                         reg = <0x00400000 0x62000>;
  466                         #interconnect-cells = <1>;
  467                         clock-names = "bus", "bus_a";
  468                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
  469                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
  470                 };
  471 
  472                 tsens: thermal-sensor@4a9000 {
  473                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
  474                         reg = <0x004a9000 0x1000>, /* TM */
  475                               <0x004a8000 0x1000>; /* SROT */
  476                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
  477                         nvmem-cell-names = "calib", "calib_sel";
  478                         #qcom,sensors = <5>;
  479                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  480                         interrupt-names = "uplow";
  481                         #thermal-sensor-cells = <1>;
  482                 };
  483 
  484                 pcnoc: interconnect@500000 {
  485                         compatible = "qcom,msm8916-pcnoc";
  486                         reg = <0x00500000 0x11000>;
  487                         #interconnect-cells = <1>;
  488                         clock-names = "bus", "bus_a";
  489                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
  490                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
  491                 };
  492 
  493                 snoc: interconnect@580000 {
  494                         compatible = "qcom,msm8916-snoc";
  495                         reg = <0x00580000 0x14000>;
  496                         #interconnect-cells = <1>;
  497                         clock-names = "bus", "bus_a";
  498                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
  499                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
  500                 };
  501 
  502                 stm: stm@802000 {
  503                         compatible = "arm,coresight-stm", "arm,primecell";
  504                         reg = <0x00802000 0x1000>,
  505                               <0x09280000 0x180000>;
  506                         reg-names = "stm-base", "stm-stimulus-base";
  507 
  508                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  509                         clock-names = "apb_pclk", "atclk";
  510 
  511                         status = "disabled";
  512 
  513                         out-ports {
  514                                 port {
  515                                         stm_out: endpoint {
  516                                                 remote-endpoint = <&funnel0_in7>;
  517                                         };
  518                                 };
  519                         };
  520                 };
  521 
  522                 /* System CTIs */
  523                 /* CTI 0 - TMC connections */
  524                 cti0: cti@810000 {
  525                         compatible = "arm,coresight-cti", "arm,primecell";
  526                         reg = <0x00810000 0x1000>;
  527 
  528                         clocks = <&rpmcc RPM_QDSS_CLK>;
  529                         clock-names = "apb_pclk";
  530 
  531                         status = "disabled";
  532                 };
  533 
  534                 /* CTI 1 - TPIU connections */
  535                 cti1: cti@811000 {
  536                         compatible = "arm,coresight-cti", "arm,primecell";
  537                         reg = <0x00811000 0x1000>;
  538 
  539                         clocks = <&rpmcc RPM_QDSS_CLK>;
  540                         clock-names = "apb_pclk";
  541 
  542                         status = "disabled";
  543                 };
  544 
  545                 /* CTIs 2-11 - no information - not instantiated */
  546 
  547                 tpiu: tpiu@820000 {
  548                         compatible = "arm,coresight-tpiu", "arm,primecell";
  549                         reg = <0x00820000 0x1000>;
  550 
  551                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  552                         clock-names = "apb_pclk", "atclk";
  553 
  554                         status = "disabled";
  555 
  556                         in-ports {
  557                                 port {
  558                                         tpiu_in: endpoint {
  559                                                 remote-endpoint = <&replicator_out1>;
  560                                         };
  561                                 };
  562                         };
  563                 };
  564 
  565                 funnel0: funnel@821000 {
  566                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
  567                         reg = <0x00821000 0x1000>;
  568 
  569                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  570                         clock-names = "apb_pclk", "atclk";
  571 
  572                         status = "disabled";
  573 
  574                         in-ports {
  575                                 #address-cells = <1>;
  576                                 #size-cells = <0>;
  577 
  578                                 /*
  579                                  * Not described input ports:
  580                                  * 0 - connected to Resource and Power Manger CPU ETM
  581                                  * 1 - not-connected
  582                                  * 2 - connected to Modem CPU ETM
  583                                  * 3 - not-connected
  584                                  * 5 - not-connected
  585                                  * 6 - connected trought funnel to Wireless CPU ETM
  586                                  * 7 - connected to STM component
  587                                  */
  588 
  589                                 port@4 {
  590                                         reg = <4>;
  591                                         funnel0_in4: endpoint {
  592                                                 remote-endpoint = <&funnel1_out>;
  593                                         };
  594                                 };
  595 
  596                                 port@7 {
  597                                         reg = <7>;
  598                                         funnel0_in7: endpoint {
  599                                                 remote-endpoint = <&stm_out>;
  600                                         };
  601                                 };
  602                         };
  603 
  604                         out-ports {
  605                                 port {
  606                                         funnel0_out: endpoint {
  607                                                 remote-endpoint = <&etf_in>;
  608                                         };
  609                                 };
  610                         };
  611                 };
  612 
  613                 replicator: replicator@824000 {
  614                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
  615                         reg = <0x00824000 0x1000>;
  616 
  617                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  618                         clock-names = "apb_pclk", "atclk";
  619 
  620                         status = "disabled";
  621 
  622                         out-ports {
  623                                 #address-cells = <1>;
  624                                 #size-cells = <0>;
  625 
  626                                 port@0 {
  627                                         reg = <0>;
  628                                         replicator_out0: endpoint {
  629                                                 remote-endpoint = <&etr_in>;
  630                                         };
  631                                 };
  632                                 port@1 {
  633                                         reg = <1>;
  634                                         replicator_out1: endpoint {
  635                                                 remote-endpoint = <&tpiu_in>;
  636                                         };
  637                                 };
  638                         };
  639 
  640                         in-ports {
  641                                 port {
  642                                         replicator_in: endpoint {
  643                                                 remote-endpoint = <&etf_out>;
  644                                         };
  645                                 };
  646                         };
  647                 };
  648 
  649                 etf: etf@825000 {
  650                         compatible = "arm,coresight-tmc", "arm,primecell";
  651                         reg = <0x00825000 0x1000>;
  652 
  653                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  654                         clock-names = "apb_pclk", "atclk";
  655 
  656                         status = "disabled";
  657 
  658                         in-ports {
  659                                 port {
  660                                         etf_in: endpoint {
  661                                                 remote-endpoint = <&funnel0_out>;
  662                                         };
  663                                 };
  664                         };
  665 
  666                         out-ports {
  667                                 port {
  668                                         etf_out: endpoint {
  669                                                 remote-endpoint = <&replicator_in>;
  670                                         };
  671                                 };
  672                         };
  673                 };
  674 
  675                 etr: etr@826000 {
  676                         compatible = "arm,coresight-tmc", "arm,primecell";
  677                         reg = <0x00826000 0x1000>;
  678 
  679                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  680                         clock-names = "apb_pclk", "atclk";
  681 
  682                         status = "disabled";
  683 
  684                         in-ports {
  685                                 port {
  686                                         etr_in: endpoint {
  687                                                 remote-endpoint = <&replicator_out0>;
  688                                         };
  689                                 };
  690                         };
  691                 };
  692 
  693                 funnel1: funnel@841000 {        /* APSS funnel only 4 inputs are used */
  694                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
  695                         reg = <0x00841000 0x1000>;
  696 
  697                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  698                         clock-names = "apb_pclk", "atclk";
  699 
  700                         status = "disabled";
  701 
  702                         in-ports {
  703                                 #address-cells = <1>;
  704                                 #size-cells = <0>;
  705 
  706                                 port@0 {
  707                                         reg = <0>;
  708                                         funnel1_in0: endpoint {
  709                                                 remote-endpoint = <&etm0_out>;
  710                                         };
  711                                 };
  712                                 port@1 {
  713                                         reg = <1>;
  714                                         funnel1_in1: endpoint {
  715                                                 remote-endpoint = <&etm1_out>;
  716                                         };
  717                                 };
  718                                 port@2 {
  719                                         reg = <2>;
  720                                         funnel1_in2: endpoint {
  721                                                 remote-endpoint = <&etm2_out>;
  722                                         };
  723                                 };
  724                                 port@3 {
  725                                         reg = <3>;
  726                                         funnel1_in3: endpoint {
  727                                                 remote-endpoint = <&etm3_out>;
  728                                         };
  729                                 };
  730                         };
  731 
  732                         out-ports {
  733                                 port {
  734                                         funnel1_out: endpoint {
  735                                                 remote-endpoint = <&funnel0_in4>;
  736                                         };
  737                                 };
  738                         };
  739                 };
  740 
  741                 debug0: debug@850000 {
  742                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
  743                         reg = <0x00850000 0x1000>;
  744                         clocks = <&rpmcc RPM_QDSS_CLK>;
  745                         clock-names = "apb_pclk";
  746                         cpu = <&CPU0>;
  747                         status = "disabled";
  748                 };
  749 
  750                 debug1: debug@852000 {
  751                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
  752                         reg = <0x00852000 0x1000>;
  753                         clocks = <&rpmcc RPM_QDSS_CLK>;
  754                         clock-names = "apb_pclk";
  755                         cpu = <&CPU1>;
  756                         status = "disabled";
  757                 };
  758 
  759                 debug2: debug@854000 {
  760                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
  761                         reg = <0x00854000 0x1000>;
  762                         clocks = <&rpmcc RPM_QDSS_CLK>;
  763                         clock-names = "apb_pclk";
  764                         cpu = <&CPU2>;
  765                         status = "disabled";
  766                 };
  767 
  768                 debug3: debug@856000 {
  769                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
  770                         reg = <0x00856000 0x1000>;
  771                         clocks = <&rpmcc RPM_QDSS_CLK>;
  772                         clock-names = "apb_pclk";
  773                         cpu = <&CPU3>;
  774                         status = "disabled";
  775                 };
  776 
  777                 /* Core CTIs; CTIs 12-15 */
  778                 /* CTI - CPU-0 */
  779                 cti12: cti@858000 {
  780                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
  781                                      "arm,primecell";
  782                         reg = <0x00858000 0x1000>;
  783 
  784                         clocks = <&rpmcc RPM_QDSS_CLK>;
  785                         clock-names = "apb_pclk";
  786 
  787                         cpu = <&CPU0>;
  788                         arm,cs-dev-assoc = <&etm0>;
  789 
  790                         status = "disabled";
  791                 };
  792 
  793                 /* CTI - CPU-1 */
  794                 cti13: cti@859000 {
  795                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
  796                                      "arm,primecell";
  797                         reg = <0x00859000 0x1000>;
  798 
  799                         clocks = <&rpmcc RPM_QDSS_CLK>;
  800                         clock-names = "apb_pclk";
  801 
  802                         cpu = <&CPU1>;
  803                         arm,cs-dev-assoc = <&etm1>;
  804 
  805                         status = "disabled";
  806                 };
  807 
  808                 /* CTI - CPU-2 */
  809                 cti14: cti@85a000 {
  810                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
  811                                      "arm,primecell";
  812                         reg = <0x0085a000 0x1000>;
  813 
  814                         clocks = <&rpmcc RPM_QDSS_CLK>;
  815                         clock-names = "apb_pclk";
  816 
  817                         cpu = <&CPU2>;
  818                         arm,cs-dev-assoc = <&etm2>;
  819 
  820                         status = "disabled";
  821                 };
  822 
  823                 /* CTI - CPU-3 */
  824                 cti15: cti@85b000 {
  825                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
  826                                      "arm,primecell";
  827                         reg = <0x0085b000 0x1000>;
  828 
  829                         clocks = <&rpmcc RPM_QDSS_CLK>;
  830                         clock-names = "apb_pclk";
  831 
  832                         cpu = <&CPU3>;
  833                         arm,cs-dev-assoc = <&etm3>;
  834 
  835                         status = "disabled";
  836                 };
  837 
  838                 etm0: etm@85c000 {
  839                         compatible = "arm,coresight-etm4x", "arm,primecell";
  840                         reg = <0x0085c000 0x1000>;
  841 
  842                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  843                         clock-names = "apb_pclk", "atclk";
  844                         arm,coresight-loses-context-with-cpu;
  845 
  846                         cpu = <&CPU0>;
  847 
  848                         status = "disabled";
  849 
  850                         out-ports {
  851                                 port {
  852                                         etm0_out: endpoint {
  853                                                 remote-endpoint = <&funnel1_in0>;
  854                                         };
  855                                 };
  856                         };
  857                 };
  858 
  859                 etm1: etm@85d000 {
  860                         compatible = "arm,coresight-etm4x", "arm,primecell";
  861                         reg = <0x0085d000 0x1000>;
  862 
  863                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  864                         clock-names = "apb_pclk", "atclk";
  865                         arm,coresight-loses-context-with-cpu;
  866 
  867                         cpu = <&CPU1>;
  868 
  869                         status = "disabled";
  870 
  871                         out-ports {
  872                                 port {
  873                                         etm1_out: endpoint {
  874                                                 remote-endpoint = <&funnel1_in1>;
  875                                         };
  876                                 };
  877                         };
  878                 };
  879 
  880                 etm2: etm@85e000 {
  881                         compatible = "arm,coresight-etm4x", "arm,primecell";
  882                         reg = <0x0085e000 0x1000>;
  883 
  884                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  885                         clock-names = "apb_pclk", "atclk";
  886                         arm,coresight-loses-context-with-cpu;
  887 
  888                         cpu = <&CPU2>;
  889 
  890                         status = "disabled";
  891 
  892                         out-ports {
  893                                 port {
  894                                         etm2_out: endpoint {
  895                                                 remote-endpoint = <&funnel1_in2>;
  896                                         };
  897                                 };
  898                         };
  899                 };
  900 
  901                 etm3: etm@85f000 {
  902                         compatible = "arm,coresight-etm4x", "arm,primecell";
  903                         reg = <0x0085f000 0x1000>;
  904 
  905                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
  906                         clock-names = "apb_pclk", "atclk";
  907                         arm,coresight-loses-context-with-cpu;
  908 
  909                         cpu = <&CPU3>;
  910 
  911                         status = "disabled";
  912 
  913                         out-ports {
  914                                 port {
  915                                         etm3_out: endpoint {
  916                                                 remote-endpoint = <&funnel1_in3>;
  917                                         };
  918                                 };
  919                         };
  920                 };
  921 
  922                 msmgpio: pinctrl@1000000 {
  923                         compatible = "qcom,msm8916-pinctrl";
  924                         reg = <0x01000000 0x300000>;
  925                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  926                         gpio-controller;
  927                         gpio-ranges = <&msmgpio 0 0 122>;
  928                         #gpio-cells = <2>;
  929                         interrupt-controller;
  930                         #interrupt-cells = <2>;
  931                 };
  932 
  933                 gcc: clock-controller@1800000 {
  934                         compatible = "qcom,gcc-msm8916";
  935                         #clock-cells = <1>;
  936                         #reset-cells = <1>;
  937                         #power-domain-cells = <1>;
  938                         reg = <0x01800000 0x80000>;
  939                 };
  940 
  941                 tcsr_mutex: hwlock@1905000 {
  942                         compatible = "qcom,tcsr-mutex";
  943                         reg = <0x01905000 0x20000>;
  944                         #hwlock-cells = <1>;
  945                 };
  946 
  947                 tcsr: syscon@1937000 {
  948                         compatible = "qcom,tcsr-msm8916", "syscon";
  949                         reg = <0x01937000 0x30000>;
  950                 };
  951 
  952                 mdss: mdss@1a00000 {
  953                         status = "disabled";
  954                         compatible = "qcom,mdss";
  955                         reg = <0x01a00000 0x1000>,
  956                               <0x01ac8000 0x3000>;
  957                         reg-names = "mdss_phys", "vbif_phys";
  958 
  959                         power-domains = <&gcc MDSS_GDSC>;
  960 
  961                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
  962                                  <&gcc GCC_MDSS_AXI_CLK>,
  963                                  <&gcc GCC_MDSS_VSYNC_CLK>;
  964                         clock-names = "iface",
  965                                       "bus",
  966                                       "vsync";
  967 
  968                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  969 
  970                         interrupt-controller;
  971                         #interrupt-cells = <1>;
  972 
  973                         #address-cells = <1>;
  974                         #size-cells = <1>;
  975                         ranges;
  976 
  977                         mdp: mdp@1a01000 {
  978                                 compatible = "qcom,mdp5";
  979                                 reg = <0x01a01000 0x89000>;
  980                                 reg-names = "mdp_phys";
  981 
  982                                 interrupt-parent = <&mdss>;
  983                                 interrupts = <0>;
  984 
  985                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
  986                                          <&gcc GCC_MDSS_AXI_CLK>,
  987                                          <&gcc GCC_MDSS_MDP_CLK>,
  988                                          <&gcc GCC_MDSS_VSYNC_CLK>;
  989                                 clock-names = "iface",
  990                                               "bus",
  991                                               "core",
  992                                               "vsync";
  993 
  994                                 iommus = <&apps_iommu 4>;
  995 
  996                                 ports {
  997                                         #address-cells = <1>;
  998                                         #size-cells = <0>;
  999 
 1000                                         port@0 {
 1001                                                 reg = <0>;
 1002                                                 mdp5_intf1_out: endpoint {
 1003                                                         remote-endpoint = <&dsi0_in>;
 1004                                                 };
 1005                                         };
 1006                                 };
 1007                         };
 1008 
 1009                         dsi0: dsi@1a98000 {
 1010                                 compatible = "qcom,mdss-dsi-ctrl";
 1011                                 reg = <0x01a98000 0x25c>;
 1012                                 reg-names = "dsi_ctrl";
 1013 
 1014                                 interrupt-parent = <&mdss>;
 1015                                 interrupts = <4>;
 1016 
 1017                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 1018                                                   <&gcc PCLK0_CLK_SRC>;
 1019                                 assigned-clock-parents = <&dsi_phy0 0>,
 1020                                                          <&dsi_phy0 1>;
 1021 
 1022                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 1023                                          <&gcc GCC_MDSS_AHB_CLK>,
 1024                                          <&gcc GCC_MDSS_AXI_CLK>,
 1025                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 1026                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 1027                                          <&gcc GCC_MDSS_ESC0_CLK>;
 1028                                 clock-names = "mdp_core",
 1029                                               "iface",
 1030                                               "bus",
 1031                                               "byte",
 1032                                               "pixel",
 1033                                               "core";
 1034                                 phys = <&dsi_phy0>;
 1035                                 phy-names = "dsi-phy";
 1036 
 1037                                 #address-cells = <1>;
 1038                                 #size-cells = <0>;
 1039 
 1040                                 ports {
 1041                                         #address-cells = <1>;
 1042                                         #size-cells = <0>;
 1043 
 1044                                         port@0 {
 1045                                                 reg = <0>;
 1046                                                 dsi0_in: endpoint {
 1047                                                         remote-endpoint = <&mdp5_intf1_out>;
 1048                                                 };
 1049                                         };
 1050 
 1051                                         port@1 {
 1052                                                 reg = <1>;
 1053                                                 dsi0_out: endpoint {
 1054                                                 };
 1055                                         };
 1056                                 };
 1057                         };
 1058 
 1059                         dsi_phy0: dsi-phy@1a98300 {
 1060                                 compatible = "qcom,dsi-phy-28nm-lp";
 1061                                 reg = <0x01a98300 0xd4>,
 1062                                       <0x01a98500 0x280>,
 1063                                       <0x01a98780 0x30>;
 1064                                 reg-names = "dsi_pll",
 1065                                             "dsi_phy",
 1066                                             "dsi_phy_regulator";
 1067 
 1068                                 #clock-cells = <1>;
 1069                                 #phy-cells = <0>;
 1070 
 1071                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 1072                                          <&xo_board>;
 1073                                 clock-names = "iface", "ref";
 1074                         };
 1075                 };
 1076 
 1077                 camss: camss@1b00000 {
 1078                         compatible = "qcom,msm8916-camss";
 1079                         reg = <0x01b0ac00 0x200>,
 1080                                 <0x01b00030 0x4>,
 1081                                 <0x01b0b000 0x200>,
 1082                                 <0x01b00038 0x4>,
 1083                                 <0x01b08000 0x100>,
 1084                                 <0x01b08400 0x100>,
 1085                                 <0x01b0a000 0x500>,
 1086                                 <0x01b00020 0x10>,
 1087                                 <0x01b10000 0x1000>;
 1088                         reg-names = "csiphy0",
 1089                                 "csiphy0_clk_mux",
 1090                                 "csiphy1",
 1091                                 "csiphy1_clk_mux",
 1092                                 "csid0",
 1093                                 "csid1",
 1094                                 "ispif",
 1095                                 "csi_clk_mux",
 1096                                 "vfe0";
 1097                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
 1098                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
 1099                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
 1100                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
 1101                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
 1102                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
 1103                         interrupt-names = "csiphy0",
 1104                                 "csiphy1",
 1105                                 "csid0",
 1106                                 "csid1",
 1107                                 "ispif",
 1108                                 "vfe0";
 1109                         power-domains = <&gcc VFE_GDSC>;
 1110                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
 1111                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
 1112                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
 1113                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
 1114                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
 1115                                 <&gcc GCC_CAMSS_CSI0_CLK>,
 1116                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
 1117                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
 1118                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
 1119                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
 1120                                 <&gcc GCC_CAMSS_CSI1_CLK>,
 1121                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
 1122                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
 1123                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
 1124                                 <&gcc GCC_CAMSS_AHB_CLK>,
 1125                                 <&gcc GCC_CAMSS_VFE0_CLK>,
 1126                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
 1127                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
 1128                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
 1129                         clock-names = "top_ahb",
 1130                                 "ispif_ahb",
 1131                                 "csiphy0_timer",
 1132                                 "csiphy1_timer",
 1133                                 "csi0_ahb",
 1134                                 "csi0",
 1135                                 "csi0_phy",
 1136                                 "csi0_pix",
 1137                                 "csi0_rdi",
 1138                                 "csi1_ahb",
 1139                                 "csi1",
 1140                                 "csi1_phy",
 1141                                 "csi1_pix",
 1142                                 "csi1_rdi",
 1143                                 "ahb",
 1144                                 "vfe0",
 1145                                 "csi_vfe0",
 1146                                 "vfe_ahb",
 1147                                 "vfe_axi";
 1148                         iommus = <&apps_iommu 3>;
 1149                         status = "disabled";
 1150                         ports {
 1151                                 #address-cells = <1>;
 1152                                 #size-cells = <0>;
 1153                         };
 1154                 };
 1155 
 1156                 cci: cci@1b0c000 {
 1157                         compatible = "qcom,msm8916-cci";
 1158                         #address-cells = <1>;
 1159                         #size-cells = <0>;
 1160                         reg = <0x01b0c000 0x1000>;
 1161                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
 1162                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
 1163                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
 1164                                 <&gcc GCC_CAMSS_CCI_CLK>,
 1165                                 <&gcc GCC_CAMSS_AHB_CLK>;
 1166                         clock-names = "camss_top_ahb", "cci_ahb",
 1167                                           "cci", "camss_ahb";
 1168                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
 1169                                           <&gcc GCC_CAMSS_CCI_CLK>;
 1170                         assigned-clock-rates = <80000000>, <19200000>;
 1171                         pinctrl-names = "default";
 1172                         pinctrl-0 = <&cci0_default>;
 1173                         status = "disabled";
 1174 
 1175                         cci_i2c0: i2c-bus@0 {
 1176                                 reg = <0>;
 1177                                 clock-frequency = <400000>;
 1178                                 #address-cells = <1>;
 1179                                 #size-cells = <0>;
 1180                         };
 1181                 };
 1182 
 1183                 gpu@1c00000 {
 1184                         compatible = "qcom,adreno-306.0", "qcom,adreno";
 1185                         reg = <0x01c00000 0x20000>;
 1186                         reg-names = "kgsl_3d0_reg_memory";
 1187                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 1188                         interrupt-names = "kgsl_3d0_irq";
 1189                         clock-names =
 1190                             "core",
 1191                             "iface",
 1192                             "mem",
 1193                             "mem_iface",
 1194                             "alt_mem_iface",
 1195                             "gfx3d";
 1196                         clocks =
 1197                             <&gcc GCC_OXILI_GFX3D_CLK>,
 1198                             <&gcc GCC_OXILI_AHB_CLK>,
 1199                             <&gcc GCC_OXILI_GMEM_CLK>,
 1200                             <&gcc GCC_BIMC_GFX_CLK>,
 1201                             <&gcc GCC_BIMC_GPU_CLK>,
 1202                             <&gcc GFX3D_CLK_SRC>;
 1203                         power-domains = <&gcc OXILI_GDSC>;
 1204                         operating-points-v2 = <&gpu_opp_table>;
 1205                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
 1206 
 1207                         gpu_opp_table: opp-table {
 1208                                 compatible = "operating-points-v2";
 1209 
 1210                                 opp-400000000 {
 1211                                         opp-hz = /bits/ 64 <400000000>;
 1212                                 };
 1213                                 opp-19200000 {
 1214                                         opp-hz = /bits/ 64 <19200000>;
 1215                                 };
 1216                         };
 1217                 };
 1218 
 1219                 venus: video-codec@1d00000 {
 1220                         compatible = "qcom,msm8916-venus";
 1221                         reg = <0x01d00000 0xff000>;
 1222                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 1223                         power-domains = <&gcc VENUS_GDSC>;
 1224                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
 1225                                  <&gcc GCC_VENUS0_AHB_CLK>,
 1226                                  <&gcc GCC_VENUS0_AXI_CLK>;
 1227                         clock-names = "core", "iface", "bus";
 1228                         iommus = <&apps_iommu 5>;
 1229                         memory-region = <&venus_mem>;
 1230                         status = "okay";
 1231 
 1232                         video-decoder {
 1233                                 compatible = "venus-decoder";
 1234                         };
 1235 
 1236                         video-encoder {
 1237                                 compatible = "venus-encoder";
 1238                         };
 1239                 };
 1240 
 1241                 apps_iommu: iommu@1ef0000 {
 1242                         #address-cells = <1>;
 1243                         #size-cells = <1>;
 1244                         #iommu-cells = <1>;
 1245                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 1246                         ranges = <0 0x01e20000 0x40000>;
 1247                         reg = <0x01ef0000 0x3000>;
 1248                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 1249                                  <&gcc GCC_APSS_TCU_CLK>;
 1250                         clock-names = "iface", "bus";
 1251                         qcom,iommu-secure-id = <17>;
 1252 
 1253                         // vfe:
 1254                         iommu-ctx@3000 {
 1255                                 compatible = "qcom,msm-iommu-v1-sec";
 1256                                 reg = <0x3000 0x1000>;
 1257                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 1258                         };
 1259 
 1260                         // mdp_0:
 1261                         iommu-ctx@4000 {
 1262                                 compatible = "qcom,msm-iommu-v1-ns";
 1263                                 reg = <0x4000 0x1000>;
 1264                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 1265                         };
 1266 
 1267                         // venus_ns:
 1268                         iommu-ctx@5000 {
 1269                                 compatible = "qcom,msm-iommu-v1-sec";
 1270                                 reg = <0x5000 0x1000>;
 1271                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 1272                         };
 1273                 };
 1274 
 1275                 gpu_iommu: iommu@1f08000 {
 1276                         #address-cells = <1>;
 1277                         #size-cells = <1>;
 1278                         #iommu-cells = <1>;
 1279                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 1280                         ranges = <0 0x01f08000 0x10000>;
 1281                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 1282                                  <&gcc GCC_GFX_TCU_CLK>;
 1283                         clock-names = "iface", "bus";
 1284                         qcom,iommu-secure-id = <18>;
 1285 
 1286                         // gfx3d_user:
 1287                         iommu-ctx@1000 {
 1288                                 compatible = "qcom,msm-iommu-v1-ns";
 1289                                 reg = <0x1000 0x1000>;
 1290                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 1291                         };
 1292 
 1293                         // gfx3d_priv:
 1294                         iommu-ctx@2000 {
 1295                                 compatible = "qcom,msm-iommu-v1-ns";
 1296                                 reg = <0x2000 0x1000>;
 1297                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 1298                         };
 1299                 };
 1300 
 1301                 spmi_bus: spmi@200f000 {
 1302                         compatible = "qcom,spmi-pmic-arb";
 1303                         reg = <0x0200f000 0x001000>,
 1304                               <0x02400000 0x400000>,
 1305                               <0x02c00000 0x400000>,
 1306                               <0x03800000 0x200000>,
 1307                               <0x0200a000 0x002100>;
 1308                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 1309                         interrupt-names = "periph_irq";
 1310                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 1311                         qcom,ee = <0>;
 1312                         qcom,channel = <0>;
 1313                         #address-cells = <2>;
 1314                         #size-cells = <0>;
 1315                         interrupt-controller;
 1316                         #interrupt-cells = <4>;
 1317                 };
 1318 
 1319                 bam_dmux_dma: dma-controller@4044000 {
 1320                         compatible = "qcom,bam-v1.7.0";
 1321                         reg = <0x04044000 0x19000>;
 1322                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 1323                         #dma-cells = <1>;
 1324                         qcom,ee = <0>;
 1325 
 1326                         num-channels = <6>;
 1327                         qcom,num-ees = <1>;
 1328                         qcom,powered-remotely;
 1329 
 1330                         status = "disabled";
 1331                 };
 1332 
 1333                 mpss: remoteproc@4080000 {
 1334                         compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
 1335                         reg = <0x04080000 0x100>,
 1336                               <0x04020000 0x040>;
 1337 
 1338                         reg-names = "qdsp6", "rmb";
 1339 
 1340                         interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
 1341                                               <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1342                                               <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1343                                               <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1344                                               <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 1345                         interrupt-names = "wdog", "fatal", "ready",
 1346                                           "handover", "stop-ack";
 1347 
 1348                         power-domains = <&rpmpd MSM8916_VDDCX>,
 1349                                         <&rpmpd MSM8916_VDDMX>;
 1350                         power-domain-names = "cx", "mx";
 1351 
 1352                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 1353                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
 1354                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 1355                                  <&xo_board>;
 1356                         clock-names = "iface", "bus", "mem", "xo";
 1357 
 1358                         qcom,smem-states = <&hexagon_smp2p_out 0>;
 1359                         qcom,smem-state-names = "stop";
 1360 
 1361                         resets = <&scm 0>;
 1362                         reset-names = "mss_restart";
 1363 
 1364                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
 1365 
 1366                         status = "disabled";
 1367 
 1368                         mba {
 1369                                 memory-region = <&mba_mem>;
 1370                         };
 1371 
 1372                         mpss {
 1373                                 memory-region = <&mpss_mem>;
 1374                         };
 1375 
 1376                         bam_dmux: bam-dmux {
 1377                                 compatible = "qcom,bam-dmux";
 1378 
 1379                                 interrupt-parent = <&hexagon_smsm>;
 1380                                 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>;
 1381                                 interrupt-names = "pc", "pc-ack";
 1382 
 1383                                 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
 1384                                 qcom,smem-state-names = "pc", "pc-ack";
 1385 
 1386                                 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>;
 1387                                 dma-names = "tx", "rx";
 1388 
 1389                                 status = "disabled";
 1390                         };
 1391 
 1392                         smd-edge {
 1393                                 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
 1394 
 1395                                 qcom,smd-edge = <0>;
 1396                                 qcom,ipc = <&apcs 8 12>;
 1397                                 qcom,remote-pid = <1>;
 1398 
 1399                                 label = "hexagon";
 1400 
 1401                                 fastrpc {
 1402                                         compatible = "qcom,fastrpc";
 1403                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
 1404                                         label = "adsp";
 1405                                         qcom,non-secure-domain;
 1406 
 1407                                         #address-cells = <1>;
 1408                                         #size-cells = <0>;
 1409 
 1410                                         cb@1 {
 1411                                                 compatible = "qcom,fastrpc-compute-cb";
 1412                                                 reg = <1>;
 1413                                         };
 1414                                 };
 1415                         };
 1416                 };
 1417 
 1418                 sound: sound@7702000 {
 1419                         status = "disabled";
 1420                         compatible = "qcom,apq8016-sbc-sndcard";
 1421                         reg = <0x07702000 0x4>, <0x07702004 0x4>;
 1422                         reg-names = "mic-iomux", "spkr-iomux";
 1423                 };
 1424 
 1425                 lpass: audio-controller@7708000 {
 1426                         status = "disabled";
 1427                         compatible = "qcom,lpass-cpu-apq8016";
 1428 
 1429                         /*
 1430                          * Note: Unlike the name would suggest, the SEC_I2S_CLK
 1431                          * is actually only used by Tertiary MI2S while
 1432                          * Primary/Secondary MI2S both use the PRI_I2S_CLK.
 1433                          */
 1434                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 1435                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 1436                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 1437                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 1438                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 1439                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 1440                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 1441 
 1442                         clock-names = "ahbix-clk",
 1443                                         "pcnoc-mport-clk",
 1444                                         "pcnoc-sway-clk",
 1445                                         "mi2s-bit-clk0",
 1446                                         "mi2s-bit-clk1",
 1447                                         "mi2s-bit-clk2",
 1448                                         "mi2s-bit-clk3";
 1449                         #sound-dai-cells = <1>;
 1450 
 1451                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 1452                         interrupt-names = "lpass-irq-lpaif";
 1453                         reg = <0x07708000 0x10000>;
 1454                         reg-names = "lpass-lpaif";
 1455 
 1456                         #address-cells = <1>;
 1457                         #size-cells = <0>;
 1458                 };
 1459 
 1460                 lpass_codec: audio-codec@771c000 {
 1461                         compatible = "qcom,msm8916-wcd-digital-codec";
 1462                         reg = <0x0771c000 0x400>;
 1463                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 1464                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
 1465                         clock-names = "ahbix-clk", "mclk";
 1466                         #sound-dai-cells = <1>;
 1467                 };
 1468 
 1469                 sdhc_1: mmc@7824000 {
 1470                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
 1471                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 1472                         reg-names = "hc_mem", "core_mem";
 1473 
 1474                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 1475                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 1476                         interrupt-names = "hc_irq", "pwr_irq";
 1477                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 1478                                  <&gcc GCC_SDCC1_APPS_CLK>,
 1479                                  <&xo_board>;
 1480                         clock-names = "iface", "core", "xo";
 1481                         mmc-ddr-1_8v;
 1482                         bus-width = <8>;
 1483                         non-removable;
 1484                         status = "disabled";
 1485                 };
 1486 
 1487                 sdhc_2: mmc@7864000 {
 1488                         compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";
 1489                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 1490                         reg-names = "hc_mem", "core_mem";
 1491 
 1492                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 1493                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 1494                         interrupt-names = "hc_irq", "pwr_irq";
 1495                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 1496                                  <&gcc GCC_SDCC2_APPS_CLK>,
 1497                                  <&xo_board>;
 1498                         clock-names = "iface", "core", "xo";
 1499                         bus-width = <4>;
 1500                         status = "disabled";
 1501                 };
 1502 
 1503                 blsp_dma: dma-controller@7884000 {
 1504                         compatible = "qcom,bam-v1.7.0";
 1505                         reg = <0x07884000 0x23000>;
 1506                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 1507                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 1508                         clock-names = "bam_clk";
 1509                         #dma-cells = <1>;
 1510                         qcom,ee = <0>;
 1511                         status = "disabled";
 1512                 };
 1513 
 1514                 blsp1_uart1: serial@78af000 {
 1515                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 1516                         reg = <0x078af000 0x200>;
 1517                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 1518                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 1519                         clock-names = "core", "iface";
 1520                         dmas = <&blsp_dma 0>, <&blsp_dma 1>;
 1521                         dma-names = "tx", "rx";
 1522                         pinctrl-names = "default", "sleep";
 1523                         pinctrl-0 = <&blsp1_uart1_default>;
 1524                         pinctrl-1 = <&blsp1_uart1_sleep>;
 1525                         status = "disabled";
 1526                 };
 1527 
 1528                 blsp1_uart2: serial@78b0000 {
 1529                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 1530                         reg = <0x078b0000 0x200>;
 1531                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 1532                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 1533                         clock-names = "core", "iface";
 1534                         dmas = <&blsp_dma 2>, <&blsp_dma 3>;
 1535                         dma-names = "tx", "rx";
 1536                         pinctrl-names = "default", "sleep";
 1537                         pinctrl-0 = <&blsp1_uart2_default>;
 1538                         pinctrl-1 = <&blsp1_uart2_sleep>;
 1539                         status = "disabled";
 1540                 };
 1541 
 1542                 blsp_i2c1: i2c@78b5000 {
 1543                         compatible = "qcom,i2c-qup-v2.2.1";
 1544                         reg = <0x078b5000 0x500>;
 1545                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 1546                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
 1547                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1548                         clock-names = "core", "iface";
 1549                         pinctrl-names = "default", "sleep";
 1550                         pinctrl-0 = <&i2c1_default>;
 1551                         pinctrl-1 = <&i2c1_sleep>;
 1552                         #address-cells = <1>;
 1553                         #size-cells = <0>;
 1554                         status = "disabled";
 1555                 };
 1556 
 1557                 blsp_spi1: spi@78b5000 {
 1558                         compatible = "qcom,spi-qup-v2.2.1";
 1559                         reg = <0x078b5000 0x500>;
 1560                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 1561                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 1562                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1563                         clock-names = "core", "iface";
 1564                         dmas = <&blsp_dma 4>, <&blsp_dma 5>;
 1565                         dma-names = "tx", "rx";
 1566                         pinctrl-names = "default", "sleep";
 1567                         pinctrl-0 = <&spi1_default>;
 1568                         pinctrl-1 = <&spi1_sleep>;
 1569                         #address-cells = <1>;
 1570                         #size-cells = <0>;
 1571                         status = "disabled";
 1572                 };
 1573 
 1574                 blsp_i2c2: i2c@78b6000 {
 1575                         compatible = "qcom,i2c-qup-v2.2.1";
 1576                         reg = <0x078b6000 0x500>;
 1577                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 1578                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 1579                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1580                         clock-names = "core", "iface";
 1581                         pinctrl-names = "default", "sleep";
 1582                         pinctrl-0 = <&i2c2_default>;
 1583                         pinctrl-1 = <&i2c2_sleep>;
 1584                         #address-cells = <1>;
 1585                         #size-cells = <0>;
 1586                         status = "disabled";
 1587                 };
 1588 
 1589                 blsp_spi2: spi@78b6000 {
 1590                         compatible = "qcom,spi-qup-v2.2.1";
 1591                         reg = <0x078b6000 0x500>;
 1592                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 1593                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 1594                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1595                         clock-names = "core", "iface";
 1596                         dmas = <&blsp_dma 6>, <&blsp_dma 7>;
 1597                         dma-names = "tx", "rx";
 1598                         pinctrl-names = "default", "sleep";
 1599                         pinctrl-0 = <&spi2_default>;
 1600                         pinctrl-1 = <&spi2_sleep>;
 1601                         #address-cells = <1>;
 1602                         #size-cells = <0>;
 1603                         status = "disabled";
 1604                 };
 1605 
 1606                 blsp_i2c3: i2c@78b7000 {
 1607                         compatible = "qcom,i2c-qup-v2.2.1";
 1608                         reg = <0x078b7000 0x500>;
 1609                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 1610                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 1611                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1612                         clock-names = "core", "iface";
 1613                         pinctrl-names = "default", "sleep";
 1614                         pinctrl-0 = <&i2c3_default>;
 1615                         pinctrl-1 = <&i2c3_sleep>;
 1616                         #address-cells = <1>;
 1617                         #size-cells = <0>;
 1618                         status = "disabled";
 1619                 };
 1620 
 1621                 blsp_spi3: spi@78b7000 {
 1622                         compatible = "qcom,spi-qup-v2.2.1";
 1623                         reg = <0x078b7000 0x500>;
 1624                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 1625                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 1626                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1627                         clock-names = "core", "iface";
 1628                         dmas = <&blsp_dma 8>, <&blsp_dma 9>;
 1629                         dma-names = "tx", "rx";
 1630                         pinctrl-names = "default", "sleep";
 1631                         pinctrl-0 = <&spi3_default>;
 1632                         pinctrl-1 = <&spi3_sleep>;
 1633                         #address-cells = <1>;
 1634                         #size-cells = <0>;
 1635                         status = "disabled";
 1636                 };
 1637 
 1638                 blsp_i2c4: i2c@78b8000 {
 1639                         compatible = "qcom,i2c-qup-v2.2.1";
 1640                         reg = <0x078b8000 0x500>;
 1641                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 1642                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 1643                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1644                         clock-names = "core", "iface";
 1645                         pinctrl-names = "default", "sleep";
 1646                         pinctrl-0 = <&i2c4_default>;
 1647                         pinctrl-1 = <&i2c4_sleep>;
 1648                         #address-cells = <1>;
 1649                         #size-cells = <0>;
 1650                         status = "disabled";
 1651                 };
 1652 
 1653                 blsp_spi4: spi@78b8000 {
 1654                         compatible = "qcom,spi-qup-v2.2.1";
 1655                         reg = <0x078b8000 0x500>;
 1656                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 1657                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 1658                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1659                         clock-names = "core", "iface";
 1660                         dmas = <&blsp_dma 10>, <&blsp_dma 11>;
 1661                         dma-names = "tx", "rx";
 1662                         pinctrl-names = "default", "sleep";
 1663                         pinctrl-0 = <&spi4_default>;
 1664                         pinctrl-1 = <&spi4_sleep>;
 1665                         #address-cells = <1>;
 1666                         #size-cells = <0>;
 1667                         status = "disabled";
 1668                 };
 1669 
 1670                 blsp_i2c5: i2c@78b9000 {
 1671                         compatible = "qcom,i2c-qup-v2.2.1";
 1672                         reg = <0x078b9000 0x500>;
 1673                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 1674                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 1675                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1676                         clock-names = "core", "iface";
 1677                         pinctrl-names = "default", "sleep";
 1678                         pinctrl-0 = <&i2c5_default>;
 1679                         pinctrl-1 = <&i2c5_sleep>;
 1680                         #address-cells = <1>;
 1681                         #size-cells = <0>;
 1682                         status = "disabled";
 1683                 };
 1684 
 1685                 blsp_spi5: spi@78b9000 {
 1686                         compatible = "qcom,spi-qup-v2.2.1";
 1687                         reg = <0x078b9000 0x500>;
 1688                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 1689                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 1690                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1691                         clock-names = "core", "iface";
 1692                         dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 1693                         dma-names = "tx", "rx";
 1694                         pinctrl-names = "default", "sleep";
 1695                         pinctrl-0 = <&spi5_default>;
 1696                         pinctrl-1 = <&spi5_sleep>;
 1697                         #address-cells = <1>;
 1698                         #size-cells = <0>;
 1699                         status = "disabled";
 1700                 };
 1701 
 1702                 blsp_i2c6: i2c@78ba000 {
 1703                         compatible = "qcom,i2c-qup-v2.2.1";
 1704                         reg = <0x078ba000 0x500>;
 1705                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 1706                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 1707                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1708                         clock-names = "core", "iface";
 1709                         pinctrl-names = "default", "sleep";
 1710                         pinctrl-0 = <&i2c6_default>;
 1711                         pinctrl-1 = <&i2c6_sleep>;
 1712                         #address-cells = <1>;
 1713                         #size-cells = <0>;
 1714                         status = "disabled";
 1715                 };
 1716 
 1717                 blsp_spi6: spi@78ba000 {
 1718                         compatible = "qcom,spi-qup-v2.2.1";
 1719                         reg = <0x078ba000 0x500>;
 1720                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 1721                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 1722                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1723                         clock-names = "core", "iface";
 1724                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
 1725                         dma-names = "tx", "rx";
 1726                         pinctrl-names = "default", "sleep";
 1727                         pinctrl-0 = <&spi6_default>;
 1728                         pinctrl-1 = <&spi6_sleep>;
 1729                         #address-cells = <1>;
 1730                         #size-cells = <0>;
 1731                         status = "disabled";
 1732                 };
 1733 
 1734                 usb: usb@78d9000 {
 1735                         compatible = "qcom,ci-hdrc";
 1736                         reg = <0x078d9000 0x200>,
 1737                               <0x078d9200 0x200>;
 1738                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 1739                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 1740                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 1741                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 1742                         clock-names = "iface", "core";
 1743                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 1744                         assigned-clock-rates = <80000000>;
 1745                         resets = <&gcc GCC_USB_HS_BCR>;
 1746                         reset-names = "core";
 1747                         phy_type = "ulpi";
 1748                         dr_mode = "otg";
 1749                         hnp-disable;
 1750                         srp-disable;
 1751                         adp-disable;
 1752                         ahb-burst-config = <0>;
 1753                         phy-names = "usb-phy";
 1754                         phys = <&usb_hs_phy>;
 1755                         status = "disabled";
 1756                         #reset-cells = <1>;
 1757 
 1758                         ulpi {
 1759                                 usb_hs_phy: phy {
 1760                                         compatible = "qcom,usb-hs-phy-msm8916",
 1761                                                      "qcom,usb-hs-phy";
 1762                                         #phy-cells = <0>;
 1763                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 1764                                         clock-names = "ref", "sleep";
 1765                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
 1766                                         reset-names = "phy", "por";
 1767                                         qcom,init-seq = /bits/ 8 <0x0 0x44>,
 1768                                                                  <0x1 0x6b>,
 1769                                                                  <0x2 0x24>,
 1770                                                                  <0x3 0x13>;
 1771                                 };
 1772                         };
 1773                 };
 1774 
 1775                 pronto: remoteproc@a21b000 {
 1776                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
 1777                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
 1778                         reg-names = "ccu", "dxe", "pmu";
 1779 
 1780                         memory-region = <&wcnss_mem>;
 1781 
 1782                         interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
 1783                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1784                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1785                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1786                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 1787                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 1788 
 1789                         power-domains = <&rpmpd MSM8916_VDDCX>,
 1790                                         <&rpmpd MSM8916_VDDMX>;
 1791                         power-domain-names = "cx", "mx";
 1792 
 1793                         qcom,smem-states = <&wcnss_smp2p_out 0>;
 1794                         qcom,smem-state-names = "stop";
 1795 
 1796                         pinctrl-names = "default";
 1797                         pinctrl-0 = <&wcnss_pin_a>;
 1798 
 1799                         status = "disabled";
 1800 
 1801                         iris {
 1802                                 compatible = "qcom,wcn3620";
 1803 
 1804                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
 1805                                 clock-names = "xo";
 1806                         };
 1807 
 1808                         smd-edge {
 1809                                 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
 1810 
 1811                                 qcom,ipc = <&apcs 8 17>;
 1812                                 qcom,smd-edge = <6>;
 1813                                 qcom,remote-pid = <4>;
 1814 
 1815                                 label = "pronto";
 1816 
 1817                                 wcnss_ctrl: wcnss {
 1818                                         compatible = "qcom,wcnss";
 1819                                         qcom,smd-channels = "WCNSS_CTRL";
 1820 
 1821                                         qcom,mmio = <&pronto>;
 1822 
 1823                                         bluetooth {
 1824                                                 compatible = "qcom,wcnss-bt";
 1825                                         };
 1826 
 1827                                         wifi {
 1828                                                 compatible = "qcom,wcnss-wlan";
 1829 
 1830                                                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 1831                                                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 1832                                                 interrupt-names = "tx", "rx";
 1833 
 1834                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
 1835                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
 1836                                         };
 1837                                 };
 1838                         };
 1839                 };
 1840 
 1841                 intc: interrupt-controller@b000000 {
 1842                         compatible = "qcom,msm-qgic2";
 1843                         interrupt-controller;
 1844                         #interrupt-cells = <3>;
 1845                         reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>,
 1846                               <0x0b001000 0x1000>, <0x0b004000 0x2000>;
 1847                         interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 1848                 };
 1849 
 1850                 apcs: mailbox@b011000 {
 1851                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
 1852                         reg = <0x0b011000 0x1000>;
 1853                         #mbox-cells = <1>;
 1854                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
 1855                         clock-names = "pll", "aux";
 1856                         #clock-cells = <0>;
 1857                 };
 1858 
 1859                 a53pll: clock@b016000 {
 1860                         compatible = "qcom,msm8916-a53pll";
 1861                         reg = <0x0b016000 0x40>;
 1862                         #clock-cells = <0>;
 1863                         clocks = <&xo_board>;
 1864                         clock-names = "xo";
 1865                 };
 1866 
 1867                 timer@b020000 {
 1868                         #address-cells = <1>;
 1869                         #size-cells = <1>;
 1870                         ranges;
 1871                         compatible = "arm,armv7-timer-mem";
 1872                         reg = <0x0b020000 0x1000>;
 1873                         clock-frequency = <19200000>;
 1874 
 1875                         frame@b021000 {
 1876                                 frame-number = <0>;
 1877                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 1878                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 1879                                 reg = <0x0b021000 0x1000>,
 1880                                       <0x0b022000 0x1000>;
 1881                         };
 1882 
 1883                         frame@b023000 {
 1884                                 frame-number = <1>;
 1885                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 1886                                 reg = <0x0b023000 0x1000>;
 1887                                 status = "disabled";
 1888                         };
 1889 
 1890                         frame@b024000 {
 1891                                 frame-number = <2>;
 1892                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 1893                                 reg = <0x0b024000 0x1000>;
 1894                                 status = "disabled";
 1895                         };
 1896 
 1897                         frame@b025000 {
 1898                                 frame-number = <3>;
 1899                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 1900                                 reg = <0x0b025000 0x1000>;
 1901                                 status = "disabled";
 1902                         };
 1903 
 1904                         frame@b026000 {
 1905                                 frame-number = <4>;
 1906                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 1907                                 reg = <0x0b026000 0x1000>;
 1908                                 status = "disabled";
 1909                         };
 1910 
 1911                         frame@b027000 {
 1912                                 frame-number = <5>;
 1913                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 1914                                 reg = <0x0b027000 0x1000>;
 1915                                 status = "disabled";
 1916                         };
 1917 
 1918                         frame@b028000 {
 1919                                 frame-number = <6>;
 1920                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 1921                                 reg = <0x0b028000 0x1000>;
 1922                                 status = "disabled";
 1923                         };
 1924                 };
 1925 
 1926                 cpu0_acc: power-manager@b088000 {
 1927                         compatible = "qcom,msm8916-acc";
 1928                         reg = <0x0b088000 0x1000>;
 1929                         status = "reserved"; /* Controlled by PSCI firmware */
 1930                 };
 1931 
 1932                 cpu0_saw: power-manager@b089000 {
 1933                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
 1934                         reg = <0x0b089000 0x1000>;
 1935                         status = "reserved"; /* Controlled by PSCI firmware */
 1936                 };
 1937 
 1938                 cpu1_acc: power-manager@b098000 {
 1939                         compatible = "qcom,msm8916-acc";
 1940                         reg = <0x0b098000 0x1000>;
 1941                         status = "reserved"; /* Controlled by PSCI firmware */
 1942                 };
 1943 
 1944                 cpu1_saw: power-manager@b099000 {
 1945                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
 1946                         reg = <0x0b099000 0x1000>;
 1947                         status = "reserved"; /* Controlled by PSCI firmware */
 1948                 };
 1949 
 1950                 cpu2_acc: power-manager@b0a8000 {
 1951                         compatible = "qcom,msm8916-acc";
 1952                         reg = <0x0b0a8000 0x1000>;
 1953                         status = "reserved"; /* Controlled by PSCI firmware */
 1954                 };
 1955 
 1956                 cpu2_saw: power-manager@b0a9000 {
 1957                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
 1958                         reg = <0x0b0a9000 0x1000>;
 1959                         status = "reserved"; /* Controlled by PSCI firmware */
 1960                 };
 1961 
 1962                 cpu3_acc: power-manager@b0b8000 {
 1963                         compatible = "qcom,msm8916-acc";
 1964                         reg = <0x0b0b8000 0x1000>;
 1965                         status = "reserved"; /* Controlled by PSCI firmware */
 1966                 };
 1967 
 1968                 cpu3_saw: power-manager@b0b9000 {
 1969                         compatible = "qcom,msm8916-saw2-v3.0-cpu", "qcom,saw2";
 1970                         reg = <0x0b0b9000 0x1000>;
 1971                         status = "reserved"; /* Controlled by PSCI firmware */
 1972                 };
 1973         };
 1974 
 1975         thermal-zones {
 1976                 cpu0-1-thermal {
 1977                         polling-delay-passive = <250>;
 1978                         polling-delay = <1000>;
 1979 
 1980                         thermal-sensors = <&tsens 5>;
 1981 
 1982                         trips {
 1983                                 cpu0_1_alert0: trip-point0 {
 1984                                         temperature = <75000>;
 1985                                         hysteresis = <2000>;
 1986                                         type = "passive";
 1987                                 };
 1988                                 cpu0_1_crit: cpu_crit {
 1989                                         temperature = <110000>;
 1990                                         hysteresis = <2000>;
 1991                                         type = "critical";
 1992                                 };
 1993                         };
 1994 
 1995                         cooling-maps {
 1996                                 map0 {
 1997                                         trip = <&cpu0_1_alert0>;
 1998                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1999                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 2000                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 2001                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 2002                                 };
 2003                         };
 2004                 };
 2005 
 2006                 cpu2-3-thermal {
 2007                         polling-delay-passive = <250>;
 2008                         polling-delay = <1000>;
 2009 
 2010                         thermal-sensors = <&tsens 4>;
 2011 
 2012                         trips {
 2013                                 cpu2_3_alert0: trip-point0 {
 2014                                         temperature = <75000>;
 2015                                         hysteresis = <2000>;
 2016                                         type = "passive";
 2017                                 };
 2018                                 cpu2_3_crit: cpu_crit {
 2019                                         temperature = <110000>;
 2020                                         hysteresis = <2000>;
 2021                                         type = "critical";
 2022                                 };
 2023                         };
 2024 
 2025                         cooling-maps {
 2026                                 map0 {
 2027                                         trip = <&cpu2_3_alert0>;
 2028                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 2029                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 2030                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 2031                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 2032                                 };
 2033                         };
 2034                 };
 2035 
 2036                 gpu-thermal {
 2037                         polling-delay-passive = <250>;
 2038                         polling-delay = <1000>;
 2039 
 2040                         thermal-sensors = <&tsens 2>;
 2041 
 2042                         trips {
 2043                                 gpu_alert0: trip-point0 {
 2044                                         temperature = <75000>;
 2045                                         hysteresis = <2000>;
 2046                                         type = "passive";
 2047                                 };
 2048                                 gpu_crit: gpu_crit {
 2049                                         temperature = <95000>;
 2050                                         hysteresis = <2000>;
 2051                                         type = "critical";
 2052                                 };
 2053                         };
 2054                 };
 2055 
 2056                 camera-thermal {
 2057                         polling-delay-passive = <250>;
 2058                         polling-delay = <1000>;
 2059 
 2060                         thermal-sensors = <&tsens 1>;
 2061 
 2062                         trips {
 2063                                 cam_alert0: trip-point0 {
 2064                                         temperature = <75000>;
 2065                                         hysteresis = <2000>;
 2066                                         type = "hot";
 2067                                 };
 2068                         };
 2069                 };
 2070 
 2071                 modem-thermal {
 2072                         polling-delay-passive = <250>;
 2073                         polling-delay = <1000>;
 2074 
 2075                         thermal-sensors = <&tsens 0>;
 2076 
 2077                         trips {
 2078                                 modem_alert0: trip-point0 {
 2079                                         temperature = <85000>;
 2080                                         hysteresis = <2000>;
 2081                                         type = "hot";
 2082                                 };
 2083                         };
 2084                 };
 2085 
 2086         };
 2087 
 2088         timer {
 2089                 compatible = "arm,armv8-timer";
 2090                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 2091                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 2092                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 2093                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 2094         };
 2095 };
 2096 
 2097 #include "msm8916-pins.dtsi"
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/msm8916.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/msm8916.dtsi
