msm8953.dtsi

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    1 // SPDX-License-Identifier: BSD-3-Clause
    2 /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
    3 
    4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
    5 #include <dt-bindings/gpio/gpio.h>
    6 #include <dt-bindings/interrupt-controller/arm-gic.h>
    7 #include <dt-bindings/power/qcom-rpmpd.h>
    8 #include <dt-bindings/thermal/thermal.h>
    9 
   10 / {
   11         interrupt-parent = <&intc>;
   12 
   13         #address-cells = <2>;
   14         #size-cells = <2>;
   15 
   16         chosen { };
   17 
   18         clocks {
   19                 sleep_clk: sleep-clk {
   20                         compatible = "fixed-clock";
   21                         #clock-cells = <0>;
   22                         clock-frequency = <32768>;
   23                 };
   24 
   25                 xo_board: xo-board {
   26                         compatible = "fixed-clock";
   27                         #clock-cells = <0>;
   28                         clock-frequency = <19200000>;
   29                         clock-output-names = "xo";
   30                 };
   31         };
   32 
   33         cpus {
   34                 #address-cells = <1>;
   35                 #size-cells = <0>;
   36 
   37                 CPU0: cpu@0 {
   38                         device_type = "cpu";
   39                         compatible = "arm,cortex-a53";
   40                         reg = <0x0>;
   41                         enable-method = "psci";
   42                         capacity-dmips-mhz = <1024>;
   43                         next-level-cache = <&L2_0>;
   44                         #cooling-cells = <2>;
   45 
   46                         l1-icache {
   47                                 compatible = "cache";
   48                         };
   49                         l1-dcache {
   50                                 compatible = "cache";
   51                         };
   52                 };
   53 
   54                 CPU1: cpu@1 {
   55                         device_type = "cpu";
   56                         compatible = "arm,cortex-a53";
   57                         reg = <0x1>;
   58                         enable-method = "psci";
   59                         capacity-dmips-mhz = <1024>;
   60                         next-level-cache = <&L2_0>;
   61                         #cooling-cells = <2>;
   62 
   63                         l1-icache {
   64                                 compatible = "cache";
   65                         };
   66                         l1-dcache {
   67                                 compatible = "cache";
   68                         };
   69                 };
   70 
   71                 CPU2: cpu@2 {
   72                         device_type = "cpu";
   73                         compatible = "arm,cortex-a53";
   74                         reg = <0x2>;
   75                         enable-method = "psci";
   76                         capacity-dmips-mhz = <1024>;
   77                         next-level-cache = <&L2_0>;
   78                         #cooling-cells = <2>;
   79 
   80                         l1-icache {
   81                                 compatible = "cache";
   82                         };
   83                         l1-dcache {
   84                                 compatible = "cache";
   85                         };
   86                 };
   87 
   88                 CPU3: cpu@3 {
   89                         device_type = "cpu";
   90                         compatible = "arm,cortex-a53";
   91                         reg = <0x3>;
   92                         enable-method = "psci";
   93                         capacity-dmips-mhz = <1024>;
   94                         next-level-cache = <&L2_0>;
   95                         #cooling-cells = <2>;
   96 
   97                         l1-icache {
   98                                 compatible = "cache";
   99                         };
  100                         l1-dcache {
  101                                 compatible = "cache";
  102                         };
  103                 };
  104 
  105                 CPU4: cpu@100 {
  106                         device_type = "cpu";
  107                         compatible = "arm,cortex-a53";
  108                         reg = <0x100>;
  109                         enable-method = "psci";
  110                         capacity-dmips-mhz = <1024>;
  111                         next-level-cache = <&L2_1>;
  112                         #cooling-cells = <2>;
  113 
  114                         l1-icache {
  115                                 compatible = "cache";
  116                         };
  117                         l1-dcache {
  118                                 compatible = "cache";
  119                         };
  120                 };
  121 
  122                 CPU5: cpu@101 {
  123                         device_type = "cpu";
  124                         compatible = "arm,cortex-a53";
  125                         reg = <0x101>;
  126                         enable-method = "psci";
  127                         capacity-dmips-mhz = <1024>;
  128                         next-level-cache = <&L2_1>;
  129                         #cooling-cells = <2>;
  130 
  131                         l1-icache {
  132                                 compatible = "cache";
  133                         };
  134                         l1-dcache {
  135                                 compatible = "cache";
  136                         };
  137                 };
  138 
  139                 CPU6: cpu@102 {
  140                         device_type = "cpu";
  141                         compatible = "arm,cortex-a53";
  142                         reg = <0x102>;
  143                         enable-method = "psci";
  144                         capacity-dmips-mhz = <1024>;
  145                         next-level-cache = <&L2_1>;
  146                         #cooling-cells = <2>;
  147 
  148                         l1-icache {
  149                                 compatible = "cache";
  150                         };
  151                         l1-dcache {
  152                                 compatible = "cache";
  153                         };
  154                 };
  155 
  156                 CPU7: cpu@103 {
  157                         device_type = "cpu";
  158                         compatible = "arm,cortex-a53";
  159                         reg = <0x103>;
  160                         enable-method = "psci";
  161                         capacity-dmips-mhz = <1024>;
  162                         next-level-cache = <&L2_1>;
  163                         #cooling-cells = <2>;
  164 
  165                         l1-icache {
  166                                 compatible = "cache";
  167                         };
  168                         l1-dcache {
  169                                 compatible = "cache";
  170                         };
  171                 };
  172 
  173                 cpu-map {
  174                         cluster0 {
  175                                 core0 {
  176                                         cpu = <&CPU0>;
  177                                 };
  178                                 core1 {
  179                                         cpu = <&CPU1>;
  180                                 };
  181                                 core2 {
  182                                         cpu = <&CPU2>;
  183                                 };
  184                                 core3 {
  185                                         cpu = <&CPU3>;
  186                                 };
  187                         };
  188 
  189                         cluster1 {
  190                                 core0 {
  191                                         cpu = <&CPU4>;
  192                                 };
  193                                 core1 {
  194                                         cpu = <&CPU5>;
  195                                 };
  196                                 core2 {
  197                                         cpu = <&CPU6>;
  198                                 };
  199                                 core3 {
  200                                         cpu = <&CPU7>;
  201                                 };
  202                         };
  203                 };
  204 
  205                 L2_0: l2-cache_0 {
  206                         compatible = "cache";
  207                         cache-level = <2>;
  208                 };
  209 
  210                 L2_1: l2-cache_1 {
  211                         compatible = "cache";
  212                         cache-level = <2>;
  213                 };
  214         };
  215 
  216         firmware {
  217                 scm: scm {
  218                         compatible = "qcom,scm-msm8953", "qcom,scm";
  219                         clocks = <&gcc GCC_CRYPTO_CLK>,
  220                                  <&gcc GCC_CRYPTO_AXI_CLK>,
  221                                  <&gcc GCC_CRYPTO_AHB_CLK>;
  222                         clock-names = "core", "bus", "iface";
  223                         #reset-cells = <1>;
  224                 };
  225         };
  226 
  227         memory {
  228                 device_type = "memory";
  229                 /* We expect the bootloader to fill in the reg */
  230                 reg = <0 0 0 0>;
  231         };
  232 
  233         pmu {
  234                 compatible = "arm,cortex-a53-pmu";
  235                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  236         };
  237 
  238         psci {
  239                 compatible = "arm,psci-1.0";
  240                 method = "smc";
  241         };
  242 
  243         reserved-memory {
  244                 #address-cells = <2>;
  245                 #size-cells = <2>;
  246                 ranges;
  247 
  248                 zap_shader_region: memory@81800000 {
  249                         compatible = "shared-dma-pool";
  250                         reg = <0x0 0x81800000 0x0 0x2000>;
  251                         no-map;
  252                 };
  253 
  254                 memory@85b00000 {
  255                         reg = <0x0 0x85b00000 0x0 0x800000>;
  256                         no-map;
  257                 };
  258 
  259                 smem_mem: memory@86300000 {
  260                         compatible = "qcom,smem";
  261                         reg = <0x0 0x86300000 0x0 0x100000>;
  262                         qcom,rpm-msg-ram = <&rpm_msg_ram>;
  263                         hwlocks = <&tcsr_mutex 3>;
  264                         no-map;
  265                 };
  266 
  267                 memory@86400000 {
  268                         reg = <0x0 0x86400000 0x0 0x400000>;
  269                         no-map;
  270                 };
  271 
  272                 mpss_mem: memory@86c00000 {
  273                         reg = <0x0 0x86c00000 0x0 0x6a00000>;
  274                         no-map;
  275                 };
  276 
  277                 adsp_fw_mem: memory@8d600000 {
  278                         reg = <0x0 0x8d600000 0x0 0x1100000>;
  279                         no-map;
  280                 };
  281 
  282                 wcnss_fw_mem: memory@8e700000 {
  283                         reg = <0x0 0x8e700000 0x0 0x700000>;
  284                         no-map;
  285                 };
  286 
  287                 memory@90000000 {
  288                         reg = <0 0x90000000 0 0x1000>;
  289                         no-map;
  290                 };
  291 
  292                 memory@90001000 {
  293                         reg = <0x0 0x90001000 0x0 0x13ff000>;
  294                         no-map;
  295                 };
  296 
  297                 venus_mem: memory@91400000 {
  298                         reg = <0x0 0x91400000 0x0 0x700000>;
  299                         no-map;
  300                 };
  301 
  302                 mba_mem: memory@92000000 {
  303                         reg = <0x0 0x92000000 0x0 0x100000>;
  304                         no-map;
  305                 };
  306 
  307                 memory@f2d00000 {
  308                         compatible = "qcom,rmtfs-mem";
  309                         reg = <0x0 0xf2d00000 0x0 0x180000>;
  310                         no-map;
  311 
  312                         qcom,client-id = <1>;
  313                 };
  314         };
  315 
  316         smd {
  317                 compatible = "qcom,smd";
  318 
  319                 rpm {
  320                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  321                         qcom,ipc = <&apcs 8 0>;
  322                         qcom,smd-edge = <15>;
  323 
  324                         rpm_requests: rpm-requests {
  325                                 compatible = "qcom,rpm-msm8953";
  326                                 qcom,smd-channels = "rpm_requests";
  327 
  328                                 rpmcc: rpmcc {
  329                                         compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
  330                                         clocks = <&xo_board>;
  331                                         clock-names = "xo";
  332                                         #clock-cells = <1>;
  333                                 };
  334 
  335                                 rpmpd: power-controller {
  336                                         compatible = "qcom,msm8953-rpmpd";
  337                                         #power-domain-cells = <1>;
  338                                         operating-points-v2 = <&rpmpd_opp_table>;
  339 
  340                                         clocks = <&xo_board>;
  341                                         clock-names = "ref";
  342 
  343                                         rpmpd_opp_table: opp-table {
  344                                                 compatible = "operating-points-v2";
  345 
  346                                                 rpmpd_opp_ret: opp1 {
  347                                                         opp-level = <RPM_SMD_LEVEL_RETENTION>;
  348                                                 };
  349 
  350                                                 rpmpd_opp_ret_plus: opp2 {
  351                                                         opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
  352                                                 };
  353 
  354                                                 rpmpd_opp_min_svs: opp3 {
  355                                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
  356                                                 };
  357 
  358                                                 rpmpd_opp_low_svs: opp4 {
  359                                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
  360                                                 };
  361 
  362                                                 rpmpd_opp_svs: opp5 {
  363                                                         opp-level = <RPM_SMD_LEVEL_SVS>;
  364                                                 };
  365 
  366                                                 rpmpd_opp_svs_plus: opp6 {
  367                                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
  368                                                 };
  369 
  370                                                 rpmpd_opp_nom: opp7 {
  371                                                         opp-level = <RPM_SMD_LEVEL_NOM>;
  372                                                 };
  373 
  374                                                 rpmpd_opp_nom_plus: opp8 {
  375                                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
  376                                                 };
  377 
  378                                                 rpmpd_opp_turbo: opp9 {
  379                                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
  380                                                 };
  381                                         };
  382                                 };
  383                         };
  384                 };
  385         };
  386 
  387         smsm {
  388                 compatible = "qcom,smsm";
  389 
  390                 #address-cells = <1>;
  391                 #size-cells = <0>;
  392 
  393                 qcom,ipc-1 = <&apcs 8 13>;
  394                 qcom,ipc-3 = <&apcs 8 19>;
  395 
  396                 apps_smsm: apps@0 {
  397                         reg = <0>;
  398 
  399                         #qcom,smem-state-cells = <1>;
  400                 };
  401         };
  402 
  403         soc: soc@0 {
  404                 #address-cells = <1>;
  405                 #size-cells = <1>;
  406                 ranges = <0 0 0 0xffffffff>;
  407                 compatible = "simple-bus";
  408 
  409                 rpm_msg_ram: sram@60000 {
  410                         compatible = "qcom,rpm-msg-ram";
  411                         reg = <0x60000 0x8000>;
  412                 };
  413 
  414                 hsusb_phy: phy@79000 {
  415                         compatible = "qcom,msm8953-qusb2-phy";
  416                         reg = <0x79000 0x180>;
  417                         #phy-cells = <0>;
  418 
  419                         clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
  420                                  <&gcc GCC_QUSB_REF_CLK>;
  421                         clock-names = "cfg_ahb", "ref";
  422 
  423                         qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
  424 
  425                         resets = <&gcc GCC_QUSB2_PHY_BCR>;
  426 
  427                         status = "disabled";
  428                 };
  429 
  430                 rng@e3000 {
  431                         compatible = "qcom,prng";
  432                         reg = <0x000e3000 0x1000>;
  433                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  434                         clock-names = "core";
  435                 };
  436 
  437                 tsens0: thermal-sensor@4a9000 {
  438                         compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
  439                         reg = <0x4a9000 0x1000>, /* TM */
  440                               <0x4a8000 0x1000>; /* SROT */
  441                         #qcom,sensors = <16>;
  442                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
  443                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
  444                         interrupt-names = "uplow", "critical";
  445                         #thermal-sensor-cells = <1>;
  446                 };
  447 
  448                 restart@4ab000 {
  449                         compatible = "qcom,pshold";
  450                         reg = <0x4ab000 0x4>;
  451                 };
  452 
  453                 tlmm: pinctrl@1000000 {
  454                         compatible = "qcom,msm8953-pinctrl";
  455                         reg = <0x1000000 0x300000>;
  456                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  457                         gpio-controller;
  458                         gpio-ranges = <&tlmm 0 0 155>;
  459                         #gpio-cells = <2>;
  460                         interrupt-controller;
  461                         #interrupt-cells = <2>;
  462 
  463                         uart_console_active: uart-console-active-pins {
  464                                 pins = "gpio4", "gpio5";
  465                                 function = "blsp_uart2";
  466                                 drive-strength = <2>;
  467                                 bias-disable;
  468                         };
  469 
  470                         uart_console_sleep: uart-console-sleep-pins {
  471                                 pins = "gpio4", "gpio5";
  472                                 function = "blsp_uart2";
  473                                 drive-strength = <2>;
  474                                 bias-pull-down;
  475                         };
  476 
  477                         sdc1_clk_on: sdc1-clk-on-pins {
  478                                 pins = "sdc1_clk";
  479                                 bias-disable;
  480                                 drive-strength = <16>;
  481                         };
  482 
  483                         sdc1_clk_off: sdc1-clk-off-pins {
  484                                 pins = "sdc1_clk";
  485                                 bias-disable;
  486                                 drive-strength = <2>;
  487                         };
  488 
  489                         sdc1_cmd_on: sdc1-cmd-on-pins {
  490                                 pins = "sdc1_cmd";
  491                                 bias-disable;
  492                                 drive-strength = <10>;
  493                         };
  494 
  495                         sdc1_cmd_off: sdc1-cmd-off-pins {
  496                                 pins = "sdc1_cmd";
  497                                 bias-disable;
  498                                 drive-strength = <2>;
  499                         };
  500 
  501                         sdc1_data_on: sdc1-data-on-pins {
  502                                 pins = "sdc1_data";
  503                                 bias-pull-up;
  504                                 drive-strength = <10>;
  505                         };
  506 
  507                         sdc1_data_off: sdc1-data-off-pins {
  508                                 pins = "sdc1_data";
  509                                 bias-pull-up;
  510                                 drive-strength = <2>;
  511                         };
  512 
  513                         sdc1_rclk_on: sdc1-rclk-on-pins {
  514                                 pins = "sdc1_rclk";
  515                                 bias-pull-down;
  516                         };
  517 
  518                         sdc1_rclk_off: sdc1-rclk-off-pins {
  519                                 pins = "sdc1_rclk";
  520                                 bias-pull-down;
  521                         };
  522 
  523                         sdc2_clk_on: sdc2-clk-on-pins {
  524                                 pins = "sdc2_clk";
  525                                 drive-strength = <16>;
  526                                 bias-disable;
  527                         };
  528 
  529                         sdc2_clk_off: sdc2-clk-off-pins {
  530                                 pins = "sdc2_clk";
  531                                 bias-disable;
  532                                 drive-strength = <2>;
  533                         };
  534 
  535                         sdc2_cmd_on: sdc2-cmd-on-pins {
  536                                 pins = "sdc2_cmd";
  537                                 bias-pull-up;
  538                                 drive-strength = <10>;
  539                         };
  540 
  541                         sdc2_cmd_off: sdc2-cmd-off-pins {
  542                                 pins = "sdc2_cmd";
  543                                 bias-pull-up;
  544                                 drive-strength = <2>;
  545                         };
  546 
  547                         sdc2_data_on: sdc2-data-on-pins {
  548                                 pins = "sdc2_data";
  549                                 bias-pull-up;
  550                                 drive-strength = <10>;
  551                         };
  552 
  553                         sdc2_data_off: sdc2-data-off-pins {
  554                                 pins = "sdc2_data";
  555                                 bias-pull-up;
  556                                 drive-strength = <2>;
  557                         };
  558 
  559                         sdc2_cd_on: cd-on-pins {
  560                                 pins = "gpio133";
  561                                 function = "gpio";
  562                                 drive-strength = <2>;
  563                                 bias-pull-up;
  564                         };
  565 
  566                         sdc2_cd_off: cd-off-pins {
  567                                 pins = "gpio133";
  568                                 function = "gpio";
  569                                 drive-strength = <2>;
  570                                 bias-disable;
  571                         };
  572 
  573                         gpio_key_default: gpio-key-default-pins {
  574                                 pins = "gpio85";
  575                                 function = "gpio";
  576                                 drive-strength = <2>;
  577                                 bias-pull-up;
  578                         };
  579 
  580                         i2c_1_default: i2c-1-default-pins {
  581                                 pins = "gpio2", "gpio3";
  582                                 function = "blsp_i2c1";
  583                                 drive-strength = <2>;
  584                                 bias-disable;
  585                         };
  586 
  587                         i2c_1_sleep: i2c-1-sleep-pins {
  588                                 pins = "gpio2", "gpio3";
  589                                 function = "gpio";
  590                                 drive-strength = <2>;
  591                                 bias-disable;
  592                         };
  593 
  594                         i2c_2_default: i2c-2-default-pins {
  595                                 pins = "gpio6", "gpio7";
  596                                 function = "blsp_i2c2";
  597                                 drive-strength = <2>;
  598                                 bias-disable;
  599                         };
  600 
  601                         i2c_2_sleep: i2c-2-sleep-pins {
  602                                 pins = "gpio6", "gpio7";
  603                                 function = "gpio";
  604                                 drive-strength = <2>;
  605                                 bias-disable;
  606                         };
  607 
  608                         i2c_3_default: i2c-3-default-pins {
  609                                 pins = "gpio10", "gpio11";
  610                                 function = "blsp_i2c3";
  611                                 drive-strength = <2>;
  612                                 bias-disable;
  613                         };
  614 
  615                         i2c_3_sleep: i2c-3-sleep-pins {
  616                                 pins = "gpio10", "gpio11";
  617                                 function = "gpio";
  618                                 drive-strength = <2>;
  619                                 bias-disable;
  620                         };
  621 
  622                         i2c_4_default: i2c-4-default-pins {
  623                                 pins = "gpio14", "gpio15";
  624                                 function = "blsp_i2c4";
  625                                 drive-strength = <2>;
  626                                 bias-disable;
  627                         };
  628 
  629                         i2c_4_sleep: i2c-4-sleep-pins {
  630                                 pins = "gpio14", "gpio15";
  631                                 function = "gpio";
  632                                 drive-strength = <2>;
  633                                 bias-disable;
  634                         };
  635 
  636                         i2c_5_default: i2c-5-default-pins {
  637                                 pins = "gpio18", "gpio19";
  638                                 function = "blsp_i2c5";
  639                                 drive-strength = <2>;
  640                                 bias-disable;
  641                         };
  642 
  643                         i2c_5_sleep: i2c-5-sleep-pins {
  644                                 pins = "gpio18", "gpio19";
  645                                 function = "gpio";
  646                                 drive-strength = <2>;
  647                                 bias-disable;
  648                         };
  649 
  650                         i2c_6_default: i2c-6-default-pins {
  651                                 pins = "gpio22", "gpio23";
  652                                 function = "blsp_i2c6";
  653                                 drive-strength = <2>;
  654                                 bias-disable;
  655                         };
  656 
  657                         i2c_6_sleep: i2c-6-sleep-pins {
  658                                 pins = "gpio22", "gpio23";
  659                                 function = "gpio";
  660                                 drive-strength = <2>;
  661                                 bias-disable;
  662                         };
  663 
  664                         i2c_7_default: i2c-7-default-pins {
  665                                 pins = "gpio135", "gpio136";
  666                                 function = "blsp_i2c7";
  667                                 drive-strength = <2>;
  668                                 bias-disable;
  669                         };
  670 
  671                         i2c_7_sleep: i2c-7-sleep-pins {
  672                                 pins = "gpio135", "gpio136";
  673                                 function = "gpio";
  674                                 drive-strength = <2>;
  675                                 bias-disable;
  676                         };
  677 
  678                         i2c_8_default: i2c-8-default-pins {
  679                                 pins = "gpio98", "gpio99";
  680                                 function = "blsp_i2c8";
  681                                 drive-strength = <2>;
  682                                 bias-disable;
  683                         };
  684 
  685                         i2c_8_sleep: i2c-8-sleep-pins {
  686                                 pins = "gpio98", "gpio99";
  687                                 function = "gpio";
  688                                 drive-strength = <2>;
  689                                 bias-disable;
  690                         };
  691                 };
  692 
  693                 gcc: clock-controller@1800000 {
  694                         compatible = "qcom,gcc-msm8953";
  695                         reg = <0x1800000 0x80000>;
  696                         #clock-cells = <1>;
  697                         #reset-cells = <1>;
  698                         #power-domain-cells = <1>;
  699                         clocks = <&xo_board>,
  700                                  <&sleep_clk>,
  701                                  <0>,
  702                                  <0>,
  703                                  <0>,
  704                                  <0>;
  705                         clock-names = "xo",
  706                                       "sleep",
  707                                       "dsi0pll",
  708                                       "dsi0pllbyte",
  709                                       "dsi1pll",
  710                                       "dsi1pllbyte";
  711                 };
  712 
  713                 tcsr_mutex: hwlock@1905000 {
  714                         compatible = "qcom,tcsr-mutex";
  715                         reg = <0x1905000 0x20000>;
  716                         #hwlock-cells = <1>;
  717                 };
  718 
  719                 tcsr: syscon@1937000 {
  720                         compatible = "qcom,tcsr-msm8953", "syscon";
  721                         reg = <0x1937000 0x30000>;
  722                 };
  723 
  724                 tcsr_phy_clk_scheme_sel: syscon@193f044 {
  725                         compatible = "syscon";
  726                         reg = <0x193f044 0x4>;
  727                 };
  728 
  729                 spmi_bus: spmi@200f000 {
  730                         compatible = "qcom,spmi-pmic-arb";
  731                         reg = <0x200f000 0x1000>,
  732                               <0x2400000 0x800000>,
  733                               <0x2c00000 0x800000>,
  734                               <0x3800000 0x200000>,
  735                               <0x200a000 0x2100>;
  736                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
  737                         interrupt-names = "periph_irq";
  738                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  739                         qcom,ee = <0>;
  740                         qcom,channel = <0>;
  741                         interrupt-controller;
  742 
  743                         #interrupt-cells = <4>;
  744                         #address-cells = <2>;
  745                         #size-cells = <0>;
  746                 };
  747 
  748                 usb3: usb@70f8800 {
  749                         compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
  750                         reg = <0x70f8800 0x400>;
  751                         #address-cells = <1>;
  752                         #size-cells = <1>;
  753                         ranges;
  754 
  755                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  756                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
  757                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
  758 
  759                         clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
  760                                  <&gcc GCC_USB30_MASTER_CLK>,
  761                                  <&gcc GCC_PCNOC_USB3_AXI_CLK>,
  762                                  <&gcc GCC_USB30_SLEEP_CLK>,
  763                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
  764                         clock-names = "cfg_noc",
  765                                       "core",
  766                                       "iface",
  767                                       "sleep",
  768                                       "mock_utmi";
  769 
  770                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
  771                                           <&gcc GCC_USB30_MASTER_CLK>;
  772                         assigned-clock-rates = <19200000>, <133330000>;
  773 
  774                         power-domains = <&gcc USB30_GDSC>;
  775 
  776                         qcom,select-utmi-as-pipe-clk;
  777 
  778                         status = "disabled";
  779 
  780                         usb3_dwc3: usb@7000000 {
  781                                 compatible = "snps,dwc3";
  782                                 reg = <0x07000000 0xcc00>;
  783                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  784                                 phys = <&hsusb_phy>;
  785                                 phy-names = "usb2-phy";
  786 
  787                                 snps,usb2-gadget-lpm-disable;
  788                                 snps,dis-u1-entry-quirk;
  789                                 snps,dis-u2-entry-quirk;
  790                                 snps,is-utmi-l1-suspend;
  791                                 snps,hird-threshold = /bits/ 8 <0x00>;
  792 
  793                                 maximum-speed = "high-speed";
  794                                 phy_mode = "utmi";
  795                         };
  796                 };
  797 
  798                 sdhc_1: mmc@7824900 {
  799                         compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
  800 
  801                         reg = <0x7824900 0x500>, <0x7824000 0x800>;
  802                         reg-names = "hc_mem", "core_mem";
  803 
  804                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  805                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  806                         interrupt-names = "hc_irq", "pwr_irq";
  807 
  808                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
  809                                  <&gcc GCC_SDCC1_APPS_CLK>,
  810                                  <&xo_board>;
  811                         clock-names = "iface", "core", "xo";
  812 
  813                         power-domains = <&rpmpd MSM8953_VDDCX>;
  814                         operating-points-v2 = <&sdhc1_opp_table>;
  815 
  816                         pinctrl-names = "default", "sleep";
  817                         pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
  818                         pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
  819 
  820                         mmc-hs400-1_8v;
  821                         mmc-hs200-1_8v;
  822                         mmc-ddr-1_8v;
  823                         bus-width = <8>;
  824                         non-removable;
  825 
  826                         status = "disabled";
  827 
  828                         sdhc1_opp_table: opp-table-sdhc1 {
  829                                 compatible = "operating-points-v2";
  830 
  831                                 opp-25000000 {
  832                                         opp-hz = /bits/ 64 <25000000>;
  833                                         required-opps = <&rpmpd_opp_low_svs>;
  834                                 };
  835 
  836                                 opp-50000000 {
  837                                         opp-hz = /bits/ 64 <50000000>;
  838                                         required-opps = <&rpmpd_opp_svs>;
  839                                 };
  840 
  841                                 opp-100000000 {
  842                                         opp-hz = /bits/ 64 <100000000>;
  843                                         required-opps = <&rpmpd_opp_svs>;
  844                                 };
  845 
  846                                 opp-192000000 {
  847                                         opp-hz = /bits/ 64 <192000000>;
  848                                         required-opps = <&rpmpd_opp_nom>;
  849                                 };
  850 
  851                                 opp-384000000 {
  852                                         opp-hz = /bits/ 64 <384000000>;
  853                                         required-opps = <&rpmpd_opp_nom>;
  854                                 };
  855                         };
  856                 };
  857 
  858                 sdhc_2: mmc@7864900 {
  859                         compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
  860 
  861                         reg = <0x7864900 0x500>, <0x7864000 0x800>;
  862                         reg-names = "hc_mem", "core_mem";
  863 
  864                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  865                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
  866                         interrupt-names = "hc_irq", "pwr_irq";
  867 
  868                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
  869                                  <&gcc GCC_SDCC2_APPS_CLK>,
  870                                  <&xo_board>;
  871                         clock-names = "iface", "core", "xo";
  872 
  873                         power-domains = <&rpmpd MSM8953_VDDCX>;
  874                         operating-points-v2 = <&sdhc2_opp_table>;
  875 
  876                         pinctrl-names = "default", "sleep";
  877                         pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
  878                         pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
  879 
  880                         bus-width = <4>;
  881 
  882                         status = "disabled";
  883 
  884                         sdhc2_opp_table: opp-table-sdhc2 {
  885                                 compatible = "operating-points-v2";
  886 
  887                                 opp-25000000 {
  888                                         opp-hz = /bits/ 64 <25000000>;
  889                                         required-opps = <&rpmpd_opp_low_svs>;
  890                                 };
  891 
  892                                 opp-50000000 {
  893                                         opp-hz = /bits/ 64 <50000000>;
  894                                         required-opps = <&rpmpd_opp_svs>;
  895                                 };
  896 
  897                                 opp-100000000 {
  898                                         opp-hz = /bits/ 64 <100000000>;
  899                                         required-opps = <&rpmpd_opp_svs>;
  900                                 };
  901 
  902                                 opp-177770000 {
  903                                         opp-hz = /bits/ 64 <177770000>;
  904                                         required-opps = <&rpmpd_opp_nom>;
  905                                 };
  906 
  907                                 opp-200000000 {
  908                                         opp-hz = /bits/ 64 <200000000>;
  909                                         required-opps = <&rpmpd_opp_nom>;
  910                                 };
  911                         };
  912                 };
  913 
  914                 uart_0: serial@78af000 {
  915                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  916                         reg = <0x78af000 0x200>;
  917                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  918                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
  919                                  <&gcc GCC_BLSP1_AHB_CLK>;
  920                         clock-names = "core", "iface";
  921 
  922                         status = "disabled";
  923                 };
  924 
  925                 i2c_1: i2c@78b5000 {
  926                         compatible = "qcom,i2c-qup-v2.2.1";
  927                         reg = <0x78b5000 0x600>;
  928                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  929                         clock-names = "core", "iface";
  930                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
  931                                  <&gcc GCC_BLSP1_AHB_CLK>;
  932 
  933                         pinctrl-names = "default", "sleep";
  934                         pinctrl-0 = <&i2c_1_default>;
  935                         pinctrl-1 = <&i2c_1_sleep>;
  936 
  937                         #address-cells = <1>;
  938                         #size-cells = <0>;
  939 
  940                         status = "disabled";
  941                 };
  942 
  943                 i2c_2: i2c@78b6000 {
  944                         compatible = "qcom,i2c-qup-v2.2.1";
  945                         reg = <0x78b6000 0x600>;
  946                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  947                         clock-names = "core", "iface";
  948                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
  949                                  <&gcc GCC_BLSP1_AHB_CLK>;
  950 
  951                         pinctrl-names = "default", "sleep";
  952                         pinctrl-0 = <&i2c_2_default>;
  953                         pinctrl-1 = <&i2c_2_sleep>;
  954 
  955                         #address-cells = <1>;
  956                         #size-cells = <0>;
  957 
  958                         status = "disabled";
  959                 };
  960 
  961                 i2c_3: i2c@78b7000 {
  962                         compatible = "qcom,i2c-qup-v2.2.1";
  963                         reg = <0x78b7000 0x600>;
  964                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  965                         clock-names = "core", "iface";
  966                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
  967                                  <&gcc GCC_BLSP1_AHB_CLK>;
  968                         pinctrl-names = "default", "sleep";
  969                         pinctrl-0 = <&i2c_3_default>;
  970                         pinctrl-1 = <&i2c_3_sleep>;
  971 
  972                         #address-cells = <1>;
  973                         #size-cells = <0>;
  974 
  975                         status = "disabled";
  976                 };
  977 
  978                 i2c_4: i2c@78b8000 {
  979                         compatible = "qcom,i2c-qup-v2.2.1";
  980                         reg = <0x78b8000 0x600>;
  981                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  982                         clock-names = "core", "iface";
  983                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
  984                                  <&gcc GCC_BLSP1_AHB_CLK>;
  985                         pinctrl-names = "default", "sleep";
  986                         pinctrl-0 = <&i2c_4_default>;
  987                         pinctrl-1 = <&i2c_4_sleep>;
  988 
  989                         #address-cells = <1>;
  990                         #size-cells = <0>;
  991 
  992                         status = "disabled";
  993                 };
  994 
  995                 i2c_5: i2c@7af5000 {
  996                         compatible = "qcom,i2c-qup-v2.2.1";
  997                         reg = <0x7af5000 0x600>;
  998                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
  999                         clock-names = "core", "iface";
 1000                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
 1001                                  <&gcc GCC_BLSP2_AHB_CLK>;
 1002                         pinctrl-names = "default", "sleep";
 1003                         pinctrl-0 = <&i2c_5_default>;
 1004                         pinctrl-1 = <&i2c_5_sleep>;
 1005 
 1006                         #address-cells = <1>;
 1007                         #size-cells = <0>;
 1008 
 1009                         status = "disabled";
 1010                 };
 1011 
 1012                 i2c_6: i2c@7af6000 {
 1013                         compatible = "qcom,i2c-qup-v2.2.1";
 1014                         reg = <0x7af6000 0x600>;
 1015                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 1016                         clock-names = "core", "iface";
 1017                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
 1018                                  <&gcc GCC_BLSP2_AHB_CLK>;
 1019                         pinctrl-names = "default", "sleep";
 1020                         pinctrl-0 = <&i2c_6_default>;
 1021                         pinctrl-1 = <&i2c_6_sleep>;
 1022 
 1023                         #address-cells = <1>;
 1024                         #size-cells = <0>;
 1025 
 1026                         status = "disabled";
 1027                 };
 1028 
 1029                 i2c_7: i2c@7af7000 {
 1030                         compatible = "qcom,i2c-qup-v2.2.1";
 1031                         reg = <0x7af7000 0x600>;
 1032                         interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
 1033                         clock-names = "core", "iface";
 1034                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
 1035                                  <&gcc GCC_BLSP2_AHB_CLK>;
 1036                         pinctrl-names = "default", "sleep";
 1037                         pinctrl-0 = <&i2c_7_default>;
 1038                         pinctrl-1 = <&i2c_7_sleep>;
 1039 
 1040                         #address-cells = <1>;
 1041                         #size-cells = <0>;
 1042 
 1043                         status = "disabled";
 1044                 };
 1045 
 1046                 i2c_8: i2c@7af8000 {
 1047                         compatible = "qcom,i2c-qup-v2.2.1";
 1048                         reg = <0x7af8000 0x600>;
 1049                         interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
 1050                         clock-names = "core", "iface";
 1051                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
 1052                                  <&gcc GCC_BLSP2_AHB_CLK>;
 1053                         pinctrl-names = "default", "sleep";
 1054                         pinctrl-0 = <&i2c_8_default>;
 1055                         pinctrl-1 = <&i2c_8_sleep>;
 1056 
 1057                         #address-cells = <1>;
 1058                         #size-cells = <0>;
 1059 
 1060                         status = "disabled";
 1061                 };
 1062 
 1063                 intc: interrupt-controller@b000000 {
 1064                         compatible = "qcom,msm-qgic2";
 1065                         interrupt-controller;
 1066                         #interrupt-cells = <3>;
 1067                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 1068                 };
 1069 
 1070                 apcs: mailbox@b011000 {
 1071                         compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
 1072                         reg = <0xb011000 0x1000>;
 1073                         #mbox-cells = <1>;
 1074                 };
 1075 
 1076                 timer@b120000 {
 1077                         compatible = "arm,armv7-timer-mem";
 1078                         reg = <0xb120000 0x1000>;
 1079                         #address-cells = <0x01>;
 1080                         #size-cells = <0x01>;
 1081                         ranges;
 1082 
 1083                         frame@b121000 {
 1084                                 frame-number = <0>;
 1085                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 1086                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 1087                                 reg = <0xb121000 0x1000>,
 1088                                       <0xb122000 0x1000>;
 1089                         };
 1090 
 1091                         frame@b123000 {
 1092                                 frame-number = <1>;
 1093                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 1094                                 reg = <0xb123000 0x1000>;
 1095                                 status = "disabled";
 1096                         };
 1097 
 1098                         frame@b124000 {
 1099                                 frame-number = <2>;
 1100                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 1101                                 reg = <0xb124000 0x1000>;
 1102                                 status = "disabled";
 1103                         };
 1104 
 1105                         frame@b125000 {
 1106                                 frame-number = <3>;
 1107                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 1108                                 reg = <0xb125000 0x1000>;
 1109                                 status = "disabled";
 1110                         };
 1111 
 1112                         frame@b126000 {
 1113                                 frame-number = <4>;
 1114                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 1115                                 reg = <0xb126000 0x1000>;
 1116                                 status = "disabled";
 1117                         };
 1118 
 1119                         frame@b127000 {
 1120                                 frame-number = <5>;
 1121                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 1122                                 reg = <0xb127000 0x1000>;
 1123                                 status = "disabled";
 1124                         };
 1125 
 1126                         frame@b128000 {
 1127                                 frame-number = <6>;
 1128                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 1129                                 reg = <0xb128000 0x1000>;
 1130                                 status = "disabled";
 1131                         };
 1132                 };
 1133         };
 1134 
 1135         thermal-zones {
 1136                 cpu0-thermal {
 1137                         polling-delay-passive = <250>;
 1138                         polling-delay = <1000>;
 1139                         thermal-sensors = <&tsens0 9>;
 1140                         trips {
 1141                                 cpu0_alert: trip-point0 {
 1142                                         temperature = <80000>;
 1143                                         hysteresis = <2000>;
 1144                                         type = "passive";
 1145                                 };
 1146                                 cpu0_crit: crit {
 1147                                         temperature = <100000>;
 1148                                         hysteresis = <2000>;
 1149                                         type = "critical";
 1150                                 };
 1151                         };
 1152                         cooling-maps {
 1153                                 map0 {
 1154                                         trip = <&cpu0_alert>;
 1155                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1156                                 };
 1157                         };
 1158                 };
 1159                 cpu1-thermal {
 1160                         polling-delay-passive = <250>;
 1161                         polling-delay = <1000>;
 1162                         thermal-sensors = <&tsens0 10>;
 1163                         trips {
 1164                                 cpu1_alert: trip-point0 {
 1165                                         temperature = <80000>;
 1166                                         hysteresis = <2000>;
 1167                                         type = "passive";
 1168                                 };
 1169                                 cpu1_crit: crit {
 1170                                         temperature = <100000>;
 1171                                         hysteresis = <2000>;
 1172                                         type = "critical";
 1173                                 };
 1174                         };
 1175                         cooling-maps {
 1176                                 map0 {
 1177                                         trip = <&cpu1_alert>;
 1178                                         cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1179                                 };
 1180                         };
 1181                 };
 1182                 cpu2-thermal {
 1183                         polling-delay-passive = <250>;
 1184                         polling-delay = <1000>;
 1185                         thermal-sensors = <&tsens0 11>;
 1186                         trips {
 1187                                 cpu2_alert: trip-point0 {
 1188                                         temperature = <80000>;
 1189                                         hysteresis = <2000>;
 1190                                         type = "passive";
 1191                                 };
 1192                                 cpu2_crit: crit {
 1193                                         temperature = <100000>;
 1194                                         hysteresis = <2000>;
 1195                                         type = "critical";
 1196                                 };
 1197                         };
 1198                         cooling-maps {
 1199                                 map0 {
 1200                                         trip = <&cpu2_alert>;
 1201                                         cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1202                                 };
 1203                         };
 1204                 };
 1205                 cpu3-thermal {
 1206                         polling-delay-passive = <250>;
 1207                         polling-delay = <1000>;
 1208                         thermal-sensors = <&tsens0 12>;
 1209                         trips {
 1210                                 cpu3_alert: trip-point0 {
 1211                                         temperature = <80000>;
 1212                                         hysteresis = <2000>;
 1213                                         type = "passive";
 1214                                 };
 1215                                 cpu3_crit: crit {
 1216                                         temperature = <100000>;
 1217                                         hysteresis = <2000>;
 1218                                         type = "critical";
 1219                                 };
 1220                         };
 1221                         cooling-maps {
 1222                                 map0 {
 1223                                         trip = <&cpu3_alert>;
 1224                                         cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1225                                 };
 1226                         };
 1227                 };
 1228                 cpu4-thermal {
 1229                         polling-delay-passive = <250>;
 1230                         polling-delay = <1000>;
 1231                         thermal-sensors = <&tsens0 4>;
 1232                         trips {
 1233                                 cpu4_alert: trip-point0 {
 1234                                         temperature = <80000>;
 1235                                         hysteresis = <2000>;
 1236                                         type = "passive";
 1237                                 };
 1238                                 cpu4_crit: crit {
 1239                                         temperature = <100000>;
 1240                                         hysteresis = <2000>;
 1241                                         type = "critical";
 1242                                 };
 1243                         };
 1244                         cooling-maps {
 1245                                 map0 {
 1246                                         trip = <&cpu4_alert>;
 1247                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1248                                 };
 1249                         };
 1250                 };
 1251                 cpu5-thermal {
 1252                         polling-delay-passive = <250>;
 1253                         polling-delay = <1000>;
 1254                         thermal-sensors = <&tsens0 5>;
 1255                         trips {
 1256                                 cpu5_alert: trip-point0 {
 1257                                         temperature = <80000>;
 1258                                         hysteresis = <2000>;
 1259                                         type = "passive";
 1260                                 };
 1261                                 cpu5_crit: crit {
 1262                                         temperature = <100000>;
 1263                                         hysteresis = <2000>;
 1264                                         type = "critical";
 1265                                 };
 1266                         };
 1267                         cooling-maps {
 1268                                 map0 {
 1269                                         trip = <&cpu5_alert>;
 1270                                         cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1271                                 };
 1272                         };
 1273                 };
 1274                 cpu6-thermal {
 1275                         polling-delay-passive = <250>;
 1276                         polling-delay = <1000>;
 1277                         thermal-sensors = <&tsens0 6>;
 1278                         trips {
 1279                                 cpu6_alert: trip-point0 {
 1280                                         temperature = <80000>;
 1281                                         hysteresis = <2000>;
 1282                                         type = "passive";
 1283                                 };
 1284                                 cpu6_crit: crit {
 1285                                         temperature = <100000>;
 1286                                         hysteresis = <2000>;
 1287                                         type = "critical";
 1288                                 };
 1289                         };
 1290                         cooling-maps {
 1291                                 map0 {
 1292                                         trip = <&cpu6_alert>;
 1293                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1294                                 };
 1295                         };
 1296                 };
 1297                 cpu7-thermal {
 1298                         polling-delay-passive = <250>;
 1299                         polling-delay = <1000>;
 1300                         thermal-sensors = <&tsens0 7>;
 1301                         trips {
 1302                                 cpu7_alert: trip-point0 {
 1303                                         temperature = <80000>;
 1304                                         hysteresis = <2000>;
 1305                                         type = "passive";
 1306                                 };
 1307                                 cpu7_crit: crit {
 1308                                         temperature = <100000>;
 1309                                         hysteresis = <2000>;
 1310                                         type = "critical";
 1311                                 };
 1312                         };
 1313                         cooling-maps {
 1314                                 map0 {
 1315                                         trip = <&cpu7_alert>;
 1316                                         cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1317                                 };
 1318                         };
 1319                 };
 1320         };
 1321 
 1322         timer {
 1323                 compatible = "arm,armv8-timer";
 1324                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 1325                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 1326                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 1327                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 1328         };
 1329 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/msm8953.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/msm8953.dtsi
