msm8996.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
    3  */
    4 
    5 #include <dt-bindings/interrupt-controller/arm-gic.h>
    6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
    7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
    8 #include <dt-bindings/clock/qcom,rpmcc.h>
    9 #include <dt-bindings/interconnect/qcom,msm8996.h>
   10 #include <dt-bindings/power/qcom-rpmpd.h>
   11 #include <dt-bindings/soc/qcom,apr.h>
   12 #include <dt-bindings/thermal/thermal.h>
   13 
   14 / {
   15         interrupt-parent = <&intc>;
   16 
   17         #address-cells = <2>;
   18         #size-cells = <2>;
   19 
   20         chosen { };
   21 
   22         clocks {
   23                 xo_board: xo-board {
   24                         compatible = "fixed-clock";
   25                         #clock-cells = <0>;
   26                         clock-frequency = <19200000>;
   27                         clock-output-names = "xo_board";
   28                 };
   29 
   30                 sleep_clk: sleep-clk {
   31                         compatible = "fixed-clock";
   32                         #clock-cells = <0>;
   33                         clock-frequency = <32764>;
   34                         clock-output-names = "sleep_clk";
   35                 };
   36         };
   37 
   38         cpus {
   39                 #address-cells = <2>;
   40                 #size-cells = <0>;
   41 
   42                 CPU0: cpu@0 {
   43                         device_type = "cpu";
   44                         compatible = "qcom,kryo";
   45                         reg = <0x0 0x0>;
   46                         enable-method = "psci";
   47                         cpu-idle-states = <&CPU_SLEEP_0>;
   48                         capacity-dmips-mhz = <1024>;
   49                         clocks = <&kryocc 0>;
   50                         operating-points-v2 = <&cluster0_opp>;
   51                         #cooling-cells = <2>;
   52                         next-level-cache = <&L2_0>;
   53                         L2_0: l2-cache {
   54                               compatible = "cache";
   55                               cache-level = <2>;
   56                         };
   57                 };
   58 
   59                 CPU1: cpu@1 {
   60                         device_type = "cpu";
   61                         compatible = "qcom,kryo";
   62                         reg = <0x0 0x1>;
   63                         enable-method = "psci";
   64                         cpu-idle-states = <&CPU_SLEEP_0>;
   65                         capacity-dmips-mhz = <1024>;
   66                         clocks = <&kryocc 0>;
   67                         operating-points-v2 = <&cluster0_opp>;
   68                         #cooling-cells = <2>;
   69                         next-level-cache = <&L2_0>;
   70                 };
   71 
   72                 CPU2: cpu@100 {
   73                         device_type = "cpu";
   74                         compatible = "qcom,kryo";
   75                         reg = <0x0 0x100>;
   76                         enable-method = "psci";
   77                         cpu-idle-states = <&CPU_SLEEP_0>;
   78                         capacity-dmips-mhz = <1024>;
   79                         clocks = <&kryocc 1>;
   80                         operating-points-v2 = <&cluster1_opp>;
   81                         #cooling-cells = <2>;
   82                         next-level-cache = <&L2_1>;
   83                         L2_1: l2-cache {
   84                               compatible = "cache";
   85                               cache-level = <2>;
   86                         };
   87                 };
   88 
   89                 CPU3: cpu@101 {
   90                         device_type = "cpu";
   91                         compatible = "qcom,kryo";
   92                         reg = <0x0 0x101>;
   93                         enable-method = "psci";
   94                         cpu-idle-states = <&CPU_SLEEP_0>;
   95                         capacity-dmips-mhz = <1024>;
   96                         clocks = <&kryocc 1>;
   97                         operating-points-v2 = <&cluster1_opp>;
   98                         #cooling-cells = <2>;
   99                         next-level-cache = <&L2_1>;
  100                 };
  101 
  102                 cpu-map {
  103                         cluster0 {
  104                                 core0 {
  105                                         cpu = <&CPU0>;
  106                                 };
  107 
  108                                 core1 {
  109                                         cpu = <&CPU1>;
  110                                 };
  111                         };
  112 
  113                         cluster1 {
  114                                 core0 {
  115                                         cpu = <&CPU2>;
  116                                 };
  117 
  118                                 core1 {
  119                                         cpu = <&CPU3>;
  120                                 };
  121                         };
  122                 };
  123 
  124                 idle-states {
  125                         entry-method = "psci";
  126 
  127                         CPU_SLEEP_0: cpu-sleep-0 {
  128                                 compatible = "arm,idle-state";
  129                                 idle-state-name = "standalone-power-collapse";
  130                                 arm,psci-suspend-param = <0x00000004>;
  131                                 entry-latency-us = <130>;
  132                                 exit-latency-us = <80>;
  133                                 min-residency-us = <300>;
  134                         };
  135                 };
  136         };
  137 
  138         cluster0_opp: opp-table-cluster0 {
  139                 compatible = "operating-points-v2-kryo-cpu";
  140                 nvmem-cells = <&speedbin_efuse>;
  141                 opp-shared;
  142 
  143                 /* Nominal fmax for now */
  144                 opp-307200000 {
  145                         opp-hz = /bits/ 64 <307200000>;
  146                         opp-supported-hw = <0x77>;
  147                         clock-latency-ns = <200000>;
  148                 };
  149                 opp-422400000 {
  150                         opp-hz = /bits/ 64 <422400000>;
  151                         opp-supported-hw = <0x77>;
  152                         clock-latency-ns = <200000>;
  153                 };
  154                 opp-480000000 {
  155                         opp-hz = /bits/ 64 <480000000>;
  156                         opp-supported-hw = <0x77>;
  157                         clock-latency-ns = <200000>;
  158                 };
  159                 opp-556800000 {
  160                         opp-hz = /bits/ 64 <556800000>;
  161                         opp-supported-hw = <0x77>;
  162                         clock-latency-ns = <200000>;
  163                 };
  164                 opp-652800000 {
  165                         opp-hz = /bits/ 64 <652800000>;
  166                         opp-supported-hw = <0x77>;
  167                         clock-latency-ns = <200000>;
  168                 };
  169                 opp-729600000 {
  170                         opp-hz = /bits/ 64 <729600000>;
  171                         opp-supported-hw = <0x77>;
  172                         clock-latency-ns = <200000>;
  173                 };
  174                 opp-844800000 {
  175                         opp-hz = /bits/ 64 <844800000>;
  176                         opp-supported-hw = <0x77>;
  177                         clock-latency-ns = <200000>;
  178                 };
  179                 opp-960000000 {
  180                         opp-hz = /bits/ 64 <960000000>;
  181                         opp-supported-hw = <0x77>;
  182                         clock-latency-ns = <200000>;
  183                 };
  184                 opp-1036800000 {
  185                         opp-hz = /bits/ 64 <1036800000>;
  186                         opp-supported-hw = <0x77>;
  187                         clock-latency-ns = <200000>;
  188                 };
  189                 opp-1113600000 {
  190                         opp-hz = /bits/ 64 <1113600000>;
  191                         opp-supported-hw = <0x77>;
  192                         clock-latency-ns = <200000>;
  193                 };
  194                 opp-1190400000 {
  195                         opp-hz = /bits/ 64 <1190400000>;
  196                         opp-supported-hw = <0x77>;
  197                         clock-latency-ns = <200000>;
  198                 };
  199                 opp-1228800000 {
  200                         opp-hz = /bits/ 64 <1228800000>;
  201                         opp-supported-hw = <0x77>;
  202                         clock-latency-ns = <200000>;
  203                 };
  204                 opp-1324800000 {
  205                         opp-hz = /bits/ 64 <1324800000>;
  206                         opp-supported-hw = <0x77>;
  207                         clock-latency-ns = <200000>;
  208                 };
  209                 opp-1401600000 {
  210                         opp-hz = /bits/ 64 <1401600000>;
  211                         opp-supported-hw = <0x77>;
  212                         clock-latency-ns = <200000>;
  213                 };
  214                 opp-1478400000 {
  215                         opp-hz = /bits/ 64 <1478400000>;
  216                         opp-supported-hw = <0x77>;
  217                         clock-latency-ns = <200000>;
  218                 };
  219                 opp-1593600000 {
  220                         opp-hz = /bits/ 64 <1593600000>;
  221                         opp-supported-hw = <0x77>;
  222                         clock-latency-ns = <200000>;
  223                 };
  224         };
  225 
  226         cluster1_opp: opp-table-cluster1 {
  227                 compatible = "operating-points-v2-kryo-cpu";
  228                 nvmem-cells = <&speedbin_efuse>;
  229                 opp-shared;
  230 
  231                 /* Nominal fmax for now */
  232                 opp-307200000 {
  233                         opp-hz = /bits/ 64 <307200000>;
  234                         opp-supported-hw = <0x77>;
  235                         clock-latency-ns = <200000>;
  236                 };
  237                 opp-403200000 {
  238                         opp-hz = /bits/ 64 <403200000>;
  239                         opp-supported-hw = <0x77>;
  240                         clock-latency-ns = <200000>;
  241                 };
  242                 opp-480000000 {
  243                         opp-hz = /bits/ 64 <480000000>;
  244                         opp-supported-hw = <0x77>;
  245                         clock-latency-ns = <200000>;
  246                 };
  247                 opp-556800000 {
  248                         opp-hz = /bits/ 64 <556800000>;
  249                         opp-supported-hw = <0x77>;
  250                         clock-latency-ns = <200000>;
  251                 };
  252                 opp-652800000 {
  253                         opp-hz = /bits/ 64 <652800000>;
  254                         opp-supported-hw = <0x77>;
  255                         clock-latency-ns = <200000>;
  256                 };
  257                 opp-729600000 {
  258                         opp-hz = /bits/ 64 <729600000>;
  259                         opp-supported-hw = <0x77>;
  260                         clock-latency-ns = <200000>;
  261                 };
  262                 opp-806400000 {
  263                         opp-hz = /bits/ 64 <806400000>;
  264                         opp-supported-hw = <0x77>;
  265                         clock-latency-ns = <200000>;
  266                 };
  267                 opp-883200000 {
  268                         opp-hz = /bits/ 64 <883200000>;
  269                         opp-supported-hw = <0x77>;
  270                         clock-latency-ns = <200000>;
  271                 };
  272                 opp-940800000 {
  273                         opp-hz = /bits/ 64 <940800000>;
  274                         opp-supported-hw = <0x77>;
  275                         clock-latency-ns = <200000>;
  276                 };
  277                 opp-1036800000 {
  278                         opp-hz = /bits/ 64 <1036800000>;
  279                         opp-supported-hw = <0x77>;
  280                         clock-latency-ns = <200000>;
  281                 };
  282                 opp-1113600000 {
  283                         opp-hz = /bits/ 64 <1113600000>;
  284                         opp-supported-hw = <0x77>;
  285                         clock-latency-ns = <200000>;
  286                 };
  287                 opp-1190400000 {
  288                         opp-hz = /bits/ 64 <1190400000>;
  289                         opp-supported-hw = <0x77>;
  290                         clock-latency-ns = <200000>;
  291                 };
  292                 opp-1248000000 {
  293                         opp-hz = /bits/ 64 <1248000000>;
  294                         opp-supported-hw = <0x77>;
  295                         clock-latency-ns = <200000>;
  296                 };
  297                 opp-1324800000 {
  298                         opp-hz = /bits/ 64 <1324800000>;
  299                         opp-supported-hw = <0x77>;
  300                         clock-latency-ns = <200000>;
  301                 };
  302                 opp-1401600000 {
  303                         opp-hz = /bits/ 64 <1401600000>;
  304                         opp-supported-hw = <0x77>;
  305                         clock-latency-ns = <200000>;
  306                 };
  307                 opp-1478400000 {
  308                         opp-hz = /bits/ 64 <1478400000>;
  309                         opp-supported-hw = <0x77>;
  310                         clock-latency-ns = <200000>;
  311                 };
  312                 opp-1555200000 {
  313                         opp-hz = /bits/ 64 <1555200000>;
  314                         opp-supported-hw = <0x77>;
  315                         clock-latency-ns = <200000>;
  316                 };
  317                 opp-1632000000 {
  318                         opp-hz = /bits/ 64 <1632000000>;
  319                         opp-supported-hw = <0x77>;
  320                         clock-latency-ns = <200000>;
  321                 };
  322                 opp-1708800000 {
  323                         opp-hz = /bits/ 64 <1708800000>;
  324                         opp-supported-hw = <0x77>;
  325                         clock-latency-ns = <200000>;
  326                 };
  327                 opp-1785600000 {
  328                         opp-hz = /bits/ 64 <1785600000>;
  329                         opp-supported-hw = <0x77>;
  330                         clock-latency-ns = <200000>;
  331                 };
  332                 opp-1824000000 {
  333                         opp-hz = /bits/ 64 <1824000000>;
  334                         opp-supported-hw = <0x77>;
  335                         clock-latency-ns = <200000>;
  336                 };
  337                 opp-1920000000 {
  338                         opp-hz = /bits/ 64 <1920000000>;
  339                         opp-supported-hw = <0x77>;
  340                         clock-latency-ns = <200000>;
  341                 };
  342                 opp-1996800000 {
  343                         opp-hz = /bits/ 64 <1996800000>;
  344                         opp-supported-hw = <0x77>;
  345                         clock-latency-ns = <200000>;
  346                 };
  347                 opp-2073600000 {
  348                         opp-hz = /bits/ 64 <2073600000>;
  349                         opp-supported-hw = <0x77>;
  350                         clock-latency-ns = <200000>;
  351                 };
  352                 opp-2150400000 {
  353                         opp-hz = /bits/ 64 <2150400000>;
  354                         opp-supported-hw = <0x77>;
  355                         clock-latency-ns = <200000>;
  356                 };
  357         };
  358 
  359         firmware {
  360                 scm {
  361                         compatible = "qcom,scm-msm8996", "qcom,scm";
  362                         qcom,dload-mode = <&tcsr 0x13000>;
  363                 };
  364         };
  365 
  366         tcsr_mutex: hwlock {
  367                 compatible = "qcom,tcsr-mutex";
  368                 syscon = <&tcsr_mutex_regs 0 0x1000>;
  369                 #hwlock-cells = <1>;
  370         };
  371 
  372         memory@80000000 {
  373                 device_type = "memory";
  374                 /* We expect the bootloader to fill in the reg */
  375                 reg = <0x0 0x80000000 0x0 0x0>;
  376         };
  377 
  378         psci {
  379                 compatible = "arm,psci-1.0";
  380                 method = "smc";
  381         };
  382 
  383         reserved-memory {
  384                 #address-cells = <2>;
  385                 #size-cells = <2>;
  386                 ranges;
  387 
  388                 hyp_mem: memory@85800000 {
  389                         reg = <0x0 0x85800000 0x0 0x600000>;
  390                         no-map;
  391                 };
  392 
  393                 xbl_mem: memory@85e00000 {
  394                         reg = <0x0 0x85e00000 0x0 0x200000>;
  395                         no-map;
  396                 };
  397 
  398                 smem_mem: smem-mem@86000000 {
  399                         reg = <0x0 0x86000000 0x0 0x200000>;
  400                         no-map;
  401                 };
  402 
  403                 tz_mem: memory@86200000 {
  404                         reg = <0x0 0x86200000 0x0 0x2600000>;
  405                         no-map;
  406                 };
  407 
  408                 rmtfs_mem: rmtfs {
  409                         compatible = "qcom,rmtfs-mem";
  410 
  411                         size = <0x0 0x200000>;
  412                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  413                         no-map;
  414 
  415                         qcom,client-id = <1>;
  416                         qcom,vmid = <15>;
  417                 };
  418 
  419                 mpss_mem: mpss@88800000 {
  420                         reg = <0x0 0x88800000 0x0 0x6200000>;
  421                         no-map;
  422                 };
  423 
  424                 adsp_mem: adsp@8ea00000 {
  425                         reg = <0x0 0x8ea00000 0x0 0x1b00000>;
  426                         no-map;
  427                 };
  428 
  429                 slpi_mem: slpi@90500000 {
  430                         reg = <0x0 0x90500000 0x0 0xa00000>;
  431                         no-map;
  432                 };
  433 
  434                 gpu_mem: gpu@90f00000 {
  435                         compatible = "shared-dma-pool";
  436                         reg = <0x0 0x90f00000 0x0 0x100000>;
  437                         no-map;
  438                 };
  439 
  440                 venus_mem: venus@91000000 {
  441                         reg = <0x0 0x91000000 0x0 0x500000>;
  442                         no-map;
  443                 };
  444 
  445                 mba_mem: mba@91500000 {
  446                         reg = <0x0 0x91500000 0x0 0x200000>;
  447                         no-map;
  448                 };
  449         };
  450 
  451         rpm-glink {
  452                 compatible = "qcom,glink-rpm";
  453 
  454                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  455 
  456                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
  457 
  458                 mboxes = <&apcs_glb 0>;
  459 
  460                 rpm_requests: rpm-requests {
  461                         compatible = "qcom,rpm-msm8996";
  462                         qcom,glink-channels = "rpm_requests";
  463 
  464                         rpmcc: qcom,rpmcc {
  465                                 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
  466                                 #clock-cells = <1>;
  467                                 clocks = <&xo_board>;
  468                                 clock-names = "xo";
  469                         };
  470 
  471                         rpmpd: power-controller {
  472                                 compatible = "qcom,msm8996-rpmpd";
  473                                 #power-domain-cells = <1>;
  474                                 operating-points-v2 = <&rpmpd_opp_table>;
  475 
  476                                 rpmpd_opp_table: opp-table {
  477                                         compatible = "operating-points-v2";
  478 
  479                                         rpmpd_opp1: opp1 {
  480                                                 opp-level = <1>;
  481                                         };
  482 
  483                                         rpmpd_opp2: opp2 {
  484                                                 opp-level = <2>;
  485                                         };
  486 
  487                                         rpmpd_opp3: opp3 {
  488                                                 opp-level = <3>;
  489                                         };
  490 
  491                                         rpmpd_opp4: opp4 {
  492                                                 opp-level = <4>;
  493                                         };
  494 
  495                                         rpmpd_opp5: opp5 {
  496                                                 opp-level = <5>;
  497                                         };
  498 
  499                                         rpmpd_opp6: opp6 {
  500                                                 opp-level = <6>;
  501                                         };
  502                                 };
  503                         };
  504                 };
  505         };
  506 
  507         smem {
  508                 compatible = "qcom,smem";
  509                 memory-region = <&smem_mem>;
  510                 hwlocks = <&tcsr_mutex 3>;
  511         };
  512 
  513         smp2p-adsp {
  514                 compatible = "qcom,smp2p";
  515                 qcom,smem = <443>, <429>;
  516 
  517                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
  518 
  519                 mboxes = <&apcs_glb 10>;
  520 
  521                 qcom,local-pid = <0>;
  522                 qcom,remote-pid = <2>;
  523 
  524                 adsp_smp2p_out: master-kernel {
  525                         qcom,entry-name = "master-kernel";
  526                         #qcom,smem-state-cells = <1>;
  527                 };
  528 
  529                 adsp_smp2p_in: slave-kernel {
  530                         qcom,entry-name = "slave-kernel";
  531 
  532                         interrupt-controller;
  533                         #interrupt-cells = <2>;
  534                 };
  535         };
  536 
  537         smp2p-mpss {
  538                 compatible = "qcom,smp2p";
  539                 qcom,smem = <435>, <428>;
  540 
  541                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
  542 
  543                 mboxes = <&apcs_glb 14>;
  544 
  545                 qcom,local-pid = <0>;
  546                 qcom,remote-pid = <1>;
  547 
  548                 mpss_smp2p_out: master-kernel {
  549                         qcom,entry-name = "master-kernel";
  550                         #qcom,smem-state-cells = <1>;
  551                 };
  552 
  553                 mpss_smp2p_in: slave-kernel {
  554                         qcom,entry-name = "slave-kernel";
  555 
  556                         interrupt-controller;
  557                         #interrupt-cells = <2>;
  558                 };
  559         };
  560 
  561         smp2p-slpi {
  562                 compatible = "qcom,smp2p";
  563                 qcom,smem = <481>, <430>;
  564 
  565                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
  566 
  567                 mboxes = <&apcs_glb 26>;
  568 
  569                 qcom,local-pid = <0>;
  570                 qcom,remote-pid = <3>;
  571 
  572                 slpi_smp2p_out: master-kernel {
  573                         qcom,entry-name = "master-kernel";
  574                         #qcom,smem-state-cells = <1>;
  575                 };
  576 
  577                 slpi_smp2p_in: slave-kernel {
  578                         qcom,entry-name = "slave-kernel";
  579 
  580                         interrupt-controller;
  581                         #interrupt-cells = <2>;
  582                 };
  583         };
  584 
  585         soc: soc {
  586                 #address-cells = <1>;
  587                 #size-cells = <1>;
  588                 ranges = <0 0 0 0xffffffff>;
  589                 compatible = "simple-bus";
  590 
  591                 pcie_phy: phy-wrapper@34000 {
  592                         compatible = "qcom,msm8996-qmp-pcie-phy";
  593                         reg = <0x00034000 0x488>;
  594                         #address-cells = <1>;
  595                         #size-cells = <1>;
  596                         ranges = <0x0 0x00034000 0x4000>;
  597 
  598                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
  599                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
  600                                 <&gcc GCC_PCIE_CLKREF_CLK>;
  601                         clock-names = "aux", "cfg_ahb", "ref";
  602 
  603                         resets = <&gcc GCC_PCIE_PHY_BCR>,
  604                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
  605                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
  606                         reset-names = "phy", "common", "cfg";
  607 
  608                         status = "disabled";
  609 
  610                         pciephy_0: phy@1000 {
  611                                 reg = <0x1000 0x130>,
  612                                       <0x1200 0x200>,
  613                                       <0x1400 0x1dc>;
  614 
  615                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
  616                                 clock-names = "pipe0";
  617                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
  618                                 reset-names = "lane0";
  619 
  620                                 #clock-cells = <0>;
  621                                 clock-output-names = "pcie_0_pipe_clk_src";
  622 
  623                                 #phy-cells = <0>;
  624                         };
  625 
  626                         pciephy_1: phy@2000 {
  627                                 reg = <0x2000 0x130>,
  628                                       <0x2200 0x200>,
  629                                       <0x2400 0x1dc>;
  630 
  631                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
  632                                 clock-names = "pipe1";
  633                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
  634                                 reset-names = "lane1";
  635 
  636                                 #clock-cells = <0>;
  637                                 clock-output-names = "pcie_1_pipe_clk_src";
  638 
  639                                 #phy-cells = <0>;
  640                         };
  641 
  642                         pciephy_2: phy@3000 {
  643                                 reg = <0x3000 0x130>,
  644                                       <0x3200 0x200>,
  645                                       <0x3400 0x1dc>;
  646 
  647                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
  648                                 clock-names = "pipe2";
  649                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
  650                                 reset-names = "lane2";
  651 
  652                                 #clock-cells = <0>;
  653                                 clock-output-names = "pcie_2_pipe_clk_src";
  654 
  655                                 #phy-cells = <0>;
  656                         };
  657                 };
  658 
  659                 rpm_msg_ram: sram@68000 {
  660                         compatible = "qcom,rpm-msg-ram";
  661                         reg = <0x00068000 0x6000>;
  662                 };
  663 
  664                 qfprom@74000 {
  665                         compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
  666                         reg = <0x00074000 0x8ff>;
  667                         #address-cells = <1>;
  668                         #size-cells = <1>;
  669 
  670                         qusb2p_hstx_trim: hstx_trim@24e {
  671                                 reg = <0x24e 0x2>;
  672                                 bits = <5 4>;
  673                         };
  674 
  675                         qusb2s_hstx_trim: hstx_trim@24f {
  676                                 reg = <0x24f 0x1>;
  677                                 bits = <1 4>;
  678                         };
  679 
  680                         speedbin_efuse: speedbin@133 {
  681                                 reg = <0x133 0x1>;
  682                                 bits = <5 3>;
  683                         };
  684                 };
  685 
  686                 rng: rng@83000 {
  687                         compatible = "qcom,prng-ee";
  688                         reg = <0x00083000 0x1000>;
  689                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  690                         clock-names = "core";
  691                 };
  692 
  693                 gcc: clock-controller@300000 {
  694                         compatible = "qcom,gcc-msm8996";
  695                         #clock-cells = <1>;
  696                         #reset-cells = <1>;
  697                         #power-domain-cells = <1>;
  698                         reg = <0x00300000 0x90000>;
  699 
  700                         clocks = <&rpmcc RPM_SMD_BB_CLK1>,
  701                                  <&rpmcc RPM_SMD_LN_BB_CLK>,
  702                                  <&sleep_clk>,
  703                                  <&pciephy_0>,
  704                                  <&pciephy_1>,
  705                                  <&pciephy_2>,
  706                                  <&ssusb_phy_0>,
  707                                  <0>, <0>, <0>;
  708                         clock-names = "cxo",
  709                                       "cxo2",
  710                                       "sleep_clk",
  711                                       "pcie_0_pipe_clk_src",
  712                                       "pcie_1_pipe_clk_src",
  713                                       "pcie_2_pipe_clk_src",
  714                                       "usb3_phy_pipe_clk_src",
  715                                       "ufs_rx_symbol_0_clk_src",
  716                                       "ufs_rx_symbol_1_clk_src",
  717                                       "ufs_tx_symbol_0_clk_src";
  718                 };
  719 
  720                 bimc: interconnect@408000 {
  721                         compatible = "qcom,msm8996-bimc";
  722                         reg = <0x00408000 0x5a000>;
  723                         #interconnect-cells = <1>;
  724                         clock-names = "bus", "bus_a";
  725                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
  726                                  <&rpmcc RPM_SMD_BIMC_A_CLK>;
  727                 };
  728 
  729                 tsens0: thermal-sensor@4a9000 {
  730                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
  731                         reg = <0x004a9000 0x1000>, /* TM */
  732                               <0x004a8000 0x1000>; /* SROT */
  733                         #qcom,sensors = <13>;
  734                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
  735                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
  736                         interrupt-names = "uplow", "critical";
  737                         #thermal-sensor-cells = <1>;
  738                 };
  739 
  740                 tsens1: thermal-sensor@4ad000 {
  741                         compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
  742                         reg = <0x004ad000 0x1000>, /* TM */
  743                               <0x004ac000 0x1000>; /* SROT */
  744                         #qcom,sensors = <8>;
  745                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
  746                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
  747                         interrupt-names = "uplow", "critical";
  748                         #thermal-sensor-cells = <1>;
  749                 };
  750 
  751                 cryptobam: dma-controller@644000 {
  752                         compatible = "qcom,bam-v1.7.0";
  753                         reg = <0x00644000 0x24000>;
  754                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  755                         clocks = <&gcc GCC_CE1_CLK>;
  756                         clock-names = "bam_clk";
  757                         #dma-cells = <1>;
  758                         qcom,ee = <0>;
  759                         qcom,controlled-remotely;
  760                 };
  761 
  762                 crypto: crypto@67a000 {
  763                         compatible = "qcom,crypto-v5.4";
  764                         reg = <0x0067a000 0x6000>;
  765                         clocks = <&gcc GCC_CE1_AHB_CLK>,
  766                                  <&gcc GCC_CE1_AXI_CLK>,
  767                                  <&gcc GCC_CE1_CLK>;
  768                         clock-names = "iface", "bus", "core";
  769                         dmas = <&cryptobam 6>, <&cryptobam 7>;
  770                         dma-names = "rx", "tx";
  771                 };
  772 
  773                 cnoc: interconnect@500000 {
  774                         compatible = "qcom,msm8996-cnoc";
  775                         reg = <0x00500000 0x1000>;
  776                         #interconnect-cells = <1>;
  777                         clock-names = "bus", "bus_a";
  778                         clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
  779                                  <&rpmcc RPM_SMD_CNOC_A_CLK>;
  780                 };
  781 
  782                 snoc: interconnect@524000 {
  783                         compatible = "qcom,msm8996-snoc";
  784                         reg = <0x00524000 0x1c000>;
  785                         #interconnect-cells = <1>;
  786                         clock-names = "bus", "bus_a";
  787                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
  788                                  <&rpmcc RPM_SMD_SNOC_A_CLK>;
  789                 };
  790 
  791                 a0noc: interconnect@543000 {
  792                         compatible = "qcom,msm8996-a0noc";
  793                         reg = <0x00543000 0x6000>;
  794                         #interconnect-cells = <1>;
  795                         clock-names = "aggre0_snoc_axi",
  796                                       "aggre0_cnoc_ahb",
  797                                       "aggre0_noc_mpu_cfg";
  798                         clocks = <&gcc GCC_AGGRE0_SNOC_AXI_CLK>,
  799                                  <&gcc GCC_AGGRE0_CNOC_AHB_CLK>,
  800                                  <&gcc GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK>;
  801                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
  802                 };
  803 
  804                 a1noc: interconnect@562000 {
  805                         compatible = "qcom,msm8996-a1noc";
  806                         reg = <0x00562000 0x5000>;
  807                         #interconnect-cells = <1>;
  808                         clock-names = "bus", "bus_a";
  809                         clocks = <&rpmcc RPM_SMD_AGGR1_NOC_CLK>,
  810                                  <&rpmcc RPM_SMD_AGGR1_NOC_A_CLK>;
  811                 };
  812 
  813                 a2noc: interconnect@583000 {
  814                         compatible = "qcom,msm8996-a2noc";
  815                         reg = <0x00583000 0x7000>;
  816                         #interconnect-cells = <1>;
  817                         clock-names = "bus", "bus_a";
  818                         clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
  819                                  <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
  820                 };
  821 
  822                 mnoc: interconnect@5a4000 {
  823                         compatible = "qcom,msm8996-mnoc";
  824                         reg = <0x005a4000 0x1c000>;
  825                         #interconnect-cells = <1>;
  826                         clock-names = "bus", "bus_a", "iface";
  827                         clocks = <&rpmcc RPM_SMD_MMAXI_CLK>,
  828                                  <&rpmcc RPM_SMD_MMAXI_A_CLK>,
  829                                  <&mmcc AHB_CLK_SRC>;
  830                 };
  831 
  832                 pnoc: interconnect@5c0000 {
  833                         compatible = "qcom,msm8996-pnoc";
  834                         reg = <0x005c0000 0x3000>;
  835                         #interconnect-cells = <1>;
  836                         clock-names = "bus", "bus_a";
  837                         clocks = <&rpmcc RPM_SMD_PCNOC_CLK>,
  838                                  <&rpmcc RPM_SMD_PCNOC_A_CLK>;
  839                 };
  840 
  841                 tcsr_mutex_regs: syscon@740000 {
  842                         compatible = "syscon";
  843                         reg = <0x00740000 0x40000>;
  844                 };
  845 
  846                 tcsr: syscon@7a0000 {
  847                         compatible = "qcom,tcsr-msm8996", "syscon";
  848                         reg = <0x007a0000 0x18000>;
  849                 };
  850 
  851                 mmcc: clock-controller@8c0000 {
  852                         compatible = "qcom,mmcc-msm8996";
  853                         #clock-cells = <1>;
  854                         #reset-cells = <1>;
  855                         #power-domain-cells = <1>;
  856                         reg = <0x008c0000 0x40000>;
  857                         clocks = <&xo_board>,
  858                                  <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
  859                                  <&gcc GPLL0>,
  860                                  <&dsi0_phy 1>,
  861                                  <&dsi0_phy 0>,
  862                                  <0>,
  863                                  <0>,
  864                                  <0>;
  865                         clock-names = "xo",
  866                                       "gcc_mmss_noc_cfg_ahb_clk",
  867                                       "gpll0",
  868                                       "dsi0pll",
  869                                       "dsi0pllbyte",
  870                                       "dsi1pll",
  871                                       "dsi1pllbyte",
  872                                       "hdmipll";
  873                         assigned-clocks = <&mmcc MMPLL9_PLL>,
  874                                           <&mmcc MMPLL1_PLL>,
  875                                           <&mmcc MMPLL3_PLL>,
  876                                           <&mmcc MMPLL4_PLL>,
  877                                           <&mmcc MMPLL5_PLL>;
  878                         assigned-clock-rates = <624000000>,
  879                                                <810000000>,
  880                                                <980000000>,
  881                                                <960000000>,
  882                                                <825000000>;
  883                 };
  884 
  885                 mdss: mdss@900000 {
  886                         compatible = "qcom,mdss";
  887 
  888                         reg = <0x00900000 0x1000>,
  889                               <0x009b0000 0x1040>,
  890                               <0x009b8000 0x1040>;
  891                         reg-names = "mdss_phys",
  892                                     "vbif_phys",
  893                                     "vbif_nrt_phys";
  894 
  895                         power-domains = <&mmcc MDSS_GDSC>;
  896                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  897 
  898                         interrupt-controller;
  899                         #interrupt-cells = <1>;
  900 
  901                         clocks = <&mmcc MDSS_AHB_CLK>,
  902                                  <&mmcc MDSS_MDP_CLK>;
  903                         clock-names = "iface", "core";
  904 
  905                         #address-cells = <1>;
  906                         #size-cells = <1>;
  907                         ranges;
  908 
  909                         status = "disabled";
  910 
  911                         mdp: mdp@901000 {
  912                                 compatible = "qcom,mdp5";
  913                                 reg = <0x00901000 0x90000>;
  914                                 reg-names = "mdp_phys";
  915 
  916                                 interrupt-parent = <&mdss>;
  917                                 interrupts = <0>;
  918 
  919                                 clocks = <&mmcc MDSS_AHB_CLK>,
  920                                          <&mmcc MDSS_AXI_CLK>,
  921                                          <&mmcc MDSS_MDP_CLK>,
  922                                          <&mmcc SMMU_MDP_AXI_CLK>,
  923                                          <&mmcc MDSS_VSYNC_CLK>;
  924                                 clock-names = "iface",
  925                                               "bus",
  926                                               "core",
  927                                               "iommu",
  928                                               "vsync";
  929 
  930                                 iommus = <&mdp_smmu 0>;
  931 
  932                                 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
  933                                          <&mmcc MDSS_VSYNC_CLK>;
  934                                 assigned-clock-rates = <300000000>,
  935                                          <19200000>;
  936 
  937                                 interconnects = <&mnoc MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>,
  938                                                 <&mnoc MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>,
  939                                                 <&mnoc MASTER_ROTATOR &bimc SLAVE_EBI_CH0>;
  940                                 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
  941 
  942                                 ports {
  943                                         #address-cells = <1>;
  944                                         #size-cells = <0>;
  945 
  946                                         port@0 {
  947                                                 reg = <0>;
  948                                                 mdp5_intf3_out: endpoint {
  949                                                         remote-endpoint = <&hdmi_in>;
  950                                                 };
  951                                         };
  952 
  953                                         port@1 {
  954                                                 reg = <1>;
  955                                                 mdp5_intf1_out: endpoint {
  956                                                         remote-endpoint = <&dsi0_in>;
  957                                                 };
  958                                         };
  959 
  960                                         port@2 {
  961                                                 reg = <2>;
  962                                                 mdp5_intf2_out: endpoint {
  963                                                         remote-endpoint = <&dsi1_in>;
  964                                                 };
  965                                         };
  966                                 };
  967                         };
  968 
  969                         dsi0: dsi@994000 {
  970                                 compatible = "qcom,mdss-dsi-ctrl";
  971                                 reg = <0x00994000 0x400>;
  972                                 reg-names = "dsi_ctrl";
  973 
  974                                 interrupt-parent = <&mdss>;
  975                                 interrupts = <4>;
  976 
  977                                 clocks = <&mmcc MDSS_MDP_CLK>,
  978                                          <&mmcc MDSS_BYTE0_CLK>,
  979                                          <&mmcc MDSS_AHB_CLK>,
  980                                          <&mmcc MDSS_AXI_CLK>,
  981                                          <&mmcc MMSS_MISC_AHB_CLK>,
  982                                          <&mmcc MDSS_PCLK0_CLK>,
  983                                          <&mmcc MDSS_ESC0_CLK>;
  984                                 clock-names = "mdp_core",
  985                                               "byte",
  986                                               "iface",
  987                                               "bus",
  988                                               "core_mmss",
  989                                               "pixel",
  990                                               "core";
  991                                 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
  992                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
  993 
  994                                 phys = <&dsi0_phy>;
  995                                 phy-names = "dsi";
  996                                 status = "disabled";
  997 
  998                                 #address-cells = <1>;
  999                                 #size-cells = <0>;
 1000 
 1001                                 ports {
 1002                                         #address-cells = <1>;
 1003                                         #size-cells = <0>;
 1004 
 1005                                         port@0 {
 1006                                                 reg = <0>;
 1007                                                 dsi0_in: endpoint {
 1008                                                         remote-endpoint = <&mdp5_intf1_out>;
 1009                                                 };
 1010                                         };
 1011 
 1012                                         port@1 {
 1013                                                 reg = <1>;
 1014                                                 dsi0_out: endpoint {
 1015                                                 };
 1016                                         };
 1017                                 };
 1018                         };
 1019 
 1020                         dsi0_phy: dsi-phy@994400 {
 1021                                 compatible = "qcom,dsi-phy-14nm";
 1022                                 reg = <0x00994400 0x100>,
 1023                                       <0x00994500 0x300>,
 1024                                       <0x00994800 0x188>;
 1025                                 reg-names = "dsi_phy",
 1026                                             "dsi_phy_lane",
 1027                                             "dsi_pll";
 1028 
 1029                                 #clock-cells = <1>;
 1030                                 #phy-cells = <0>;
 1031 
 1032                                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
 1033                                 clock-names = "iface", "ref";
 1034                                 status = "disabled";
 1035                         };
 1036 
 1037                         dsi1: dsi@996000 {
 1038                                 compatible = "qcom,mdss-dsi-ctrl";
 1039                                 reg = <0x00996000 0x400>;
 1040                                 reg-names = "dsi_ctrl";
 1041 
 1042                                 interrupt-parent = <&mdss>;
 1043                                 interrupts = <4>;
 1044 
 1045                                 clocks = <&mmcc MDSS_MDP_CLK>,
 1046                                          <&mmcc MDSS_BYTE1_CLK>,
 1047                                          <&mmcc MDSS_AHB_CLK>,
 1048                                          <&mmcc MDSS_AXI_CLK>,
 1049                                          <&mmcc MMSS_MISC_AHB_CLK>,
 1050                                          <&mmcc MDSS_PCLK1_CLK>,
 1051                                          <&mmcc MDSS_ESC1_CLK>;
 1052                                 clock-names = "mdp_core",
 1053                                               "byte",
 1054                                               "iface",
 1055                                               "bus",
 1056                                               "core_mmss",
 1057                                               "pixel",
 1058                                               "core";
 1059                                 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
 1060                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 1061 
 1062                                 phys = <&dsi1_phy>;
 1063                                 phy-names = "dsi";
 1064                                 status = "disabled";
 1065 
 1066                                 #address-cells = <1>;
 1067                                 #size-cells = <0>;
 1068 
 1069                                 ports {
 1070                                         #address-cells = <1>;
 1071                                         #size-cells = <0>;
 1072 
 1073                                         port@0 {
 1074                                                 reg = <0>;
 1075                                                 dsi1_in: endpoint {
 1076                                                         remote-endpoint = <&mdp5_intf2_out>;
 1077                                                 };
 1078                                         };
 1079 
 1080                                         port@1 {
 1081                                                 reg = <1>;
 1082                                                 dsi1_out: endpoint {
 1083                                                 };
 1084                                         };
 1085                                 };
 1086                         };
 1087 
 1088                         dsi1_phy: dsi-phy@996400 {
 1089                                 compatible = "qcom,dsi-phy-14nm";
 1090                                 reg = <0x00996400 0x100>,
 1091                                       <0x00996500 0x300>,
 1092                                       <0x00996800 0x188>;
 1093                                 reg-names = "dsi_phy",
 1094                                             "dsi_phy_lane",
 1095                                             "dsi_pll";
 1096 
 1097                                 #clock-cells = <1>;
 1098                                 #phy-cells = <0>;
 1099 
 1100                                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
 1101                                 clock-names = "iface", "ref";
 1102                                 status = "disabled";
 1103                         };
 1104 
 1105                         hdmi: hdmi-tx@9a0000 {
 1106                                 compatible = "qcom,hdmi-tx-8996";
 1107                                 reg =   <0x009a0000 0x50c>,
 1108                                         <0x00070000 0x6158>,
 1109                                         <0x009e0000 0xfff>;
 1110                                 reg-names = "core_physical",
 1111                                             "qfprom_physical",
 1112                                             "hdcp_physical";
 1113 
 1114                                 interrupt-parent = <&mdss>;
 1115                                 interrupts = <8>;
 1116 
 1117                                 clocks = <&mmcc MDSS_MDP_CLK>,
 1118                                          <&mmcc MDSS_AHB_CLK>,
 1119                                          <&mmcc MDSS_HDMI_CLK>,
 1120                                          <&mmcc MDSS_HDMI_AHB_CLK>,
 1121                                          <&mmcc MDSS_EXTPCLK_CLK>;
 1122                                 clock-names =
 1123                                         "mdp_core",
 1124                                         "iface",
 1125                                         "core",
 1126                                         "alt_iface",
 1127                                         "extp";
 1128 
 1129                                 phys = <&hdmi_phy>;
 1130                                 #sound-dai-cells = <1>;
 1131 
 1132                                 status = "disabled";
 1133 
 1134                                 ports {
 1135                                         #address-cells = <1>;
 1136                                         #size-cells = <0>;
 1137 
 1138                                         port@0 {
 1139                                                 reg = <0>;
 1140                                                 hdmi_in: endpoint {
 1141                                                         remote-endpoint = <&mdp5_intf3_out>;
 1142                                                 };
 1143                                         };
 1144                                 };
 1145                         };
 1146 
 1147                         hdmi_phy: hdmi-phy@9a0600 {
 1148                                 #phy-cells = <0>;
 1149                                 compatible = "qcom,hdmi-phy-8996";
 1150                                 reg = <0x009a0600 0x1c4>,
 1151                                       <0x009a0a00 0x124>,
 1152                                       <0x009a0c00 0x124>,
 1153                                       <0x009a0e00 0x124>,
 1154                                       <0x009a1000 0x124>,
 1155                                       <0x009a1200 0x0c8>;
 1156                                 reg-names = "hdmi_pll",
 1157                                             "hdmi_tx_l0",
 1158                                             "hdmi_tx_l1",
 1159                                             "hdmi_tx_l2",
 1160                                             "hdmi_tx_l3",
 1161                                             "hdmi_phy";
 1162 
 1163                                 clocks = <&mmcc MDSS_AHB_CLK>,
 1164                                          <&gcc GCC_HDMI_CLKREF_CLK>;
 1165                                 clock-names = "iface",
 1166                                               "ref";
 1167 
 1168                                 status = "disabled";
 1169                         };
 1170                 };
 1171 
 1172                 gpu: gpu@b00000 {
 1173                         compatible = "qcom,adreno-530.2", "qcom,adreno";
 1174 
 1175                         reg = <0x00b00000 0x3f000>;
 1176                         reg-names = "kgsl_3d0_reg_memory";
 1177 
 1178                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 1179 
 1180                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
 1181                                 <&mmcc GPU_AHB_CLK>,
 1182                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
 1183                                 <&gcc GCC_BIMC_GFX_CLK>,
 1184                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
 1185 
 1186                         clock-names = "core",
 1187                                 "iface",
 1188                                 "rbbmtimer",
 1189                                 "mem",
 1190                                 "mem_iface";
 1191 
 1192                         interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>;
 1193                         interconnect-names = "gfx-mem";
 1194 
 1195                         power-domains = <&mmcc GPU_GX_GDSC>;
 1196                         iommus = <&adreno_smmu 0>;
 1197 
 1198                         nvmem-cells = <&speedbin_efuse>;
 1199                         nvmem-cell-names = "speed_bin";
 1200 
 1201                         operating-points-v2 = <&gpu_opp_table>;
 1202 
 1203                         status = "disabled";
 1204 
 1205                         #cooling-cells = <2>;
 1206 
 1207                         gpu_opp_table: opp-table {
 1208                                 compatible = "operating-points-v2";
 1209 
 1210                                 /*
 1211                                  * 624Mhz and 560Mhz are only available on speed
 1212                                  * bin (1 << 0). All the rest are available on
 1213                                  * all bins of the hardware
 1214                                  */
 1215                                 opp-624000000 {
 1216                                         opp-hz = /bits/ 64 <624000000>;
 1217                                         opp-supported-hw = <0x01>;
 1218                                 };
 1219                                 opp-560000000 {
 1220                                         opp-hz = /bits/ 64 <560000000>;
 1221                                         opp-supported-hw = <0x01>;
 1222                                 };
 1223                                 opp-510000000 {
 1224                                         opp-hz = /bits/ 64 <510000000>;
 1225                                         opp-supported-hw = <0xFF>;
 1226                                 };
 1227                                 opp-401800000 {
 1228                                         opp-hz = /bits/ 64 <401800000>;
 1229                                         opp-supported-hw = <0xFF>;
 1230                                 };
 1231                                 opp-315000000 {
 1232                                         opp-hz = /bits/ 64 <315000000>;
 1233                                         opp-supported-hw = <0xFF>;
 1234                                 };
 1235                                 opp-214000000 {
 1236                                         opp-hz = /bits/ 64 <214000000>;
 1237                                         opp-supported-hw = <0xFF>;
 1238                                 };
 1239                                 opp-133000000 {
 1240                                         opp-hz = /bits/ 64 <133000000>;
 1241                                         opp-supported-hw = <0xFF>;
 1242                                 };
 1243                         };
 1244 
 1245                         zap-shader {
 1246                                 memory-region = <&gpu_mem>;
 1247                         };
 1248                 };
 1249 
 1250                 tlmm: pinctrl@1010000 {
 1251                         compatible = "qcom,msm8996-pinctrl";
 1252                         reg = <0x01010000 0x300000>;
 1253                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 1254                         gpio-controller;
 1255                         gpio-ranges = <&tlmm 0 0 150>;
 1256                         #gpio-cells = <2>;
 1257                         interrupt-controller;
 1258                         #interrupt-cells = <2>;
 1259 
 1260                         blsp1_spi1_default: blsp1-spi1-default {
 1261                                 spi {
 1262                                         pins = "gpio0", "gpio1", "gpio3";
 1263                                         function = "blsp_spi1";
 1264                                         drive-strength = <12>;
 1265                                         bias-disable;
 1266                                 };
 1267 
 1268                                 cs {
 1269                                         pins = "gpio2";
 1270                                         function = "gpio";
 1271                                         drive-strength = <16>;
 1272                                         bias-disable;
 1273                                         output-high;
 1274                                 };
 1275                         };
 1276 
 1277                         blsp1_spi1_sleep: blsp1-spi1-sleep {
 1278                                 pins = "gpio0", "gpio1", "gpio2", "gpio3";
 1279                                 function = "gpio";
 1280                                 drive-strength = <2>;
 1281                                 bias-pull-down;
 1282                         };
 1283 
 1284                         blsp2_uart2_2pins_default: blsp2-uart1-2pins {
 1285                                 pins = "gpio4", "gpio5";
 1286                                 function = "blsp_uart8";
 1287                                 drive-strength = <16>;
 1288                                 bias-disable;
 1289                         };
 1290 
 1291                         blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
 1292                                 pins = "gpio4", "gpio5";
 1293                                 function = "gpio";
 1294                                 drive-strength = <2>;
 1295                                 bias-disable;
 1296                         };
 1297 
 1298                         blsp2_i2c2_default: blsp2-i2c2 {
 1299                                 pins = "gpio6", "gpio7";
 1300                                 function = "blsp_i2c8";
 1301                                 drive-strength = <16>;
 1302                                 bias-disable;
 1303                         };
 1304 
 1305                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
 1306                                 pins = "gpio6", "gpio7";
 1307                                 function = "gpio";
 1308                                 drive-strength = <2>;
 1309                                 bias-disable;
 1310                         };
 1311 
 1312                         cci0_default: cci0-default {
 1313                                 pins = "gpio17", "gpio18";
 1314                                 function = "cci_i2c";
 1315                                 drive-strength = <16>;
 1316                                 bias-disable;
 1317                         };
 1318 
 1319                         camera0_state_on:
 1320                         camera_rear_default: camera-rear-default {
 1321                                 camera0_mclk: mclk0 {
 1322                                         pins = "gpio13";
 1323                                         function = "cam_mclk";
 1324                                         drive-strength = <16>;
 1325                                         bias-disable;
 1326                                 };
 1327 
 1328                                 camera0_rst: rst {
 1329                                         pins = "gpio25";
 1330                                         function = "gpio";
 1331                                         drive-strength = <16>;
 1332                                         bias-disable;
 1333                                 };
 1334 
 1335                                 camera0_pwdn: pwdn {
 1336                                         pins = "gpio26";
 1337                                         function = "gpio";
 1338                                         drive-strength = <16>;
 1339                                         bias-disable;
 1340                                 };
 1341                         };
 1342 
 1343                         cci1_default: cci1-default {
 1344                                 pins = "gpio19", "gpio20";
 1345                                 function = "cci_i2c";
 1346                                 drive-strength = <16>;
 1347                                 bias-disable;
 1348                         };
 1349 
 1350                         camera1_state_on:
 1351                         camera_board_default: camera-board-default {
 1352                                 mclk1 {
 1353                                         pins = "gpio14";
 1354                                         function = "cam_mclk";
 1355                                         drive-strength = <16>;
 1356                                         bias-disable;
 1357                                 };
 1358 
 1359                                 pwdn {
 1360                                         pins = "gpio98";
 1361                                         function = "gpio";
 1362                                         drive-strength = <16>;
 1363                                         bias-disable;
 1364                                 };
 1365 
 1366                                 rst {
 1367                                         pins = "gpio104";
 1368                                         function = "gpio";
 1369                                         drive-strength = <16>;
 1370                                         bias-disable;
 1371                                 };
 1372                         };
 1373 
 1374                         camera2_state_on:
 1375                         camera_front_default: camera-front-default {
 1376                                 camera2_mclk: mclk2 {
 1377                                         pins = "gpio15";
 1378                                         function = "cam_mclk";
 1379                                         drive-strength = <16>;
 1380                                         bias-disable;
 1381                                 };
 1382 
 1383                                 camera2_rst: rst {
 1384                                         pins = "gpio23";
 1385                                         function = "gpio";
 1386                                         drive-strength = <16>;
 1387                                         bias-disable;
 1388                                 };
 1389 
 1390                                 pwdn {
 1391                                         pins = "gpio133";
 1392                                         function = "gpio";
 1393                                         drive-strength = <16>;
 1394                                         bias-disable;
 1395                                 };
 1396                         };
 1397 
 1398                         pcie0_state_on: pcie0-state-on {
 1399                                 perst {
 1400                                         pins = "gpio35";
 1401                                         function = "gpio";
 1402                                         drive-strength = <2>;
 1403                                         bias-pull-down;
 1404                                 };
 1405 
 1406                                 clkreq {
 1407                                         pins = "gpio36";
 1408                                         function = "pci_e0";
 1409                                         drive-strength = <2>;
 1410                                         bias-pull-up;
 1411                                 };
 1412 
 1413                                 wake {
 1414                                         pins = "gpio37";
 1415                                         function = "gpio";
 1416                                         drive-strength = <2>;
 1417                                         bias-pull-up;
 1418                                 };
 1419                         };
 1420 
 1421                         pcie0_state_off: pcie0-state-off {
 1422                                 perst {
 1423                                         pins = "gpio35";
 1424                                         function = "gpio";
 1425                                         drive-strength = <2>;
 1426                                         bias-pull-down;
 1427                                 };
 1428 
 1429                                 clkreq {
 1430                                         pins = "gpio36";
 1431                                         function = "gpio";
 1432                                         drive-strength = <2>;
 1433                                         bias-disable;
 1434                                 };
 1435 
 1436                                 wake {
 1437                                         pins = "gpio37";
 1438                                         function = "gpio";
 1439                                         drive-strength = <2>;
 1440                                         bias-disable;
 1441                                 };
 1442                         };
 1443 
 1444                         blsp1_uart2_default: blsp1-uart2-default {
 1445                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
 1446                                 function = "blsp_uart2";
 1447                                 drive-strength = <16>;
 1448                                 bias-disable;
 1449                         };
 1450 
 1451                         blsp1_uart2_sleep: blsp1-uart2-sleep {
 1452                                 pins = "gpio41", "gpio42", "gpio43", "gpio44";
 1453                                 function = "gpio";
 1454                                 drive-strength = <2>;
 1455                                 bias-disable;
 1456                         };
 1457 
 1458                         blsp1_i2c3_default: blsp1-i2c2-default {
 1459                                 pins = "gpio47", "gpio48";
 1460                                 function = "blsp_i2c3";
 1461                                 drive-strength = <16>;
 1462                                 bias-disable;
 1463                         };
 1464 
 1465                         blsp1_i2c3_sleep: blsp1-i2c2-sleep {
 1466                                 pins = "gpio47", "gpio48";
 1467                                 function = "gpio";
 1468                                 drive-strength = <2>;
 1469                                 bias-disable;
 1470                         };
 1471 
 1472                         blsp2_uart3_4pins_default: blsp2-uart2-4pins {
 1473                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
 1474                                 function = "blsp_uart9";
 1475                                 drive-strength = <16>;
 1476                                 bias-disable;
 1477                         };
 1478 
 1479                         blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
 1480                                 pins = "gpio49", "gpio50", "gpio51", "gpio52";
 1481                                 function = "blsp_uart9";
 1482                                 drive-strength = <2>;
 1483                                 bias-disable;
 1484                         };
 1485 
 1486                         blsp2_i2c3_default: blsp2-i2c3 {
 1487                                 pins = "gpio51", "gpio52";
 1488                                 function = "blsp_i2c9";
 1489                                 drive-strength = <16>;
 1490                                 bias-disable;
 1491                         };
 1492 
 1493                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
 1494                                 pins = "gpio51", "gpio52";
 1495                                 function = "gpio";
 1496                                 drive-strength = <2>;
 1497                                 bias-disable;
 1498                         };
 1499 
 1500                         wcd_intr_default: wcd-intr-default{
 1501                                 pins = "gpio54";
 1502                                 function = "gpio";
 1503                                 drive-strength = <2>;
 1504                                 bias-pull-down;
 1505                                 input-enable;
 1506                         };
 1507 
 1508                         blsp2_i2c1_default: blsp2-i2c1 {
 1509                                 pins = "gpio55", "gpio56";
 1510                                 function = "blsp_i2c7";
 1511                                 drive-strength = <16>;
 1512                                 bias-disable;
 1513                         };
 1514 
 1515                         blsp2_i2c1_sleep: blsp2-i2c0-sleep {
 1516                                 pins = "gpio55", "gpio56";
 1517                                 function = "gpio";
 1518                                 drive-strength = <2>;
 1519                                 bias-disable;
 1520                         };
 1521 
 1522                         blsp2_i2c5_default: blsp2-i2c5 {
 1523                                 pins = "gpio60", "gpio61";
 1524                                 function = "blsp_i2c11";
 1525                                 drive-strength = <2>;
 1526                                 bias-disable;
 1527                         };
 1528 
 1529                         /* Sleep state for BLSP2_I2C5 is missing.. */
 1530 
 1531                         cdc_reset_active: cdc-reset-active {
 1532                                 pins = "gpio64";
 1533                                 function = "gpio";
 1534                                 drive-strength = <16>;
 1535                                 bias-pull-down;
 1536                                 output-high;
 1537                         };
 1538 
 1539                         cdc_reset_sleep: cdc-reset-sleep {
 1540                                 pins = "gpio64";
 1541                                 function = "gpio";
 1542                                 drive-strength = <16>;
 1543                                 bias-disable;
 1544                                 output-low;
 1545                         };
 1546 
 1547                         blsp2_spi6_default: blsp2-spi5-default {
 1548                                 spi {
 1549                                         pins = "gpio85", "gpio86", "gpio88";
 1550                                         function = "blsp_spi12";
 1551                                         drive-strength = <12>;
 1552                                         bias-disable;
 1553                                 };
 1554 
 1555                                 cs {
 1556                                         pins = "gpio87";
 1557                                         function = "gpio";
 1558                                         drive-strength = <16>;
 1559                                         bias-disable;
 1560                                         output-high;
 1561                                 };
 1562                         };
 1563 
 1564                         blsp2_spi6_sleep: blsp2-spi5-sleep {
 1565                                 pins = "gpio85", "gpio86", "gpio87", "gpio88";
 1566                                 function = "gpio";
 1567                                 drive-strength = <2>;
 1568                                 bias-pull-down;
 1569                         };
 1570 
 1571                         blsp2_i2c6_default: blsp2-i2c6 {
 1572                                 pins = "gpio87", "gpio88";
 1573                                 function = "blsp_i2c12";
 1574                                 drive-strength = <16>;
 1575                                 bias-disable;
 1576                         };
 1577 
 1578                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
 1579                                 pins = "gpio87", "gpio88";
 1580                                 function = "gpio";
 1581                                 drive-strength = <2>;
 1582                                 bias-disable;
 1583                         };
 1584 
 1585                         pcie1_state_on: pcie1-state-on {
 1586                                 perst {
 1587                                         pins = "gpio130";
 1588                                         function = "gpio";
 1589                                         drive-strength = <2>;
 1590                                         bias-pull-down;
 1591                                 };
 1592 
 1593                                 clkreq {
 1594                                         pins = "gpio131";
 1595                                         function = "pci_e1";
 1596                                         drive-strength = <2>;
 1597                                         bias-pull-up;
 1598                                 };
 1599 
 1600                                 wake {
 1601                                         pins = "gpio132";
 1602                                         function = "gpio";
 1603                                         drive-strength = <2>;
 1604                                         bias-pull-down;
 1605                                 };
 1606                         };
 1607 
 1608                         pcie1_state_off: pcie1-state-off {
 1609                                 /* Perst is missing? */
 1610                                 clkreq {
 1611                                         pins = "gpio131";
 1612                                         function = "gpio";
 1613                                         drive-strength = <2>;
 1614                                         bias-disable;
 1615                                 };
 1616 
 1617                                 wake {
 1618                                         pins = "gpio132";
 1619                                         function = "gpio";
 1620                                         drive-strength = <2>;
 1621                                         bias-disable;
 1622                                 };
 1623                         };
 1624 
 1625                         pcie2_state_on: pcie2-state-on {
 1626                                 perst {
 1627                                         pins = "gpio114";
 1628                                         function = "gpio";
 1629                                         drive-strength = <2>;
 1630                                         bias-pull-down;
 1631                                 };
 1632 
 1633                                 clkreq {
 1634                                         pins = "gpio115";
 1635                                         function = "pci_e2";
 1636                                         drive-strength = <2>;
 1637                                         bias-pull-up;
 1638                                 };
 1639 
 1640                                 wake {
 1641                                         pins = "gpio116";
 1642                                         function = "gpio";
 1643                                         drive-strength = <2>;
 1644                                         bias-pull-down;
 1645                                 };
 1646                         };
 1647 
 1648                         pcie2_state_off: pcie2-state-off {
 1649                                 /* Perst is missing? */
 1650                                 clkreq {
 1651                                         pins = "gpio115";
 1652                                         function = "gpio";
 1653                                         drive-strength = <2>;
 1654                                         bias-disable;
 1655                                 };
 1656 
 1657                                 wake {
 1658                                         pins = "gpio116";
 1659                                         function = "gpio";
 1660                                         drive-strength = <2>;
 1661                                         bias-disable;
 1662                                 };
 1663                         };
 1664 
 1665                         sdc1_state_on: sdc1-state-on {
 1666                                 clk {
 1667                                         pins = "sdc1_clk";
 1668                                         bias-disable;
 1669                                         drive-strength = <16>;
 1670                                 };
 1671 
 1672                                 cmd {
 1673                                         pins = "sdc1_cmd";
 1674                                         bias-pull-up;
 1675                                         drive-strength = <10>;
 1676                                 };
 1677 
 1678                                 data {
 1679                                         pins = "sdc1_data";
 1680                                         bias-pull-up;
 1681                                         drive-strength = <10>;
 1682                                 };
 1683 
 1684                                 rclk {
 1685                                         pins = "sdc1_rclk";
 1686                                         bias-pull-down;
 1687                                 };
 1688                         };
 1689 
 1690                         sdc1_state_off: sdc1-state-off {
 1691                                 clk {
 1692                                         pins = "sdc1_clk";
 1693                                         bias-disable;
 1694                                         drive-strength = <2>;
 1695                                 };
 1696 
 1697                                 cmd {
 1698                                         pins = "sdc1_cmd";
 1699                                         bias-pull-up;
 1700                                         drive-strength = <2>;
 1701                                 };
 1702 
 1703                                 data {
 1704                                         pins = "sdc1_data";
 1705                                         bias-pull-up;
 1706                                         drive-strength = <2>;
 1707                                 };
 1708 
 1709                                 rclk {
 1710                                         pins = "sdc1_rclk";
 1711                                         bias-pull-down;
 1712                                 };
 1713                         };
 1714 
 1715                         sdc2_state_on: sdc2-clk-on {
 1716                                 clk {
 1717                                         pins = "sdc2_clk";
 1718                                         bias-disable;
 1719                                         drive-strength = <16>;
 1720                                 };
 1721 
 1722                                 cmd {
 1723                                         pins = "sdc2_cmd";
 1724                                         bias-pull-up;
 1725                                         drive-strength = <10>;
 1726                                 };
 1727 
 1728                                 data {
 1729                                         pins = "sdc2_data";
 1730                                         bias-pull-up;
 1731                                         drive-strength = <10>;
 1732                                 };
 1733                         };
 1734 
 1735                         sdc2_state_off: sdc2-clk-off {
 1736                                 clk {
 1737                                         pins = "sdc2_clk";
 1738                                         bias-disable;
 1739                                         drive-strength = <2>;
 1740                                 };
 1741 
 1742                                 cmd {
 1743                                         pins = "sdc2_cmd";
 1744                                         bias-pull-up;
 1745                                         drive-strength = <2>;
 1746                                 };
 1747 
 1748                                 data {
 1749                                         pins = "sdc2_data";
 1750                                         bias-pull-up;
 1751                                         drive-strength = <2>;
 1752                                 };
 1753                         };
 1754                 };
 1755 
 1756                 sram@290000 {
 1757                         compatible = "qcom,rpm-stats";
 1758                         reg = <0x00290000 0x10000>;
 1759                 };
 1760 
 1761                 spmi_bus: spmi@400f000 {
 1762                         compatible = "qcom,spmi-pmic-arb";
 1763                         reg = <0x0400f000 0x1000>,
 1764                               <0x04400000 0x800000>,
 1765                               <0x04c00000 0x800000>,
 1766                               <0x05800000 0x200000>,
 1767                               <0x0400a000 0x002100>;
 1768                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 1769                         interrupt-names = "periph_irq";
 1770                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 1771                         qcom,ee = <0>;
 1772                         qcom,channel = <0>;
 1773                         #address-cells = <2>;
 1774                         #size-cells = <0>;
 1775                         interrupt-controller;
 1776                         #interrupt-cells = <4>;
 1777                 };
 1778 
 1779                 agnoc@0 {
 1780                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
 1781                         compatible = "simple-pm-bus";
 1782                         #address-cells = <1>;
 1783                         #size-cells = <1>;
 1784                         ranges;
 1785 
 1786                         pcie0: pcie@600000 {
 1787                                 compatible = "qcom,pcie-msm8996";
 1788                                 status = "disabled";
 1789                                 power-domains = <&gcc PCIE0_GDSC>;
 1790                                 bus-range = <0x00 0xff>;
 1791                                 num-lanes = <1>;
 1792 
 1793                                 reg = <0x00600000 0x2000>,
 1794                                       <0x0c000000 0xf1d>,
 1795                                       <0x0c000f20 0xa8>,
 1796                                       <0x0c100000 0x100000>;
 1797                                 reg-names = "parf", "dbi", "elbi","config";
 1798 
 1799                                 phys = <&pciephy_0>;
 1800                                 phy-names = "pciephy";
 1801 
 1802                                 #address-cells = <3>;
 1803                                 #size-cells = <2>;
 1804                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
 1805                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
 1806 
 1807                                 device_type = "pci";
 1808 
 1809                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 1810                                 interrupt-names = "msi";
 1811                                 #interrupt-cells = <1>;
 1812                                 interrupt-map-mask = <0 0 0 0x7>;
 1813                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1814                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1815                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1816                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1817 
 1818                                 pinctrl-names = "default", "sleep";
 1819                                 pinctrl-0 = <&pcie0_state_on>;
 1820                                 pinctrl-1 = <&pcie0_state_off>;
 1821 
 1822                                 linux,pci-domain = <0>;
 1823 
 1824                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 1825                                         <&gcc GCC_PCIE_0_AUX_CLK>,
 1826                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 1827                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 1828                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 1829 
 1830                                 clock-names = "pipe",
 1831                                                 "aux",
 1832                                                 "cfg",
 1833                                                 "bus_master",
 1834                                                 "bus_slave";
 1835 
 1836                         };
 1837 
 1838                         pcie1: pcie@608000 {
 1839                                 compatible = "qcom,pcie-msm8996";
 1840                                 power-domains = <&gcc PCIE1_GDSC>;
 1841                                 bus-range = <0x00 0xff>;
 1842                                 num-lanes = <1>;
 1843 
 1844                                 status = "disabled";
 1845 
 1846                                 reg = <0x00608000 0x2000>,
 1847                                       <0x0d000000 0xf1d>,
 1848                                       <0x0d000f20 0xa8>,
 1849                                       <0x0d100000 0x100000>;
 1850 
 1851                                 reg-names = "parf", "dbi", "elbi","config";
 1852 
 1853                                 phys = <&pciephy_1>;
 1854                                 phy-names = "pciephy";
 1855 
 1856                                 #address-cells = <3>;
 1857                                 #size-cells = <2>;
 1858                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
 1859                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
 1860 
 1861                                 device_type = "pci";
 1862 
 1863                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 1864                                 interrupt-names = "msi";
 1865                                 #interrupt-cells = <1>;
 1866                                 interrupt-map-mask = <0 0 0 0x7>;
 1867                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1868                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1869                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1870                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1871 
 1872                                 pinctrl-names = "default", "sleep";
 1873                                 pinctrl-0 = <&pcie1_state_on>;
 1874                                 pinctrl-1 = <&pcie1_state_off>;
 1875 
 1876                                 linux,pci-domain = <1>;
 1877 
 1878                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 1879                                         <&gcc GCC_PCIE_1_AUX_CLK>,
 1880                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 1881                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 1882                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
 1883 
 1884                                 clock-names = "pipe",
 1885                                                 "aux",
 1886                                                 "cfg",
 1887                                                 "bus_master",
 1888                                                 "bus_slave";
 1889                         };
 1890 
 1891                         pcie2: pcie@610000 {
 1892                                 compatible = "qcom,pcie-msm8996";
 1893                                 power-domains = <&gcc PCIE2_GDSC>;
 1894                                 bus-range = <0x00 0xff>;
 1895                                 num-lanes = <1>;
 1896                                 status = "disabled";
 1897                                 reg = <0x00610000 0x2000>,
 1898                                       <0x0e000000 0xf1d>,
 1899                                       <0x0e000f20 0xa8>,
 1900                                       <0x0e100000 0x100000>;
 1901 
 1902                                 reg-names = "parf", "dbi", "elbi","config";
 1903 
 1904                                 phys = <&pciephy_2>;
 1905                                 phy-names = "pciephy";
 1906 
 1907                                 #address-cells = <3>;
 1908                                 #size-cells = <2>;
 1909                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
 1910                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
 1911 
 1912                                 device_type = "pci";
 1913 
 1914                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 1915                                 interrupt-names = "msi";
 1916                                 #interrupt-cells = <1>;
 1917                                 interrupt-map-mask = <0 0 0 0x7>;
 1918                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1919                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1920                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1921                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1922 
 1923                                 pinctrl-names = "default", "sleep";
 1924                                 pinctrl-0 = <&pcie2_state_on>;
 1925                                 pinctrl-1 = <&pcie2_state_off>;
 1926 
 1927                                 linux,pci-domain = <2>;
 1928                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
 1929                                         <&gcc GCC_PCIE_2_AUX_CLK>,
 1930                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
 1931                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
 1932                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
 1933 
 1934                                 clock-names = "pipe",
 1935                                                 "aux",
 1936                                                 "cfg",
 1937                                                 "bus_master",
 1938                                                 "bus_slave";
 1939                         };
 1940                 };
 1941 
 1942                 ufshc: ufshc@624000 {
 1943                         compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
 1944                                      "jedec,ufs-2.0";
 1945                         reg = <0x00624000 0x2500>;
 1946                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 1947 
 1948                         phys = <&ufsphy_lane>;
 1949                         phy-names = "ufsphy";
 1950 
 1951                         power-domains = <&gcc UFS_GDSC>;
 1952 
 1953                         clock-names =
 1954                                 "core_clk_src",
 1955                                 "core_clk",
 1956                                 "bus_clk",
 1957                                 "bus_aggr_clk",
 1958                                 "iface_clk",
 1959                                 "core_clk_unipro_src",
 1960                                 "core_clk_unipro",
 1961                                 "core_clk_ice",
 1962                                 "ref_clk",
 1963                                 "tx_lane0_sync_clk",
 1964                                 "rx_lane0_sync_clk";
 1965                         clocks =
 1966                                 <&gcc UFS_AXI_CLK_SRC>,
 1967                                 <&gcc GCC_UFS_AXI_CLK>,
 1968                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
 1969                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 1970                                 <&gcc GCC_UFS_AHB_CLK>,
 1971                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
 1972                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 1973                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
 1974                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
 1975                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 1976                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
 1977                         freq-table-hz =
 1978                                 <100000000 200000000>,
 1979                                 <0 0>,
 1980                                 <0 0>,
 1981                                 <0 0>,
 1982                                 <0 0>,
 1983                                 <150000000 300000000>,
 1984                                 <0 0>,
 1985                                 <0 0>,
 1986                                 <0 0>,
 1987                                 <0 0>,
 1988                                 <0 0>;
 1989 
 1990                         lanes-per-direction = <1>;
 1991                         #reset-cells = <1>;
 1992                         status = "disabled";
 1993 
 1994                         ufs_variant {
 1995                                 compatible = "qcom,ufs_variant";
 1996                         };
 1997                 };
 1998 
 1999                 ufsphy: phy@627000 {
 2000                         compatible = "qcom,msm8996-qmp-ufs-phy";
 2001                         reg = <0x00627000 0x1c4>;
 2002                         #address-cells = <1>;
 2003                         #size-cells = <1>;
 2004                         ranges;
 2005 
 2006                         clocks = <&gcc GCC_UFS_CLKREF_CLK>;
 2007                         clock-names = "ref";
 2008 
 2009                         resets = <&ufshc 0>;
 2010                         reset-names = "ufsphy";
 2011                         status = "disabled";
 2012 
 2013                         ufsphy_lane: phy@627400 {
 2014                                 reg = <0x627400 0x12c>,
 2015                                       <0x627600 0x200>,
 2016                                       <0x627c00 0x1b4>;
 2017                                 #phy-cells = <0>;
 2018                         };
 2019                 };
 2020 
 2021                 camss: camss@a00000 {
 2022                         compatible = "qcom,msm8996-camss";
 2023                         reg = <0x00a34000 0x1000>,
 2024                               <0x00a00030 0x4>,
 2025                               <0x00a35000 0x1000>,
 2026                               <0x00a00038 0x4>,
 2027                               <0x00a36000 0x1000>,
 2028                               <0x00a00040 0x4>,
 2029                               <0x00a30000 0x100>,
 2030                               <0x00a30400 0x100>,
 2031                               <0x00a30800 0x100>,
 2032                               <0x00a30c00 0x100>,
 2033                               <0x00a31000 0x500>,
 2034                               <0x00a00020 0x10>,
 2035                               <0x00a10000 0x1000>,
 2036                               <0x00a14000 0x1000>;
 2037                         reg-names = "csiphy0",
 2038                                 "csiphy0_clk_mux",
 2039                                 "csiphy1",
 2040                                 "csiphy1_clk_mux",
 2041                                 "csiphy2",
 2042                                 "csiphy2_clk_mux",
 2043                                 "csid0",
 2044                                 "csid1",
 2045                                 "csid2",
 2046                                 "csid3",
 2047                                 "ispif",
 2048                                 "csi_clk_mux",
 2049                                 "vfe0",
 2050                                 "vfe1";
 2051                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
 2052                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
 2053                                 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
 2054                                 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
 2055                                 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
 2056                                 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
 2057                                 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
 2058                                 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
 2059                                 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
 2060                                 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
 2061                         interrupt-names = "csiphy0",
 2062                                 "csiphy1",
 2063                                 "csiphy2",
 2064                                 "csid0",
 2065                                 "csid1",
 2066                                 "csid2",
 2067                                 "csid3",
 2068                                 "ispif",
 2069                                 "vfe0",
 2070                                 "vfe1";
 2071                         power-domains = <&mmcc VFE0_GDSC>,
 2072                                         <&mmcc VFE1_GDSC>;
 2073                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
 2074                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
 2075                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
 2076                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
 2077                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
 2078                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
 2079                                 <&mmcc CAMSS_CSI0_CLK>,
 2080                                 <&mmcc CAMSS_CSI0PHY_CLK>,
 2081                                 <&mmcc CAMSS_CSI0PIX_CLK>,
 2082                                 <&mmcc CAMSS_CSI0RDI_CLK>,
 2083                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
 2084                                 <&mmcc CAMSS_CSI1_CLK>,
 2085                                 <&mmcc CAMSS_CSI1PHY_CLK>,
 2086                                 <&mmcc CAMSS_CSI1PIX_CLK>,
 2087                                 <&mmcc CAMSS_CSI1RDI_CLK>,
 2088                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
 2089                                 <&mmcc CAMSS_CSI2_CLK>,
 2090                                 <&mmcc CAMSS_CSI2PHY_CLK>,
 2091                                 <&mmcc CAMSS_CSI2PIX_CLK>,
 2092                                 <&mmcc CAMSS_CSI2RDI_CLK>,
 2093                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
 2094                                 <&mmcc CAMSS_CSI3_CLK>,
 2095                                 <&mmcc CAMSS_CSI3PHY_CLK>,
 2096                                 <&mmcc CAMSS_CSI3PIX_CLK>,
 2097                                 <&mmcc CAMSS_CSI3RDI_CLK>,
 2098                                 <&mmcc CAMSS_AHB_CLK>,
 2099                                 <&mmcc CAMSS_VFE0_CLK>,
 2100                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
 2101                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
 2102                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
 2103                                 <&mmcc CAMSS_VFE1_CLK>,
 2104                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
 2105                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
 2106                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
 2107                                 <&mmcc CAMSS_VFE_AHB_CLK>,
 2108                                 <&mmcc CAMSS_VFE_AXI_CLK>;
 2109                         clock-names = "top_ahb",
 2110                                 "ispif_ahb",
 2111                                 "csiphy0_timer",
 2112                                 "csiphy1_timer",
 2113                                 "csiphy2_timer",
 2114                                 "csi0_ahb",
 2115                                 "csi0",
 2116                                 "csi0_phy",
 2117                                 "csi0_pix",
 2118                                 "csi0_rdi",
 2119                                 "csi1_ahb",
 2120                                 "csi1",
 2121                                 "csi1_phy",
 2122                                 "csi1_pix",
 2123                                 "csi1_rdi",
 2124                                 "csi2_ahb",
 2125                                 "csi2",
 2126                                 "csi2_phy",
 2127                                 "csi2_pix",
 2128                                 "csi2_rdi",
 2129                                 "csi3_ahb",
 2130                                 "csi3",
 2131                                 "csi3_phy",
 2132                                 "csi3_pix",
 2133                                 "csi3_rdi",
 2134                                 "ahb",
 2135                                 "vfe0",
 2136                                 "csi_vfe0",
 2137                                 "vfe0_ahb",
 2138                                 "vfe0_stream",
 2139                                 "vfe1",
 2140                                 "csi_vfe1",
 2141                                 "vfe1_ahb",
 2142                                 "vfe1_stream",
 2143                                 "vfe_ahb",
 2144                                 "vfe_axi";
 2145                         iommus = <&vfe_smmu 0>,
 2146                                  <&vfe_smmu 1>,
 2147                                  <&vfe_smmu 2>,
 2148                                  <&vfe_smmu 3>;
 2149                         status = "disabled";
 2150                         ports {
 2151                                 #address-cells = <1>;
 2152                                 #size-cells = <0>;
 2153                         };
 2154                 };
 2155 
 2156                 cci: cci@a0c000 {
 2157                         compatible = "qcom,msm8996-cci";
 2158                         #address-cells = <1>;
 2159                         #size-cells = <0>;
 2160                         reg = <0xa0c000 0x1000>;
 2161                         interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
 2162                         power-domains = <&mmcc CAMSS_GDSC>;
 2163                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
 2164                                  <&mmcc CAMSS_CCI_AHB_CLK>,
 2165                                  <&mmcc CAMSS_CCI_CLK>,
 2166                                  <&mmcc CAMSS_AHB_CLK>;
 2167                         clock-names = "camss_top_ahb",
 2168                                       "cci_ahb",
 2169                                       "cci",
 2170                                       "camss_ahb";
 2171                         assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
 2172                                           <&mmcc CAMSS_CCI_CLK>;
 2173                         assigned-clock-rates = <80000000>, <37500000>;
 2174                         pinctrl-names = "default";
 2175                         pinctrl-0 = <&cci0_default &cci1_default>;
 2176                         status = "disabled";
 2177 
 2178                         cci_i2c0: i2c-bus@0 {
 2179                                 reg = <0>;
 2180                                 clock-frequency = <400000>;
 2181                                 #address-cells = <1>;
 2182                                 #size-cells = <0>;
 2183                         };
 2184 
 2185                         cci_i2c1: i2c-bus@1 {
 2186                                 reg = <1>;
 2187                                 clock-frequency = <400000>;
 2188                                 #address-cells = <1>;
 2189                                 #size-cells = <0>;
 2190                         };
 2191                 };
 2192 
 2193                 adreno_smmu: iommu@b40000 {
 2194                         compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
 2195                         reg = <0x00b40000 0x10000>;
 2196 
 2197                         #global-interrupts = <1>;
 2198                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 2199                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 2200                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
 2201                         #iommu-cells = <1>;
 2202 
 2203                         clocks = <&mmcc GPU_AHB_CLK>,
 2204                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
 2205                         clock-names = "iface", "bus";
 2206 
 2207                         power-domains = <&mmcc GPU_GDSC>;
 2208                 };
 2209 
 2210                 venus: video-codec@c00000 {
 2211                         compatible = "qcom,msm8996-venus";
 2212                         reg = <0x00c00000 0xff000>;
 2213                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 2214                         power-domains = <&mmcc VENUS_GDSC>;
 2215                         clocks = <&mmcc VIDEO_CORE_CLK>,
 2216                                  <&mmcc VIDEO_AHB_CLK>,
 2217                                  <&mmcc VIDEO_AXI_CLK>,
 2218                                  <&mmcc VIDEO_MAXI_CLK>;
 2219                         clock-names = "core", "iface", "bus", "mbus";
 2220                         interconnects = <&mnoc MASTER_VIDEO_P0 &bimc SLAVE_EBI_CH0>,
 2221                                         <&bimc MASTER_AMPSS_M0 &mnoc SLAVE_VENUS_CFG>;
 2222                         interconnect-names = "video-mem", "cpu-cfg";
 2223                         iommus = <&venus_smmu 0x00>,
 2224                                  <&venus_smmu 0x01>,
 2225                                  <&venus_smmu 0x0a>,
 2226                                  <&venus_smmu 0x07>,
 2227                                  <&venus_smmu 0x0e>,
 2228                                  <&venus_smmu 0x0f>,
 2229                                  <&venus_smmu 0x08>,
 2230                                  <&venus_smmu 0x09>,
 2231                                  <&venus_smmu 0x0b>,
 2232                                  <&venus_smmu 0x0c>,
 2233                                  <&venus_smmu 0x0d>,
 2234                                  <&venus_smmu 0x10>,
 2235                                  <&venus_smmu 0x11>,
 2236                                  <&venus_smmu 0x21>,
 2237                                  <&venus_smmu 0x28>,
 2238                                  <&venus_smmu 0x29>,
 2239                                  <&venus_smmu 0x2b>,
 2240                                  <&venus_smmu 0x2c>,
 2241                                  <&venus_smmu 0x2d>,
 2242                                  <&venus_smmu 0x31>;
 2243                         memory-region = <&venus_mem>;
 2244                         status = "disabled";
 2245 
 2246                         video-decoder {
 2247                                 compatible = "venus-decoder";
 2248                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
 2249                                 clock-names = "core";
 2250                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
 2251                         };
 2252 
 2253                         video-encoder {
 2254                                 compatible = "venus-encoder";
 2255                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
 2256                                 clock-names = "core";
 2257                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
 2258                         };
 2259                 };
 2260 
 2261                 mdp_smmu: iommu@d00000 {
 2262                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 2263                         reg = <0x00d00000 0x10000>;
 2264 
 2265                         #global-interrupts = <1>;
 2266                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 2267                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 2268                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
 2269                         #iommu-cells = <1>;
 2270                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
 2271                                  <&mmcc SMMU_MDP_AXI_CLK>;
 2272                         clock-names = "iface", "bus";
 2273 
 2274                         power-domains = <&mmcc MDSS_GDSC>;
 2275                 };
 2276 
 2277                 venus_smmu: iommu@d40000 {
 2278                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 2279                         reg = <0x00d40000 0x20000>;
 2280                         #global-interrupts = <1>;
 2281                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 2282                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 2283                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 2284                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 2285                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 2286                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 2287                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 2288                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 2289                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
 2290                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
 2291                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
 2292                         clock-names = "iface", "bus";
 2293                         #iommu-cells = <1>;
 2294                         status = "okay";
 2295                 };
 2296 
 2297                 vfe_smmu: iommu@da0000 {
 2298                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 2299                         reg = <0x00da0000 0x10000>;
 2300 
 2301                         #global-interrupts = <1>;
 2302                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 2303                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 2304                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 2305                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
 2306                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
 2307                                  <&mmcc SMMU_VFE_AXI_CLK>;
 2308                         clock-names = "iface",
 2309                                       "bus";
 2310                         #iommu-cells = <1>;
 2311                 };
 2312 
 2313                 lpass_q6_smmu: iommu@1600000 {
 2314                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 2315                         reg = <0x01600000 0x20000>;
 2316                         #iommu-cells = <1>;
 2317                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
 2318 
 2319                         #global-interrupts = <1>;
 2320                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 2321                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
 2322                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
 2323                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
 2324                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 2325                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 2326                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 2327                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 2328                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 2329                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 2330                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 2331                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 2332                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
 2333 
 2334                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
 2335                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
 2336                         clock-names = "iface", "bus";
 2337                 };
 2338 
 2339                 slpi_pil: remoteproc@1c00000 {
 2340                         compatible = "qcom,msm8996-slpi-pil";
 2341                         reg = <0x01c00000 0x4000>;
 2342 
 2343                         interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
 2344                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 2345                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 2346                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 2347                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 2348                         interrupt-names = "wdog",
 2349                                           "fatal",
 2350                                           "ready",
 2351                                           "handover",
 2352                                           "stop-ack";
 2353 
 2354                         clocks = <&xo_board>,
 2355                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
 2356                         clock-names = "xo", "aggre2";
 2357 
 2358                         memory-region = <&slpi_mem>;
 2359 
 2360                         qcom,smem-states = <&slpi_smp2p_out 0>;
 2361                         qcom,smem-state-names = "stop";
 2362 
 2363                         power-domains = <&rpmpd MSM8996_VDDSSCX>;
 2364                         power-domain-names = "ssc_cx";
 2365 
 2366                         status = "disabled";
 2367 
 2368                         smd-edge {
 2369                                 interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
 2370 
 2371                                 label = "dsps";
 2372                                 mboxes = <&apcs_glb 25>;
 2373                                 qcom,smd-edge = <3>;
 2374                                 qcom,remote-pid = <3>;
 2375                         };
 2376                 };
 2377 
 2378                 mss_pil: remoteproc@2080000 {
 2379                         compatible = "qcom,msm8996-mss-pil";
 2380                         reg = <0x2080000 0x100>,
 2381                               <0x2180000 0x020>;
 2382                         reg-names = "qdsp6", "rmb";
 2383 
 2384                         interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
 2385                                               <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 2386                                               <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 2387                                               <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 2388                                               <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
 2389                                               <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
 2390                         interrupt-names = "wdog", "fatal", "ready",
 2391                                           "handover", "stop-ack",
 2392                                           "shutdown-ack";
 2393 
 2394                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 2395                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
 2396                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 2397                                  <&xo_board>,
 2398                                  <&gcc GCC_MSS_GPLL0_DIV_CLK>,
 2399                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
 2400                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
 2401                                  <&rpmcc RPM_SMD_PCNOC_CLK>,
 2402                                  <&rpmcc RPM_SMD_QDSS_CLK>;
 2403                         clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
 2404                                       "snoc_axi", "mnoc_axi", "pnoc", "qdss";
 2405 
 2406                         resets = <&gcc GCC_MSS_RESTART>;
 2407                         reset-names = "mss_restart";
 2408 
 2409                         power-domains = <&rpmpd MSM8996_VDDCX>,
 2410                                         <&rpmpd MSM8996_VDDMX>;
 2411                         power-domain-names = "cx", "mx";
 2412 
 2413                         qcom,smem-states = <&mpss_smp2p_out 0>;
 2414                         qcom,smem-state-names = "stop";
 2415 
 2416                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
 2417 
 2418                         status = "disabled";
 2419 
 2420                         mba {
 2421                                 memory-region = <&mba_mem>;
 2422                         };
 2423 
 2424                         mpss {
 2425                                 memory-region = <&mpss_mem>;
 2426                         };
 2427 
 2428                         smd-edge {
 2429                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
 2430 
 2431                                 label = "mpss";
 2432                                 mboxes = <&apcs_glb 12>;
 2433                                 qcom,smd-edge = <0>;
 2434                                 qcom,remote-pid = <1>;
 2435                         };
 2436                 };
 2437 
 2438                 stm@3002000 {
 2439                         compatible = "arm,coresight-stm", "arm,primecell";
 2440                         reg = <0x3002000 0x1000>,
 2441                               <0x8280000 0x180000>;
 2442                         reg-names = "stm-base", "stm-stimulus-base";
 2443 
 2444                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2445                         clock-names = "apb_pclk", "atclk";
 2446 
 2447                         out-ports {
 2448                                 port {
 2449                                         stm_out: endpoint {
 2450                                                 remote-endpoint =
 2451                                                   <&funnel0_in>;
 2452                                         };
 2453                                 };
 2454                         };
 2455                 };
 2456 
 2457                 tpiu@3020000 {
 2458                         compatible = "arm,coresight-tpiu", "arm,primecell";
 2459                         reg = <0x3020000 0x1000>;
 2460 
 2461                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2462                         clock-names = "apb_pclk", "atclk";
 2463 
 2464                         in-ports {
 2465                                 port {
 2466                                         tpiu_in: endpoint {
 2467                                                 remote-endpoint =
 2468                                                   <&replicator_out1>;
 2469                                         };
 2470                                 };
 2471                         };
 2472                 };
 2473 
 2474                 funnel@3021000 {
 2475                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2476                         reg = <0x3021000 0x1000>;
 2477 
 2478                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2479                         clock-names = "apb_pclk", "atclk";
 2480 
 2481                         in-ports {
 2482                                 #address-cells = <1>;
 2483                                 #size-cells = <0>;
 2484 
 2485                                 port@7 {
 2486                                         reg = <7>;
 2487                                         funnel0_in: endpoint {
 2488                                                 remote-endpoint =
 2489                                                   <&stm_out>;
 2490                                         };
 2491                                 };
 2492                         };
 2493 
 2494                         out-ports {
 2495                                 port {
 2496                                         funnel0_out: endpoint {
 2497                                                 remote-endpoint =
 2498                                                   <&merge_funnel_in0>;
 2499                                         };
 2500                                 };
 2501                         };
 2502                 };
 2503 
 2504                 funnel@3022000 {
 2505                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2506                         reg = <0x3022000 0x1000>;
 2507 
 2508                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2509                         clock-names = "apb_pclk", "atclk";
 2510 
 2511                         in-ports {
 2512                                 #address-cells = <1>;
 2513                                 #size-cells = <0>;
 2514 
 2515                                 port@6 {
 2516                                         reg = <6>;
 2517                                         funnel1_in: endpoint {
 2518                                                 remote-endpoint =
 2519                                                   <&apss_merge_funnel_out>;
 2520                                         };
 2521                                 };
 2522                         };
 2523 
 2524                         out-ports {
 2525                                 port {
 2526                                         funnel1_out: endpoint {
 2527                                                 remote-endpoint =
 2528                                                   <&merge_funnel_in1>;
 2529                                         };
 2530                                 };
 2531                         };
 2532                 };
 2533 
 2534                 funnel@3023000 {
 2535                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2536                         reg = <0x3023000 0x1000>;
 2537 
 2538                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2539                         clock-names = "apb_pclk", "atclk";
 2540 
 2541 
 2542                         out-ports {
 2543                                 port {
 2544                                         funnel2_out: endpoint {
 2545                                                 remote-endpoint =
 2546                                                   <&merge_funnel_in2>;
 2547                                         };
 2548                                 };
 2549                         };
 2550                 };
 2551 
 2552                 funnel@3025000 {
 2553                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2554                         reg = <0x3025000 0x1000>;
 2555 
 2556                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2557                         clock-names = "apb_pclk", "atclk";
 2558 
 2559                         in-ports {
 2560                                 #address-cells = <1>;
 2561                                 #size-cells = <0>;
 2562 
 2563                                 port@0 {
 2564                                         reg = <0>;
 2565                                         merge_funnel_in0: endpoint {
 2566                                                 remote-endpoint =
 2567                                                   <&funnel0_out>;
 2568                                         };
 2569                                 };
 2570 
 2571                                 port@1 {
 2572                                         reg = <1>;
 2573                                         merge_funnel_in1: endpoint {
 2574                                                 remote-endpoint =
 2575                                                   <&funnel1_out>;
 2576                                         };
 2577                                 };
 2578 
 2579                                 port@2 {
 2580                                         reg = <2>;
 2581                                         merge_funnel_in2: endpoint {
 2582                                                 remote-endpoint =
 2583                                                   <&funnel2_out>;
 2584                                         };
 2585                                 };
 2586                         };
 2587 
 2588                         out-ports {
 2589                                 port {
 2590                                         merge_funnel_out: endpoint {
 2591                                                 remote-endpoint =
 2592                                                   <&etf_in>;
 2593                                         };
 2594                                 };
 2595                         };
 2596                 };
 2597 
 2598                 replicator@3026000 {
 2599                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 2600                         reg = <0x3026000 0x1000>;
 2601 
 2602                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2603                         clock-names = "apb_pclk", "atclk";
 2604 
 2605                         in-ports {
 2606                                 port {
 2607                                         replicator_in: endpoint {
 2608                                                 remote-endpoint =
 2609                                                   <&etf_out>;
 2610                                         };
 2611                                 };
 2612                         };
 2613 
 2614                         out-ports {
 2615                                 #address-cells = <1>;
 2616                                 #size-cells = <0>;
 2617 
 2618                                 port@0 {
 2619                                         reg = <0>;
 2620                                         replicator_out0: endpoint {
 2621                                                 remote-endpoint =
 2622                                                   <&etr_in>;
 2623                                         };
 2624                                 };
 2625 
 2626                                 port@1 {
 2627                                         reg = <1>;
 2628                                         replicator_out1: endpoint {
 2629                                                 remote-endpoint =
 2630                                                   <&tpiu_in>;
 2631                                         };
 2632                                 };
 2633                         };
 2634                 };
 2635 
 2636                 etf@3027000 {
 2637                         compatible = "arm,coresight-tmc", "arm,primecell";
 2638                         reg = <0x3027000 0x1000>;
 2639 
 2640                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2641                         clock-names = "apb_pclk", "atclk";
 2642 
 2643                         in-ports {
 2644                                 port {
 2645                                         etf_in: endpoint {
 2646                                                 remote-endpoint =
 2647                                                   <&merge_funnel_out>;
 2648                                         };
 2649                                 };
 2650                         };
 2651 
 2652                         out-ports {
 2653                                 port {
 2654                                         etf_out: endpoint {
 2655                                                 remote-endpoint =
 2656                                                   <&replicator_in>;
 2657                                         };
 2658                                 };
 2659                         };
 2660                 };
 2661 
 2662                 etr@3028000 {
 2663                         compatible = "arm,coresight-tmc", "arm,primecell";
 2664                         reg = <0x3028000 0x1000>;
 2665 
 2666                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2667                         clock-names = "apb_pclk", "atclk";
 2668                         arm,scatter-gather;
 2669 
 2670                         in-ports {
 2671                                 port {
 2672                                         etr_in: endpoint {
 2673                                                 remote-endpoint =
 2674                                                   <&replicator_out0>;
 2675                                         };
 2676                                 };
 2677                         };
 2678                 };
 2679 
 2680                 debug@3810000 {
 2681                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 2682                         reg = <0x3810000 0x1000>;
 2683 
 2684                         clocks = <&rpmcc RPM_QDSS_CLK>;
 2685                         clock-names = "apb_pclk";
 2686 
 2687                         cpu = <&CPU0>;
 2688                 };
 2689 
 2690                 etm@3840000 {
 2691                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2692                         reg = <0x3840000 0x1000>;
 2693 
 2694                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2695                         clock-names = "apb_pclk", "atclk";
 2696 
 2697                         cpu = <&CPU0>;
 2698 
 2699                         out-ports {
 2700                                 port {
 2701                                         etm0_out: endpoint {
 2702                                                 remote-endpoint =
 2703                                                   <&apss_funnel0_in0>;
 2704                                         };
 2705                                 };
 2706                         };
 2707                 };
 2708 
 2709                 debug@3910000 {
 2710                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 2711                         reg = <0x3910000 0x1000>;
 2712 
 2713                         clocks = <&rpmcc RPM_QDSS_CLK>;
 2714                         clock-names = "apb_pclk";
 2715 
 2716                         cpu = <&CPU1>;
 2717                 };
 2718 
 2719                 etm@3940000 {
 2720                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2721                         reg = <0x3940000 0x1000>;
 2722 
 2723                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2724                         clock-names = "apb_pclk", "atclk";
 2725 
 2726                         cpu = <&CPU1>;
 2727 
 2728                         out-ports {
 2729                                 port {
 2730                                         etm1_out: endpoint {
 2731                                                 remote-endpoint =
 2732                                                   <&apss_funnel0_in1>;
 2733                                         };
 2734                                 };
 2735                         };
 2736                 };
 2737 
 2738                 funnel@39b0000 { /* APSS Funnel 0 */
 2739                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2740                         reg = <0x39b0000 0x1000>;
 2741 
 2742                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2743                         clock-names = "apb_pclk", "atclk";
 2744 
 2745                         in-ports {
 2746                                 #address-cells = <1>;
 2747                                 #size-cells = <0>;
 2748 
 2749                                 port@0 {
 2750                                         reg = <0>;
 2751                                         apss_funnel0_in0: endpoint {
 2752                                                 remote-endpoint = <&etm0_out>;
 2753                                         };
 2754                                 };
 2755 
 2756                                 port@1 {
 2757                                         reg = <1>;
 2758                                         apss_funnel0_in1: endpoint {
 2759                                                 remote-endpoint = <&etm1_out>;
 2760                                         };
 2761                                 };
 2762                         };
 2763 
 2764                         out-ports {
 2765                                 port {
 2766                                         apss_funnel0_out: endpoint {
 2767                                                 remote-endpoint =
 2768                                                   <&apss_merge_funnel_in0>;
 2769                                         };
 2770                                 };
 2771                         };
 2772                 };
 2773 
 2774                 debug@3a10000 {
 2775                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 2776                         reg = <0x3a10000 0x1000>;
 2777 
 2778                         clocks = <&rpmcc RPM_QDSS_CLK>;
 2779                         clock-names = "apb_pclk";
 2780 
 2781                         cpu = <&CPU2>;
 2782                 };
 2783 
 2784                 etm@3a40000 {
 2785                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2786                         reg = <0x3a40000 0x1000>;
 2787 
 2788                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2789                         clock-names = "apb_pclk", "atclk";
 2790 
 2791                         cpu = <&CPU2>;
 2792 
 2793                         out-ports {
 2794                                 port {
 2795                                         etm2_out: endpoint {
 2796                                                 remote-endpoint =
 2797                                                   <&apss_funnel1_in0>;
 2798                                         };
 2799                                 };
 2800                         };
 2801                 };
 2802 
 2803                 debug@3b10000 {
 2804                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
 2805                         reg = <0x3b10000 0x1000>;
 2806 
 2807                         clocks = <&rpmcc RPM_QDSS_CLK>;
 2808                         clock-names = "apb_pclk";
 2809 
 2810                         cpu = <&CPU3>;
 2811                 };
 2812 
 2813                 etm@3b40000 {
 2814                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2815                         reg = <0x3b40000 0x1000>;
 2816 
 2817                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2818                         clock-names = "apb_pclk", "atclk";
 2819 
 2820                         cpu = <&CPU3>;
 2821 
 2822                         out-ports {
 2823                                 port {
 2824                                         etm3_out: endpoint {
 2825                                                 remote-endpoint =
 2826                                                   <&apss_funnel1_in1>;
 2827                                         };
 2828                                 };
 2829                         };
 2830                 };
 2831 
 2832                 funnel@3bb0000 { /* APSS Funnel 1 */
 2833                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2834                         reg = <0x3bb0000 0x1000>;
 2835 
 2836                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2837                         clock-names = "apb_pclk", "atclk";
 2838 
 2839                         in-ports {
 2840                                 #address-cells = <1>;
 2841                                 #size-cells = <0>;
 2842 
 2843                                 port@0 {
 2844                                         reg = <0>;
 2845                                         apss_funnel1_in0: endpoint {
 2846                                                 remote-endpoint = <&etm2_out>;
 2847                                         };
 2848                                 };
 2849 
 2850                                 port@1 {
 2851                                         reg = <1>;
 2852                                         apss_funnel1_in1: endpoint {
 2853                                                 remote-endpoint = <&etm3_out>;
 2854                                         };
 2855                                 };
 2856                         };
 2857 
 2858                         out-ports {
 2859                                 port {
 2860                                         apss_funnel1_out: endpoint {
 2861                                                 remote-endpoint =
 2862                                                   <&apss_merge_funnel_in1>;
 2863                                         };
 2864                                 };
 2865                         };
 2866                 };
 2867 
 2868                 funnel@3bc0000 {
 2869                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2870                         reg = <0x3bc0000 0x1000>;
 2871 
 2872                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
 2873                         clock-names = "apb_pclk", "atclk";
 2874 
 2875                         in-ports {
 2876                                 #address-cells = <1>;
 2877                                 #size-cells = <0>;
 2878 
 2879                                 port@0 {
 2880                                         reg = <0>;
 2881                                         apss_merge_funnel_in0: endpoint {
 2882                                                 remote-endpoint =
 2883                                                   <&apss_funnel0_out>;
 2884                                         };
 2885                                 };
 2886 
 2887                                 port@1 {
 2888                                         reg = <1>;
 2889                                         apss_merge_funnel_in1: endpoint {
 2890                                                 remote-endpoint =
 2891                                                   <&apss_funnel1_out>;
 2892                                         };
 2893                                 };
 2894                         };
 2895 
 2896                         out-ports {
 2897                                 port {
 2898                                         apss_merge_funnel_out: endpoint {
 2899                                                 remote-endpoint =
 2900                                                   <&funnel1_in>;
 2901                                         };
 2902                                 };
 2903                         };
 2904                 };
 2905 
 2906                 kryocc: clock-controller@6400000 {
 2907                         compatible = "qcom,msm8996-apcc";
 2908                         reg = <0x06400000 0x90000>;
 2909 
 2910                         clock-names = "xo";
 2911                         clocks = <&rpmcc RPM_SMD_BB_CLK1>;
 2912 
 2913                         #clock-cells = <1>;
 2914                 };
 2915 
 2916                 usb3: usb@6af8800 {
 2917                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 2918                         reg = <0x06af8800 0x400>;
 2919                         #address-cells = <1>;
 2920                         #size-cells = <1>;
 2921                         ranges;
 2922 
 2923                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 2924                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 2925                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
 2926 
 2927                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 2928                                  <&gcc GCC_USB30_MASTER_CLK>,
 2929                                  <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 2930                                  <&gcc GCC_USB30_SLEEP_CLK>,
 2931                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
 2932                         clock-names = "cfg_noc",
 2933                                       "core",
 2934                                       "iface",
 2935                                       "sleep",
 2936                                       "mock_utmi";
 2937 
 2938                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 2939                                           <&gcc GCC_USB30_MASTER_CLK>;
 2940                         assigned-clock-rates = <19200000>, <120000000>;
 2941 
 2942                         interconnects = <&a2noc MASTER_USB3 &bimc SLAVE_EBI_CH0>,
 2943                                         <&bimc MASTER_AMPSS_M0 &snoc SLAVE_USB3>;
 2944                         interconnect-names = "usb-ddr", "apps-usb";
 2945 
 2946                         power-domains = <&gcc USB30_GDSC>;
 2947                         status = "disabled";
 2948 
 2949                         usb3_dwc3: usb@6a00000 {
 2950                                 compatible = "snps,dwc3";
 2951                                 reg = <0x06a00000 0xcc00>;
 2952                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 2953                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 2954                                 phy-names = "usb2-phy", "usb3-phy";
 2955                                 snps,dis_u2_susphy_quirk;
 2956                                 snps,dis_enblslpm_quirk;
 2957                         };
 2958                 };
 2959 
 2960                 usb3phy: phy@7410000 {
 2961                         compatible = "qcom,msm8996-qmp-usb3-phy";
 2962                         reg = <0x07410000 0x1c4>;
 2963                         #address-cells = <1>;
 2964                         #size-cells = <1>;
 2965                         ranges;
 2966 
 2967                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 2968                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 2969                                 <&gcc GCC_USB3_CLKREF_CLK>;
 2970                         clock-names = "aux", "cfg_ahb", "ref";
 2971 
 2972                         resets = <&gcc GCC_USB3_PHY_BCR>,
 2973                                 <&gcc GCC_USB3PHY_PHY_BCR>;
 2974                         reset-names = "phy", "common";
 2975                         status = "disabled";
 2976 
 2977                         ssusb_phy_0: phy@7410200 {
 2978                                 reg = <0x07410200 0x200>,
 2979                                       <0x07410400 0x130>,
 2980                                       <0x07410600 0x1a8>;
 2981                                 #phy-cells = <0>;
 2982 
 2983                                 #clock-cells = <0>;
 2984                                 clock-output-names = "usb3_phy_pipe_clk_src";
 2985                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 2986                                 clock-names = "pipe0";
 2987                         };
 2988                 };
 2989 
 2990                 hsusb_phy1: phy@7411000 {
 2991                         compatible = "qcom,msm8996-qusb2-phy";
 2992                         reg = <0x07411000 0x180>;
 2993                         #phy-cells = <0>;
 2994 
 2995                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 2996                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 2997                         clock-names = "cfg_ahb", "ref";
 2998 
 2999                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 3000                         nvmem-cells = <&qusb2p_hstx_trim>;
 3001                         status = "disabled";
 3002                 };
 3003 
 3004                 hsusb_phy2: phy@7412000 {
 3005                         compatible = "qcom,msm8996-qusb2-phy";
 3006                         reg = <0x07412000 0x180>;
 3007                         #phy-cells = <0>;
 3008 
 3009                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 3010                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
 3011                         clock-names = "cfg_ahb", "ref";
 3012 
 3013                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 3014                         nvmem-cells = <&qusb2s_hstx_trim>;
 3015                         status = "disabled";
 3016                 };
 3017 
 3018                 sdhc1: mmc@7464900 {
 3019                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
 3020                         reg = <0x07464900 0x11c>, <0x07464000 0x800>;
 3021                         reg-names = "hc_mem", "core_mem";
 3022 
 3023                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 3024                                         <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 3025                         interrupt-names = "hc_irq", "pwr_irq";
 3026 
 3027                         clock-names = "iface", "core", "xo";
 3028                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 3029                                 <&gcc GCC_SDCC1_APPS_CLK>,
 3030                                 <&rpmcc RPM_SMD_BB_CLK1>;
 3031                         resets = <&gcc GCC_SDCC1_BCR>;
 3032 
 3033                         pinctrl-names = "default", "sleep";
 3034                         pinctrl-0 = <&sdc1_state_on>;
 3035                         pinctrl-1 = <&sdc1_state_off>;
 3036 
 3037                         bus-width = <8>;
 3038                         non-removable;
 3039                         status = "disabled";
 3040                 };
 3041 
 3042                 sdhc2: mmc@74a4900 {
 3043                         compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
 3044                         reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
 3045                         reg-names = "hc_mem", "core_mem";
 3046 
 3047                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 3048                                       <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 3049                         interrupt-names = "hc_irq", "pwr_irq";
 3050 
 3051                         clock-names = "iface", "core", "xo";
 3052                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 3053                                 <&gcc GCC_SDCC2_APPS_CLK>,
 3054                                 <&rpmcc RPM_SMD_BB_CLK1>;
 3055                         resets = <&gcc GCC_SDCC2_BCR>;
 3056 
 3057                         pinctrl-names = "default", "sleep";
 3058                         pinctrl-0 = <&sdc2_state_on>;
 3059                         pinctrl-1 = <&sdc2_state_off>;
 3060 
 3061                         bus-width = <4>;
 3062                         status = "disabled";
 3063                  };
 3064 
 3065                 blsp1_dma: dma-controller@7544000 {
 3066                         compatible = "qcom,bam-v1.7.0";
 3067                         reg = <0x07544000 0x2b000>;
 3068                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 3069                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 3070                         clock-names = "bam_clk";
 3071                         qcom,controlled-remotely;
 3072                         #dma-cells = <1>;
 3073                         qcom,ee = <0>;
 3074                 };
 3075 
 3076                 blsp1_uart2: serial@7570000 {
 3077                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 3078                         reg = <0x07570000 0x1000>;
 3079                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 3080                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 3081                                  <&gcc GCC_BLSP1_AHB_CLK>;
 3082                         clock-names = "core", "iface";
 3083                         pinctrl-names = "default", "sleep";
 3084                         pinctrl-0 = <&blsp1_uart2_default>;
 3085                         pinctrl-1 = <&blsp1_uart2_sleep>;
 3086                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
 3087                         dma-names = "tx", "rx";
 3088                         status = "disabled";
 3089                 };
 3090 
 3091                 blsp1_spi1: spi@7575000 {
 3092                         compatible = "qcom,spi-qup-v2.2.1";
 3093                         reg = <0x07575000 0x600>;
 3094                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 3095                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 3096                                  <&gcc GCC_BLSP1_AHB_CLK>;
 3097                         clock-names = "core", "iface";
 3098                         pinctrl-names = "default", "sleep";
 3099                         pinctrl-0 = <&blsp1_spi1_default>;
 3100                         pinctrl-1 = <&blsp1_spi1_sleep>;
 3101                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 3102                         dma-names = "tx", "rx";
 3103                         #address-cells = <1>;
 3104                         #size-cells = <0>;
 3105                         status = "disabled";
 3106                 };
 3107 
 3108                 blsp1_i2c3: i2c@7577000 {
 3109                         compatible = "qcom,i2c-qup-v2.2.1";
 3110                         reg = <0x07577000 0x1000>;
 3111                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 3112                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 3113                                  <&gcc GCC_BLSP1_AHB_CLK>;
 3114                         clock-names = "core", "iface";
 3115                         pinctrl-names = "default", "sleep";
 3116                         pinctrl-0 = <&blsp1_i2c3_default>;
 3117                         pinctrl-1 = <&blsp1_i2c3_sleep>;
 3118                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
 3119                         dma-names = "tx", "rx";
 3120                         #address-cells = <1>;
 3121                         #size-cells = <0>;
 3122                         status = "disabled";
 3123                 };
 3124 
 3125                 blsp2_dma: dma-controller@7584000 {
 3126                         compatible = "qcom,bam-v1.7.0";
 3127                         reg = <0x07584000 0x2b000>;
 3128                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 3129                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 3130                         clock-names = "bam_clk";
 3131                         qcom,controlled-remotely;
 3132                         #dma-cells = <1>;
 3133                         qcom,ee = <0>;
 3134                 };
 3135 
 3136                 blsp2_uart2: serial@75b0000 {
 3137                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 3138                         reg = <0x075b0000 0x1000>;
 3139                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 3140                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 3141                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3142                         clock-names = "core", "iface";
 3143                         status = "disabled";
 3144                 };
 3145 
 3146                 blsp2_uart3: serial@75b1000 {
 3147                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 3148                         reg = <0x075b1000 0x1000>;
 3149                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 3150                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 3151                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3152                         clock-names = "core", "iface";
 3153                         status = "disabled";
 3154                 };
 3155 
 3156                 blsp2_i2c1: i2c@75b5000 {
 3157                         compatible = "qcom,i2c-qup-v2.2.1";
 3158                         reg = <0x075b5000 0x1000>;
 3159                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 3160                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
 3161                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3162                         clock-names = "core", "iface";
 3163                         pinctrl-names = "default", "sleep";
 3164                         pinctrl-0 = <&blsp2_i2c1_default>;
 3165                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 3166                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
 3167                         dma-names = "tx", "rx";
 3168                         #address-cells = <1>;
 3169                         #size-cells = <0>;
 3170                         status = "disabled";
 3171                 };
 3172 
 3173                 blsp2_i2c2: i2c@75b6000 {
 3174                         compatible = "qcom,i2c-qup-v2.2.1";
 3175                         reg = <0x075b6000 0x1000>;
 3176                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 3177                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
 3178                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3179                         clock-names = "core", "iface";
 3180                         pinctrl-names = "default", "sleep";
 3181                         pinctrl-0 = <&blsp2_i2c2_default>;
 3182                         pinctrl-1 = <&blsp2_i2c2_sleep>;
 3183                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
 3184                         dma-names = "tx", "rx";
 3185                         #address-cells = <1>;
 3186                         #size-cells = <0>;
 3187                         status = "disabled";
 3188                 };
 3189 
 3190                 blsp2_i2c3: i2c@75b7000 {
 3191                         compatible = "qcom,i2c-qup-v2.2.1";
 3192                         reg = <0x075b7000 0x1000>;
 3193                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 3194                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
 3195                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3196                         clock-names = "core", "iface";
 3197                         clock-frequency = <400000>;
 3198                         pinctrl-names = "default", "sleep";
 3199                         pinctrl-0 = <&blsp2_i2c3_default>;
 3200                         pinctrl-1 = <&blsp2_i2c3_sleep>;
 3201                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
 3202                         dma-names = "tx", "rx";
 3203                         #address-cells = <1>;
 3204                         #size-cells = <0>;
 3205                         status = "disabled";
 3206                 };
 3207 
 3208                 blsp2_i2c5: i2c@75b9000 {
 3209                         compatible = "qcom,i2c-qup-v2.2.1";
 3210                         reg = <0x75b9000 0x1000>;
 3211                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 3212                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
 3213                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3214                         clock-names = "core", "iface";
 3215                         pinctrl-names = "default";
 3216                         pinctrl-0 = <&blsp2_i2c5_default>;
 3217                         dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
 3218                         dma-names = "tx", "rx";
 3219                         #address-cells = <1>;
 3220                         #size-cells = <0>;
 3221                         status = "disabled";
 3222                 };
 3223 
 3224                 blsp2_i2c6: i2c@75ba000 {
 3225                         compatible = "qcom,i2c-qup-v2.2.1";
 3226                         reg = <0x75ba000 0x1000>;
 3227                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 3228                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
 3229                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3230                         clock-names = "core", "iface";
 3231                         pinctrl-names = "default", "sleep";
 3232                         pinctrl-0 = <&blsp2_i2c6_default>;
 3233                         pinctrl-1 = <&blsp2_i2c6_sleep>;
 3234                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
 3235                         dma-names = "tx", "rx";
 3236                         #address-cells = <1>;
 3237                         #size-cells = <0>;
 3238                         status = "disabled";
 3239                 };
 3240 
 3241                 blsp2_spi6: spi@75ba000{
 3242                         compatible = "qcom,spi-qup-v2.2.1";
 3243                         reg = <0x075ba000 0x600>;
 3244                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 3245                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 3246                                  <&gcc GCC_BLSP2_AHB_CLK>;
 3247                         clock-names = "core", "iface";
 3248                         pinctrl-names = "default", "sleep";
 3249                         pinctrl-0 = <&blsp2_spi6_default>;
 3250                         pinctrl-1 = <&blsp2_spi6_sleep>;
 3251                         dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
 3252                         dma-names = "tx", "rx";
 3253                         #address-cells = <1>;
 3254                         #size-cells = <0>;
 3255                         status = "disabled";
 3256                 };
 3257 
 3258                 usb2: usb@76f8800 {
 3259                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 3260                         reg = <0x076f8800 0x400>;
 3261                         #address-cells = <1>;
 3262                         #size-cells = <1>;
 3263                         ranges;
 3264 
 3265                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 3266                                 <&gcc GCC_USB20_MASTER_CLK>,
 3267                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 3268                                 <&gcc GCC_USB20_SLEEP_CLK>,
 3269                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 3270                         clock-names = "cfg_noc",
 3271                                       "core",
 3272                                       "iface",
 3273                                       "sleep",
 3274                                       "mock_utmi";
 3275 
 3276                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 3277                                           <&gcc GCC_USB20_MASTER_CLK>;
 3278                         assigned-clock-rates = <19200000>, <60000000>;
 3279 
 3280                         power-domains = <&gcc USB30_GDSC>;
 3281                         qcom,select-utmi-as-pipe-clk;
 3282                         status = "disabled";
 3283 
 3284                         usb2_dwc3: usb@7600000 {
 3285                                 compatible = "snps,dwc3";
 3286                                 reg = <0x07600000 0xcc00>;
 3287                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 3288                                 phys = <&hsusb_phy2>;
 3289                                 phy-names = "usb2-phy";
 3290                                 maximum-speed = "high-speed";
 3291                                 snps,dis_u2_susphy_quirk;
 3292                                 snps,dis_enblslpm_quirk;
 3293                         };
 3294                 };
 3295 
 3296                 slimbam: dma-controller@9184000 {
 3297                         compatible = "qcom,bam-v1.7.0";
 3298                         qcom,controlled-remotely;
 3299                         reg = <0x09184000 0x32000>;
 3300                         num-channels = <31>;
 3301                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
 3302                         #dma-cells = <1>;
 3303                         qcom,ee = <1>;
 3304                         qcom,num-ees = <2>;
 3305                 };
 3306 
 3307                 slim_msm: slim@91c0000 {
 3308                         compatible = "qcom,slim-ngd-v1.5.0";
 3309                         reg = <0x091c0000 0x2C000>;
 3310                         reg-names = "ctrl";
 3311                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
 3312                         dmas = <&slimbam 3>, <&slimbam 4>,
 3313                                 <&slimbam 5>, <&slimbam 6>;
 3314                         dma-names = "rx", "tx", "tx2", "rx2";
 3315                         #address-cells = <1>;
 3316                         #size-cells = <0>;
 3317                         ngd@1 {
 3318                                 reg = <1>;
 3319                                 #address-cells = <1>;
 3320                                 #size-cells = <1>;
 3321 
 3322                                 tasha_ifd: tas-ifd {
 3323                                         compatible = "slim217,1a0";
 3324                                         reg = <0 0>;
 3325                                 };
 3326 
 3327                                 wcd9335: codec@1{
 3328                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
 3329                                         pinctrl-names = "default";
 3330 
 3331                                         compatible = "slim217,1a0";
 3332                                         reg = <1 0>;
 3333 
 3334                                         interrupt-parent = <&tlmm>;
 3335                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
 3336                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
 3337                                         interrupt-names = "intr1", "intr2";
 3338                                         interrupt-controller;
 3339                                         #interrupt-cells = <1>;
 3340                                         reset-gpios = <&tlmm 64 0>;
 3341 
 3342                                         slim-ifc-dev = <&tasha_ifd>;
 3343 
 3344                                         #sound-dai-cells = <1>;
 3345                                 };
 3346                         };
 3347                 };
 3348 
 3349                 adsp_pil: remoteproc@9300000 {
 3350                         compatible = "qcom,msm8996-adsp-pil";
 3351                         reg = <0x09300000 0x80000>;
 3352 
 3353                         interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
 3354                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 3355                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 3356                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 3357                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 3358                         interrupt-names = "wdog", "fatal", "ready",
 3359                                           "handover", "stop-ack";
 3360 
 3361                         clocks = <&rpmcc RPM_SMD_BB_CLK1>;
 3362                         clock-names = "xo";
 3363 
 3364                         memory-region = <&adsp_mem>;
 3365 
 3366                         qcom,smem-states = <&adsp_smp2p_out 0>;
 3367                         qcom,smem-state-names = "stop";
 3368 
 3369                         power-domains = <&rpmpd MSM8996_VDDCX>;
 3370                         power-domain-names = "cx";
 3371 
 3372                         status = "disabled";
 3373 
 3374                         smd-edge {
 3375                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 3376 
 3377                                 label = "lpass";
 3378                                 mboxes = <&apcs_glb 8>;
 3379                                 qcom,smd-edge = <1>;
 3380                                 qcom,remote-pid = <2>;
 3381                                 #address-cells = <1>;
 3382                                 #size-cells = <0>;
 3383                                 apr {
 3384                                         power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
 3385                                         compatible = "qcom,apr-v2";
 3386                                         qcom,smd-channels = "apr_audio_svc";
 3387                                         qcom,domain = <APR_DOMAIN_ADSP>;
 3388                                         #address-cells = <1>;
 3389                                         #size-cells = <0>;
 3390 
 3391                                         q6core {
 3392                                                 reg = <APR_SVC_ADSP_CORE>;
 3393                                                 compatible = "qcom,q6core";
 3394                                         };
 3395 
 3396                                         q6afe: q6afe {
 3397                                                 compatible = "qcom,q6afe";
 3398                                                 reg = <APR_SVC_AFE>;
 3399                                                 q6afedai: dais {
 3400                                                         compatible = "qcom,q6afe-dais";
 3401                                                         #address-cells = <1>;
 3402                                                         #size-cells = <0>;
 3403                                                         #sound-dai-cells = <1>;
 3404                                                         hdmi@1 {
 3405                                                                 reg = <1>;
 3406                                                         };
 3407                                                 };
 3408                                         };
 3409 
 3410                                         q6asm: q6asm {
 3411                                                 compatible = "qcom,q6asm";
 3412                                                 reg = <APR_SVC_ASM>;
 3413                                                 q6asmdai: dais {
 3414                                                         compatible = "qcom,q6asm-dais";
 3415                                                         #address-cells = <1>;
 3416                                                         #size-cells = <0>;
 3417                                                         #sound-dai-cells = <1>;
 3418                                                         iommus = <&lpass_q6_smmu 1>;
 3419                                                 };
 3420                                         };
 3421 
 3422                                         q6adm: q6adm {
 3423                                                 compatible = "qcom,q6adm";
 3424                                                 reg = <APR_SVC_ADM>;
 3425                                                 q6routing: routing {
 3426                                                         compatible = "qcom,q6adm-routing";
 3427                                                         #sound-dai-cells = <0>;
 3428                                                 };
 3429                                         };
 3430                                 };
 3431 
 3432                         };
 3433                 };
 3434 
 3435                 apcs_glb: mailbox@9820000 {
 3436                         compatible = "qcom,msm8996-apcs-hmss-global";
 3437                         reg = <0x09820000 0x1000>;
 3438 
 3439                         #mbox-cells = <1>;
 3440                 };
 3441 
 3442                 timer@9840000 {
 3443                         #address-cells = <1>;
 3444                         #size-cells = <1>;
 3445                         ranges;
 3446                         compatible = "arm,armv7-timer-mem";
 3447                         reg = <0x09840000 0x1000>;
 3448                         clock-frequency = <19200000>;
 3449 
 3450                         frame@9850000 {
 3451                                 frame-number = <0>;
 3452                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 3453                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 3454                                 reg = <0x09850000 0x1000>,
 3455                                       <0x09860000 0x1000>;
 3456                         };
 3457 
 3458                         frame@9870000 {
 3459                                 frame-number = <1>;
 3460                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 3461                                 reg = <0x09870000 0x1000>;
 3462                                 status = "disabled";
 3463                         };
 3464 
 3465                         frame@9880000 {
 3466                                 frame-number = <2>;
 3467                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 3468                                 reg = <0x09880000 0x1000>;
 3469                                 status = "disabled";
 3470                         };
 3471 
 3472                         frame@9890000 {
 3473                                 frame-number = <3>;
 3474                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 3475                                 reg = <0x09890000 0x1000>;
 3476                                 status = "disabled";
 3477                         };
 3478 
 3479                         frame@98a0000 {
 3480                                 frame-number = <4>;
 3481                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 3482                                 reg = <0x098a0000 0x1000>;
 3483                                 status = "disabled";
 3484                         };
 3485 
 3486                         frame@98b0000 {
 3487                                 frame-number = <5>;
 3488                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 3489                                 reg = <0x098b0000 0x1000>;
 3490                                 status = "disabled";
 3491                         };
 3492 
 3493                         frame@98c0000 {
 3494                                 frame-number = <6>;
 3495                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 3496                                 reg = <0x098c0000 0x1000>;
 3497                                 status = "disabled";
 3498                         };
 3499                 };
 3500 
 3501                 saw3: syscon@9a10000 {
 3502                         compatible = "syscon";
 3503                         reg = <0x09a10000 0x1000>;
 3504                 };
 3505 
 3506                 intc: interrupt-controller@9bc0000 {
 3507                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
 3508                         #interrupt-cells = <3>;
 3509                         interrupt-controller;
 3510                         #redistributor-regions = <1>;
 3511                         redistributor-stride = <0x0 0x40000>;
 3512                         reg = <0x09bc0000 0x10000>,
 3513                               <0x09c00000 0x100000>;
 3514                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 3515                 };
 3516         };
 3517 
 3518         sound: sound {
 3519         };
 3520 
 3521         thermal-zones {
 3522                 cpu0-thermal {
 3523                         polling-delay-passive = <250>;
 3524                         polling-delay = <1000>;
 3525 
 3526                         thermal-sensors = <&tsens0 3>;
 3527 
 3528                         trips {
 3529                                 cpu0_alert0: trip-point0 {
 3530                                         temperature = <75000>;
 3531                                         hysteresis = <2000>;
 3532                                         type = "passive";
 3533                                 };
 3534 
 3535                                 cpu0_crit: cpu_crit {
 3536                                         temperature = <110000>;
 3537                                         hysteresis = <2000>;
 3538                                         type = "critical";
 3539                                 };
 3540                         };
 3541                 };
 3542 
 3543                 cpu1-thermal {
 3544                         polling-delay-passive = <250>;
 3545                         polling-delay = <1000>;
 3546 
 3547                         thermal-sensors = <&tsens0 5>;
 3548 
 3549                         trips {
 3550                                 cpu1_alert0: trip-point0 {
 3551                                         temperature = <75000>;
 3552                                         hysteresis = <2000>;
 3553                                         type = "passive";
 3554                                 };
 3555 
 3556                                 cpu1_crit: cpu_crit {
 3557                                         temperature = <110000>;
 3558                                         hysteresis = <2000>;
 3559                                         type = "critical";
 3560                                 };
 3561                         };
 3562                 };
 3563 
 3564                 cpu2-thermal {
 3565                         polling-delay-passive = <250>;
 3566                         polling-delay = <1000>;
 3567 
 3568                         thermal-sensors = <&tsens0 8>;
 3569 
 3570                         trips {
 3571                                 cpu2_alert0: trip-point0 {
 3572                                         temperature = <75000>;
 3573                                         hysteresis = <2000>;
 3574                                         type = "passive";
 3575                                 };
 3576 
 3577                                 cpu2_crit: cpu_crit {
 3578                                         temperature = <110000>;
 3579                                         hysteresis = <2000>;
 3580                                         type = "critical";
 3581                                 };
 3582                         };
 3583                 };
 3584 
 3585                 cpu3-thermal {
 3586                         polling-delay-passive = <250>;
 3587                         polling-delay = <1000>;
 3588 
 3589                         thermal-sensors = <&tsens0 10>;
 3590 
 3591                         trips {
 3592                                 cpu3_alert0: trip-point0 {
 3593                                         temperature = <75000>;
 3594                                         hysteresis = <2000>;
 3595                                         type = "passive";
 3596                                 };
 3597 
 3598                                 cpu3_crit: cpu_crit {
 3599                                         temperature = <110000>;
 3600                                         hysteresis = <2000>;
 3601                                         type = "critical";
 3602                                 };
 3603                         };
 3604                 };
 3605 
 3606                 gpu-top-thermal {
 3607                         polling-delay-passive = <250>;
 3608                         polling-delay = <1000>;
 3609 
 3610                         thermal-sensors = <&tsens1 6>;
 3611 
 3612                         trips {
 3613                                 gpu1_alert0: trip-point0 {
 3614                                         temperature = <90000>;
 3615                                         hysteresis = <2000>;
 3616                                         type = "passive";
 3617                                 };
 3618                         };
 3619 
 3620                         cooling-maps {
 3621                                 map0 {
 3622                                         trip = <&gpu1_alert0>;
 3623                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 3624                                 };
 3625                         };
 3626                 };
 3627 
 3628                 gpu-bottom-thermal {
 3629                         polling-delay-passive = <250>;
 3630                         polling-delay = <1000>;
 3631 
 3632                         thermal-sensors = <&tsens1 7>;
 3633 
 3634                         trips {
 3635                                 gpu2_alert0: trip-point0 {
 3636                                         temperature = <90000>;
 3637                                         hysteresis = <2000>;
 3638                                         type = "passive";
 3639                                 };
 3640                         };
 3641 
 3642                         cooling-maps {
 3643                                 map0 {
 3644                                         trip = <&gpu2_alert0>;
 3645                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 3646                                 };
 3647                         };
 3648                 };
 3649 
 3650                 m4m-thermal {
 3651                         polling-delay-passive = <250>;
 3652                         polling-delay = <1000>;
 3653 
 3654                         thermal-sensors = <&tsens0 1>;
 3655 
 3656                         trips {
 3657                                 m4m_alert0: trip-point0 {
 3658                                         temperature = <90000>;
 3659                                         hysteresis = <2000>;
 3660                                         type = "hot";
 3661                                 };
 3662                         };
 3663                 };
 3664 
 3665                 l3-or-venus-thermal {
 3666                         polling-delay-passive = <250>;
 3667                         polling-delay = <1000>;
 3668 
 3669                         thermal-sensors = <&tsens0 2>;
 3670 
 3671                         trips {
 3672                                 l3_or_venus_alert0: trip-point0 {
 3673                                         temperature = <90000>;
 3674                                         hysteresis = <2000>;
 3675                                         type = "hot";
 3676                                 };
 3677                         };
 3678                 };
 3679 
 3680                 cluster0-l2-thermal {
 3681                         polling-delay-passive = <250>;
 3682                         polling-delay = <1000>;
 3683 
 3684                         thermal-sensors = <&tsens0 7>;
 3685 
 3686                         trips {
 3687                                 cluster0_l2_alert0: trip-point0 {
 3688                                         temperature = <90000>;
 3689                                         hysteresis = <2000>;
 3690                                         type = "hot";
 3691                                 };
 3692                         };
 3693                 };
 3694 
 3695                 cluster1-l2-thermal {
 3696                         polling-delay-passive = <250>;
 3697                         polling-delay = <1000>;
 3698 
 3699                         thermal-sensors = <&tsens0 12>;
 3700 
 3701                         trips {
 3702                                 cluster1_l2_alert0: trip-point0 {
 3703                                         temperature = <90000>;
 3704                                         hysteresis = <2000>;
 3705                                         type = "hot";
 3706                                 };
 3707                         };
 3708                 };
 3709 
 3710                 camera-thermal {
 3711                         polling-delay-passive = <250>;
 3712                         polling-delay = <1000>;
 3713 
 3714                         thermal-sensors = <&tsens1 1>;
 3715 
 3716                         trips {
 3717                                 camera_alert0: trip-point0 {
 3718                                         temperature = <90000>;
 3719                                         hysteresis = <2000>;
 3720                                         type = "hot";
 3721                                 };
 3722                         };
 3723                 };
 3724 
 3725                 q6-dsp-thermal {
 3726                         polling-delay-passive = <250>;
 3727                         polling-delay = <1000>;
 3728 
 3729                         thermal-sensors = <&tsens1 2>;
 3730 
 3731                         trips {
 3732                                 q6_dsp_alert0: trip-point0 {
 3733                                         temperature = <90000>;
 3734                                         hysteresis = <2000>;
 3735                                         type = "hot";
 3736                                 };
 3737                         };
 3738                 };
 3739 
 3740                 mem-thermal {
 3741                         polling-delay-passive = <250>;
 3742                         polling-delay = <1000>;
 3743 
 3744                         thermal-sensors = <&tsens1 3>;
 3745 
 3746                         trips {
 3747                                 mem_alert0: trip-point0 {
 3748                                         temperature = <90000>;
 3749                                         hysteresis = <2000>;
 3750                                         type = "hot";
 3751                                 };
 3752                         };
 3753                 };
 3754 
 3755                 modemtx-thermal {
 3756                         polling-delay-passive = <250>;
 3757                         polling-delay = <1000>;
 3758 
 3759                         thermal-sensors = <&tsens1 4>;
 3760 
 3761                         trips {
 3762                                 modemtx_alert0: trip-point0 {
 3763                                         temperature = <90000>;
 3764                                         hysteresis = <2000>;
 3765                                         type = "hot";
 3766                                 };
 3767                         };
 3768                 };
 3769         };
 3770 
 3771         timer {
 3772                 compatible = "arm,armv8-timer";
 3773                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 3774                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 3775                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 3776                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 3777         };
 3778 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/msm8996.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/msm8996.dtsi
