msm8998.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
    3 
    4 #include <dt-bindings/interrupt-controller/arm-gic.h>
    5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
    6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
    7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
    8 #include <dt-bindings/clock/qcom,rpmcc.h>
    9 #include <dt-bindings/power/qcom-rpmpd.h>
   10 #include <dt-bindings/gpio/gpio.h>
   11 
   12 / {
   13         interrupt-parent = <&intc>;
   14 
   15         qcom,msm-id = <292 0x0>;
   16 
   17         #address-cells = <2>;
   18         #size-cells = <2>;
   19 
   20         chosen { };
   21 
   22         memory@80000000 {
   23                 device_type = "memory";
   24                 /* We expect the bootloader to fill in the reg */
   25                 reg = <0x0 0x80000000 0x0 0x0>;
   26         };
   27 
   28         reserved-memory {
   29                 #address-cells = <2>;
   30                 #size-cells = <2>;
   31                 ranges;
   32 
   33                 hyp_mem: memory@85800000 {
   34                         reg = <0x0 0x85800000 0x0 0x600000>;
   35                         no-map;
   36                 };
   37 
   38                 xbl_mem: memory@85e00000 {
   39                         reg = <0x0 0x85e00000 0x0 0x100000>;
   40                         no-map;
   41                 };
   42 
   43                 smem_mem: smem-mem@86000000 {
   44                         reg = <0x0 0x86000000 0x0 0x200000>;
   45                         no-map;
   46                 };
   47 
   48                 tz_mem: memory@86200000 {
   49                         reg = <0x0 0x86200000 0x0 0x2d00000>;
   50                         no-map;
   51                 };
   52 
   53                 rmtfs_mem: memory@88f00000 {
   54                         compatible = "qcom,rmtfs-mem";
   55                         reg = <0x0 0x88f00000 0x0 0x200000>;
   56                         no-map;
   57 
   58                         qcom,client-id = <1>;
   59                         qcom,vmid = <15>;
   60                 };
   61 
   62                 spss_mem: memory@8ab00000 {
   63                         reg = <0x0 0x8ab00000 0x0 0x700000>;
   64                         no-map;
   65                 };
   66 
   67                 adsp_mem: memory@8b200000 {
   68                         reg = <0x0 0x8b200000 0x0 0x1a00000>;
   69                         no-map;
   70                 };
   71 
   72                 mpss_mem: memory@8cc00000 {
   73                         reg = <0x0 0x8cc00000 0x0 0x7000000>;
   74                         no-map;
   75                 };
   76 
   77                 venus_mem: memory@93c00000 {
   78                         reg = <0x0 0x93c00000 0x0 0x500000>;
   79                         no-map;
   80                 };
   81 
   82                 mba_mem: memory@94100000 {
   83                         reg = <0x0 0x94100000 0x0 0x200000>;
   84                         no-map;
   85                 };
   86 
   87                 slpi_mem: memory@94300000 {
   88                         reg = <0x0 0x94300000 0x0 0xf00000>;
   89                         no-map;
   90                 };
   91 
   92                 ipa_fw_mem: memory@95200000 {
   93                         reg = <0x0 0x95200000 0x0 0x10000>;
   94                         no-map;
   95                 };
   96 
   97                 ipa_gsi_mem: memory@95210000 {
   98                         reg = <0x0 0x95210000 0x0 0x5000>;
   99                         no-map;
  100                 };
  101 
  102                 gpu_mem: memory@95600000 {
  103                         reg = <0x0 0x95600000 0x0 0x100000>;
  104                         no-map;
  105                 };
  106 
  107                 wlan_msa_mem: memory@95700000 {
  108                         reg = <0x0 0x95700000 0x0 0x100000>;
  109                         no-map;
  110                 };
  111         };
  112 
  113         clocks {
  114                 xo: xo-board {
  115                         compatible = "fixed-clock";
  116                         #clock-cells = <0>;
  117                         clock-frequency = <19200000>;
  118                         clock-output-names = "xo_board";
  119                 };
  120 
  121                 sleep_clk: sleep-clk {
  122                         compatible = "fixed-clock";
  123                         #clock-cells = <0>;
  124                         clock-frequency = <32764>;
  125                 };
  126         };
  127 
  128         cpus {
  129                 #address-cells = <2>;
  130                 #size-cells = <0>;
  131 
  132                 CPU0: cpu@0 {
  133                         device_type = "cpu";
  134                         compatible = "qcom,kryo280";
  135                         reg = <0x0 0x0>;
  136                         enable-method = "psci";
  137                         capacity-dmips-mhz = <1024>;
  138                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
  139                         next-level-cache = <&L2_0>;
  140                         L2_0: l2-cache {
  141                                 compatible = "cache";
  142                                 cache-level = <2>;
  143                         };
  144                 };
  145 
  146                 CPU1: cpu@1 {
  147                         device_type = "cpu";
  148                         compatible = "qcom,kryo280";
  149                         reg = <0x0 0x1>;
  150                         enable-method = "psci";
  151                         capacity-dmips-mhz = <1024>;
  152                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
  153                         next-level-cache = <&L2_0>;
  154                 };
  155 
  156                 CPU2: cpu@2 {
  157                         device_type = "cpu";
  158                         compatible = "qcom,kryo280";
  159                         reg = <0x0 0x2>;
  160                         enable-method = "psci";
  161                         capacity-dmips-mhz = <1024>;
  162                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
  163                         next-level-cache = <&L2_0>;
  164                 };
  165 
  166                 CPU3: cpu@3 {
  167                         device_type = "cpu";
  168                         compatible = "qcom,kryo280";
  169                         reg = <0x0 0x3>;
  170                         enable-method = "psci";
  171                         capacity-dmips-mhz = <1024>;
  172                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
  173                         next-level-cache = <&L2_0>;
  174                 };
  175 
  176                 CPU4: cpu@100 {
  177                         device_type = "cpu";
  178                         compatible = "qcom,kryo280";
  179                         reg = <0x0 0x100>;
  180                         enable-method = "psci";
  181                         capacity-dmips-mhz = <1536>;
  182                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
  183                         next-level-cache = <&L2_1>;
  184                         L2_1: l2-cache {
  185                                 compatible = "cache";
  186                                 cache-level = <2>;
  187                         };
  188                 };
  189 
  190                 CPU5: cpu@101 {
  191                         device_type = "cpu";
  192                         compatible = "qcom,kryo280";
  193                         reg = <0x0 0x101>;
  194                         enable-method = "psci";
  195                         capacity-dmips-mhz = <1536>;
  196                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
  197                         next-level-cache = <&L2_1>;
  198                 };
  199 
  200                 CPU6: cpu@102 {
  201                         device_type = "cpu";
  202                         compatible = "qcom,kryo280";
  203                         reg = <0x0 0x102>;
  204                         enable-method = "psci";
  205                         capacity-dmips-mhz = <1536>;
  206                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
  207                         next-level-cache = <&L2_1>;
  208                 };
  209 
  210                 CPU7: cpu@103 {
  211                         device_type = "cpu";
  212                         compatible = "qcom,kryo280";
  213                         reg = <0x0 0x103>;
  214                         enable-method = "psci";
  215                         capacity-dmips-mhz = <1536>;
  216                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
  217                         next-level-cache = <&L2_1>;
  218                 };
  219 
  220                 cpu-map {
  221                         cluster0 {
  222                                 core0 {
  223                                         cpu = <&CPU0>;
  224                                 };
  225 
  226                                 core1 {
  227                                         cpu = <&CPU1>;
  228                                 };
  229 
  230                                 core2 {
  231                                         cpu = <&CPU2>;
  232                                 };
  233 
  234                                 core3 {
  235                                         cpu = <&CPU3>;
  236                                 };
  237                         };
  238 
  239                         cluster1 {
  240                                 core0 {
  241                                         cpu = <&CPU4>;
  242                                 };
  243 
  244                                 core1 {
  245                                         cpu = <&CPU5>;
  246                                 };
  247 
  248                                 core2 {
  249                                         cpu = <&CPU6>;
  250                                 };
  251 
  252                                 core3 {
  253                                         cpu = <&CPU7>;
  254                                 };
  255                         };
  256                 };
  257 
  258                 idle-states {
  259                         entry-method = "psci";
  260 
  261                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
  262                                 compatible = "arm,idle-state";
  263                                 idle-state-name = "little-retention";
  264                                 /* CPU Retention (C2D), L2 Active */
  265                                 arm,psci-suspend-param = <0x00000002>;
  266                                 entry-latency-us = <81>;
  267                                 exit-latency-us = <86>;
  268                                 min-residency-us = <504>;
  269                         };
  270 
  271                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
  272                                 compatible = "arm,idle-state";
  273                                 idle-state-name = "little-power-collapse";
  274                                 /* CPU + L2 Power Collapse (C3, D4) */
  275                                 arm,psci-suspend-param = <0x40000003>;
  276                                 entry-latency-us = <814>;
  277                                 exit-latency-us = <4562>;
  278                                 min-residency-us = <9183>;
  279                                 local-timer-stop;
  280                         };
  281 
  282                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
  283                                 compatible = "arm,idle-state";
  284                                 idle-state-name = "big-retention";
  285                                 /* CPU Retention (C2D), L2 Active */
  286                                 arm,psci-suspend-param = <0x00000002>;
  287                                 entry-latency-us = <79>;
  288                                 exit-latency-us = <82>;
  289                                 min-residency-us = <1302>;
  290                         };
  291 
  292                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
  293                                 compatible = "arm,idle-state";
  294                                 idle-state-name = "big-power-collapse";
  295                                 /* CPU + L2 Power Collapse (C3, D4) */
  296                                 arm,psci-suspend-param = <0x40000003>;
  297                                 entry-latency-us = <724>;
  298                                 exit-latency-us = <2027>;
  299                                 min-residency-us = <9419>;
  300                                 local-timer-stop;
  301                         };
  302                 };
  303         };
  304 
  305         firmware {
  306                 scm {
  307                         compatible = "qcom,scm-msm8998", "qcom,scm";
  308                 };
  309         };
  310 
  311         tcsr_mutex: hwlock {
  312                 compatible = "qcom,tcsr-mutex";
  313                 syscon = <&tcsr_mutex_regs 0 0x1000>;
  314                 #hwlock-cells = <1>;
  315         };
  316 
  317         psci {
  318                 compatible = "arm,psci-1.0";
  319                 method = "smc";
  320         };
  321 
  322         rpm-glink {
  323                 compatible = "qcom,glink-rpm";
  324 
  325                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  326                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
  327                 mboxes = <&apcs_glb 0>;
  328 
  329                 rpm_requests: rpm-requests {
  330                         compatible = "qcom,rpm-msm8998";
  331                         qcom,glink-channels = "rpm_requests";
  332 
  333                         rpmcc: clock-controller {
  334                                 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
  335                                 #clock-cells = <1>;
  336                         };
  337 
  338                         rpmpd: power-controller {
  339                                 compatible = "qcom,msm8998-rpmpd";
  340                                 #power-domain-cells = <1>;
  341                                 operating-points-v2 = <&rpmpd_opp_table>;
  342 
  343                                 rpmpd_opp_table: opp-table {
  344                                         compatible = "operating-points-v2";
  345 
  346                                         rpmpd_opp_ret: opp1 {
  347                                                 opp-level = <RPM_SMD_LEVEL_RETENTION>;
  348                                         };
  349 
  350                                         rpmpd_opp_ret_plus: opp2 {
  351                                                 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
  352                                         };
  353 
  354                                         rpmpd_opp_min_svs: opp3 {
  355                                                 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
  356                                         };
  357 
  358                                         rpmpd_opp_low_svs: opp4 {
  359                                                 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
  360                                         };
  361 
  362                                         rpmpd_opp_svs: opp5 {
  363                                                 opp-level = <RPM_SMD_LEVEL_SVS>;
  364                                         };
  365 
  366                                         rpmpd_opp_svs_plus: opp6 {
  367                                                 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
  368                                         };
  369 
  370                                         rpmpd_opp_nom: opp7 {
  371                                                 opp-level = <RPM_SMD_LEVEL_NOM>;
  372                                         };
  373 
  374                                         rpmpd_opp_nom_plus: opp8 {
  375                                                 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
  376                                         };
  377 
  378                                         rpmpd_opp_turbo: opp9 {
  379                                                 opp-level = <RPM_SMD_LEVEL_TURBO>;
  380                                         };
  381 
  382                                         rpmpd_opp_turbo_plus: opp10 {
  383                                                 opp-level = <RPM_SMD_LEVEL_BINNING>;
  384                                         };
  385                                 };
  386                         };
  387                 };
  388         };
  389 
  390         smem {
  391                 compatible = "qcom,smem";
  392                 memory-region = <&smem_mem>;
  393                 hwlocks = <&tcsr_mutex 3>;
  394         };
  395 
  396         smp2p-lpass {
  397                 compatible = "qcom,smp2p";
  398                 qcom,smem = <443>, <429>;
  399 
  400                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
  401 
  402                 mboxes = <&apcs_glb 10>;
  403 
  404                 qcom,local-pid = <0>;
  405                 qcom,remote-pid = <2>;
  406 
  407                 adsp_smp2p_out: master-kernel {
  408                         qcom,entry-name = "master-kernel";
  409                         #qcom,smem-state-cells = <1>;
  410                 };
  411 
  412                 adsp_smp2p_in: slave-kernel {
  413                         qcom,entry-name = "slave-kernel";
  414 
  415                         interrupt-controller;
  416                         #interrupt-cells = <2>;
  417                 };
  418         };
  419 
  420         smp2p-mpss {
  421                 compatible = "qcom,smp2p";
  422                 qcom,smem = <435>, <428>;
  423                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
  424                 mboxes = <&apcs_glb 14>;
  425                 qcom,local-pid = <0>;
  426                 qcom,remote-pid = <1>;
  427 
  428                 modem_smp2p_out: master-kernel {
  429                         qcom,entry-name = "master-kernel";
  430                         #qcom,smem-state-cells = <1>;
  431                 };
  432 
  433                 modem_smp2p_in: slave-kernel {
  434                         qcom,entry-name = "slave-kernel";
  435                         interrupt-controller;
  436                         #interrupt-cells = <2>;
  437                 };
  438         };
  439 
  440         smp2p-slpi {
  441                 compatible = "qcom,smp2p";
  442                 qcom,smem = <481>, <430>;
  443                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
  444                 mboxes = <&apcs_glb 26>;
  445                 qcom,local-pid = <0>;
  446                 qcom,remote-pid = <3>;
  447 
  448                 slpi_smp2p_out: master-kernel {
  449                         qcom,entry-name = "master-kernel";
  450                         #qcom,smem-state-cells = <1>;
  451                 };
  452 
  453                 slpi_smp2p_in: slave-kernel {
  454                         qcom,entry-name = "slave-kernel";
  455                         interrupt-controller;
  456                         #interrupt-cells = <2>;
  457                 };
  458         };
  459 
  460         thermal-zones {
  461                 cpu0-thermal {
  462                         polling-delay-passive = <250>;
  463                         polling-delay = <1000>;
  464 
  465                         thermal-sensors = <&tsens0 1>;
  466 
  467                         trips {
  468                                 cpu0_alert0: trip-point0 {
  469                                         temperature = <75000>;
  470                                         hysteresis = <2000>;
  471                                         type = "passive";
  472                                 };
  473 
  474                                 cpu0_crit: cpu_crit {
  475                                         temperature = <110000>;
  476                                         hysteresis = <2000>;
  477                                         type = "critical";
  478                                 };
  479                         };
  480                 };
  481 
  482                 cpu1-thermal {
  483                         polling-delay-passive = <250>;
  484                         polling-delay = <1000>;
  485 
  486                         thermal-sensors = <&tsens0 2>;
  487 
  488                         trips {
  489                                 cpu1_alert0: trip-point0 {
  490                                         temperature = <75000>;
  491                                         hysteresis = <2000>;
  492                                         type = "passive";
  493                                 };
  494 
  495                                 cpu1_crit: cpu_crit {
  496                                         temperature = <110000>;
  497                                         hysteresis = <2000>;
  498                                         type = "critical";
  499                                 };
  500                         };
  501                 };
  502 
  503                 cpu2-thermal {
  504                         polling-delay-passive = <250>;
  505                         polling-delay = <1000>;
  506 
  507                         thermal-sensors = <&tsens0 3>;
  508 
  509                         trips {
  510                                 cpu2_alert0: trip-point0 {
  511                                         temperature = <75000>;
  512                                         hysteresis = <2000>;
  513                                         type = "passive";
  514                                 };
  515 
  516                                 cpu2_crit: cpu_crit {
  517                                         temperature = <110000>;
  518                                         hysteresis = <2000>;
  519                                         type = "critical";
  520                                 };
  521                         };
  522                 };
  523 
  524                 cpu3-thermal {
  525                         polling-delay-passive = <250>;
  526                         polling-delay = <1000>;
  527 
  528                         thermal-sensors = <&tsens0 4>;
  529 
  530                         trips {
  531                                 cpu3_alert0: trip-point0 {
  532                                         temperature = <75000>;
  533                                         hysteresis = <2000>;
  534                                         type = "passive";
  535                                 };
  536 
  537                                 cpu3_crit: cpu_crit {
  538                                         temperature = <110000>;
  539                                         hysteresis = <2000>;
  540                                         type = "critical";
  541                                 };
  542                         };
  543                 };
  544 
  545                 cpu4-thermal {
  546                         polling-delay-passive = <250>;
  547                         polling-delay = <1000>;
  548 
  549                         thermal-sensors = <&tsens0 7>;
  550 
  551                         trips {
  552                                 cpu4_alert0: trip-point0 {
  553                                         temperature = <75000>;
  554                                         hysteresis = <2000>;
  555                                         type = "passive";
  556                                 };
  557 
  558                                 cpu4_crit: cpu_crit {
  559                                         temperature = <110000>;
  560                                         hysteresis = <2000>;
  561                                         type = "critical";
  562                                 };
  563                         };
  564                 };
  565 
  566                 cpu5-thermal {
  567                         polling-delay-passive = <250>;
  568                         polling-delay = <1000>;
  569 
  570                         thermal-sensors = <&tsens0 8>;
  571 
  572                         trips {
  573                                 cpu5_alert0: trip-point0 {
  574                                         temperature = <75000>;
  575                                         hysteresis = <2000>;
  576                                         type = "passive";
  577                                 };
  578 
  579                                 cpu5_crit: cpu_crit {
  580                                         temperature = <110000>;
  581                                         hysteresis = <2000>;
  582                                         type = "critical";
  583                                 };
  584                         };
  585                 };
  586 
  587                 cpu6-thermal {
  588                         polling-delay-passive = <250>;
  589                         polling-delay = <1000>;
  590 
  591                         thermal-sensors = <&tsens0 9>;
  592 
  593                         trips {
  594                                 cpu6_alert0: trip-point0 {
  595                                         temperature = <75000>;
  596                                         hysteresis = <2000>;
  597                                         type = "passive";
  598                                 };
  599 
  600                                 cpu6_crit: cpu_crit {
  601                                         temperature = <110000>;
  602                                         hysteresis = <2000>;
  603                                         type = "critical";
  604                                 };
  605                         };
  606                 };
  607 
  608                 cpu7-thermal {
  609                         polling-delay-passive = <250>;
  610                         polling-delay = <1000>;
  611 
  612                         thermal-sensors = <&tsens0 10>;
  613 
  614                         trips {
  615                                 cpu7_alert0: trip-point0 {
  616                                         temperature = <75000>;
  617                                         hysteresis = <2000>;
  618                                         type = "passive";
  619                                 };
  620 
  621                                 cpu7_crit: cpu_crit {
  622                                         temperature = <110000>;
  623                                         hysteresis = <2000>;
  624                                         type = "critical";
  625                                 };
  626                         };
  627                 };
  628 
  629                 gpu-bottom-thermal {
  630                         polling-delay-passive = <250>;
  631                         polling-delay = <1000>;
  632 
  633                         thermal-sensors = <&tsens0 12>;
  634 
  635                         trips {
  636                                 gpu1_alert0: trip-point0 {
  637                                         temperature = <90000>;
  638                                         hysteresis = <2000>;
  639                                         type = "hot";
  640                                 };
  641                         };
  642                 };
  643 
  644                 gpu-top-thermal {
  645                         polling-delay-passive = <250>;
  646                         polling-delay = <1000>;
  647 
  648                         thermal-sensors = <&tsens0 13>;
  649 
  650                         trips {
  651                                 gpu2_alert0: trip-point0 {
  652                                         temperature = <90000>;
  653                                         hysteresis = <2000>;
  654                                         type = "hot";
  655                                 };
  656                         };
  657                 };
  658 
  659                 clust0-mhm-thermal {
  660                         polling-delay-passive = <250>;
  661                         polling-delay = <1000>;
  662 
  663                         thermal-sensors = <&tsens0 5>;
  664 
  665                         trips {
  666                                 cluster0_mhm_alert0: trip-point0 {
  667                                         temperature = <90000>;
  668                                         hysteresis = <2000>;
  669                                         type = "hot";
  670                                 };
  671                         };
  672                 };
  673 
  674                 clust1-mhm-thermal {
  675                         polling-delay-passive = <250>;
  676                         polling-delay = <1000>;
  677 
  678                         thermal-sensors = <&tsens0 6>;
  679 
  680                         trips {
  681                                 cluster1_mhm_alert0: trip-point0 {
  682                                         temperature = <90000>;
  683                                         hysteresis = <2000>;
  684                                         type = "hot";
  685                                 };
  686                         };
  687                 };
  688 
  689                 cluster1-l2-thermal {
  690                         polling-delay-passive = <250>;
  691                         polling-delay = <1000>;
  692 
  693                         thermal-sensors = <&tsens0 11>;
  694 
  695                         trips {
  696                                 cluster1_l2_alert0: trip-point0 {
  697                                         temperature = <90000>;
  698                                         hysteresis = <2000>;
  699                                         type = "hot";
  700                                 };
  701                         };
  702                 };
  703 
  704                 modem-thermal {
  705                         polling-delay-passive = <250>;
  706                         polling-delay = <1000>;
  707 
  708                         thermal-sensors = <&tsens1 1>;
  709 
  710                         trips {
  711                                 modem_alert0: trip-point0 {
  712                                         temperature = <90000>;
  713                                         hysteresis = <2000>;
  714                                         type = "hot";
  715                                 };
  716                         };
  717                 };
  718 
  719                 mem-thermal {
  720                         polling-delay-passive = <250>;
  721                         polling-delay = <1000>;
  722 
  723                         thermal-sensors = <&tsens1 2>;
  724 
  725                         trips {
  726                                 mem_alert0: trip-point0 {
  727                                         temperature = <90000>;
  728                                         hysteresis = <2000>;
  729                                         type = "hot";
  730                                 };
  731                         };
  732                 };
  733 
  734                 wlan-thermal {
  735                         polling-delay-passive = <250>;
  736                         polling-delay = <1000>;
  737 
  738                         thermal-sensors = <&tsens1 3>;
  739 
  740                         trips {
  741                                 wlan_alert0: trip-point0 {
  742                                         temperature = <90000>;
  743                                         hysteresis = <2000>;
  744                                         type = "hot";
  745                                 };
  746                         };
  747                 };
  748 
  749                 q6-dsp-thermal {
  750                         polling-delay-passive = <250>;
  751                         polling-delay = <1000>;
  752 
  753                         thermal-sensors = <&tsens1 4>;
  754 
  755                         trips {
  756                                 q6_dsp_alert0: trip-point0 {
  757                                         temperature = <90000>;
  758                                         hysteresis = <2000>;
  759                                         type = "hot";
  760                                 };
  761                         };
  762                 };
  763 
  764                 camera-thermal {
  765                         polling-delay-passive = <250>;
  766                         polling-delay = <1000>;
  767 
  768                         thermal-sensors = <&tsens1 5>;
  769 
  770                         trips {
  771                                 camera_alert0: trip-point0 {
  772                                         temperature = <90000>;
  773                                         hysteresis = <2000>;
  774                                         type = "hot";
  775                                 };
  776                         };
  777                 };
  778 
  779                 multimedia-thermal {
  780                         polling-delay-passive = <250>;
  781                         polling-delay = <1000>;
  782 
  783                         thermal-sensors = <&tsens1 6>;
  784 
  785                         trips {
  786                                 multimedia_alert0: trip-point0 {
  787                                         temperature = <90000>;
  788                                         hysteresis = <2000>;
  789                                         type = "hot";
  790                                 };
  791                         };
  792                 };
  793         };
  794 
  795         timer {
  796                 compatible = "arm,armv8-timer";
  797                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
  798                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
  799                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
  800                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
  801         };
  802 
  803         soc: soc {
  804                 #address-cells = <1>;
  805                 #size-cells = <1>;
  806                 ranges = <0 0 0 0xffffffff>;
  807                 compatible = "simple-bus";
  808 
  809                 gcc: clock-controller@100000 {
  810                         compatible = "qcom,gcc-msm8998";
  811                         #clock-cells = <1>;
  812                         #reset-cells = <1>;
  813                         #power-domain-cells = <1>;
  814                         reg = <0x00100000 0xb0000>;
  815 
  816                         clock-names = "xo", "sleep_clk";
  817                         clocks = <&xo>, <&sleep_clk>;
  818 
  819                         /*
  820                          * The hypervisor typically configures the memory region where these clocks
  821                          * reside as read-only for the HLOS. If the HLOS tried to enable or disable
  822                          * these clocks on a device with such configuration (e.g. because they are
  823                          * enabled but unused during boot-up), the device will most likely decide
  824                          * to reboot.
  825                          * In light of that, we are conservative here and we list all such clocks
  826                          * as protected. The board dts (or a user-supplied dts) can override the
  827                          * list of protected clocks if it differs from the norm, and it is in fact
  828                          * desired for the HLOS to manage these clocks
  829                          */
  830                         protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
  831                                            <SSC_XO>,
  832                                            <SSC_CNOC_AHBS_CLK>;
  833                 };
  834 
  835                 rpm_msg_ram: sram@778000 {
  836                         compatible = "qcom,rpm-msg-ram";
  837                         reg = <0x00778000 0x7000>;
  838                 };
  839 
  840                 qfprom: qfprom@784000 {
  841                         compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
  842                         reg = <0x00784000 0x621c>;
  843                         #address-cells = <1>;
  844                         #size-cells = <1>;
  845 
  846                         qusb2_hstx_trim: hstx-trim@23a {
  847                                 reg = <0x23a 0x1>;
  848                                 bits = <0 4>;
  849                         };
  850                 };
  851 
  852                 tsens0: thermal@10ab000 {
  853                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
  854                         reg = <0x010ab000 0x1000>, /* TM */
  855                               <0x010aa000 0x1000>; /* SROT */
  856                         #qcom,sensors = <14>;
  857                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
  858                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
  859                         interrupt-names = "uplow", "critical";
  860                         #thermal-sensor-cells = <1>;
  861                 };
  862 
  863                 tsens1: thermal@10ae000 {
  864                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
  865                         reg = <0x010ae000 0x1000>, /* TM */
  866                               <0x010ad000 0x1000>; /* SROT */
  867                         #qcom,sensors = <8>;
  868                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
  869                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
  870                         interrupt-names = "uplow", "critical";
  871                         #thermal-sensor-cells = <1>;
  872                 };
  873 
  874                 anoc1_smmu: iommu@1680000 {
  875                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
  876                         reg = <0x01680000 0x10000>;
  877                         #iommu-cells = <1>;
  878 
  879                         #global-interrupts = <0>;
  880                         interrupts =
  881                                 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
  882                                 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
  883                                 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
  884                                 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
  885                                 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
  886                                 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
  887                 };
  888 
  889                 anoc2_smmu: iommu@16c0000 {
  890                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
  891                         reg = <0x016c0000 0x40000>;
  892                         #iommu-cells = <1>;
  893 
  894                         #global-interrupts = <0>;
  895                         interrupts =
  896                                 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
  897                                 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
  898                                 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
  899                                 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
  900                                 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
  901                                 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
  902                                 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
  903                                 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
  904                                 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
  905                                 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
  906                 };
  907 
  908                 pcie0: pci@1c00000 {
  909                         compatible = "qcom,pcie-msm8996";
  910                         reg =   <0x01c00000 0x2000>,
  911                                 <0x1b000000 0xf1d>,
  912                                 <0x1b000f20 0xa8>,
  913                                 <0x1b100000 0x100000>;
  914                         reg-names = "parf", "dbi", "elbi", "config";
  915                         device_type = "pci";
  916                         linux,pci-domain = <0>;
  917                         bus-range = <0x00 0xff>;
  918                         #address-cells = <3>;
  919                         #size-cells = <2>;
  920                         num-lanes = <1>;
  921                         phys = <&pciephy>;
  922                         phy-names = "pciephy";
  923                         status = "disabled";
  924 
  925                         ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
  926                                  <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
  927 
  928                         #interrupt-cells = <1>;
  929                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  930                         interrupt-names = "msi";
  931                         interrupt-map-mask = <0 0 0 0x7>;
  932                         interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
  933                                         <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
  934                                         <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
  935                                         <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
  936 
  937                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
  938                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
  939                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
  940                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
  941                                  <&gcc GCC_PCIE_0_AUX_CLK>;
  942                         clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
  943 
  944                         power-domains = <&gcc PCIE_0_GDSC>;
  945                         iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
  946                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
  947                 };
  948 
  949                 pcie_phy: phy@1c06000 {
  950                         compatible = "qcom,msm8998-qmp-pcie-phy";
  951                         reg = <0x01c06000 0x18c>;
  952                         #address-cells = <1>;
  953                         #size-cells = <1>;
  954                         status = "disabled";
  955                         ranges;
  956 
  957                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
  958                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
  959                                  <&gcc GCC_PCIE_CLKREF_CLK>;
  960                         clock-names = "aux", "cfg_ahb", "ref";
  961 
  962                         resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
  963                         reset-names = "phy", "common";
  964 
  965                         vdda-phy-supply = <&vreg_l1a_0p875>;
  966                         vdda-pll-supply = <&vreg_l2a_1p2>;
  967 
  968                         pciephy: phy@1c06800 {
  969                                 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
  970                                 #phy-cells = <0>;
  971 
  972                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
  973                                 clock-names = "pipe0";
  974                                 clock-output-names = "pcie_0_pipe_clk_src";
  975                                 #clock-cells = <0>;
  976                         };
  977                 };
  978 
  979                 ufshc: ufshc@1da4000 {
  980                         compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
  981                         reg = <0x01da4000 0x2500>;
  982                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
  983                         phys = <&ufsphy_lanes>;
  984                         phy-names = "ufsphy";
  985                         lanes-per-direction = <2>;
  986                         power-domains = <&gcc UFS_GDSC>;
  987                         status = "disabled";
  988                         #reset-cells = <1>;
  989 
  990                         clock-names =
  991                                 "core_clk",
  992                                 "bus_aggr_clk",
  993                                 "iface_clk",
  994                                 "core_clk_unipro",
  995                                 "ref_clk",
  996                                 "tx_lane0_sync_clk",
  997                                 "rx_lane0_sync_clk",
  998                                 "rx_lane1_sync_clk";
  999                         clocks =
 1000                                 <&gcc GCC_UFS_AXI_CLK>,
 1001                                 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
 1002                                 <&gcc GCC_UFS_AHB_CLK>,
 1003                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 1004                                 <&rpmcc RPM_SMD_LN_BB_CLK1>,
 1005                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 1006                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
 1007                                 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
 1008                         freq-table-hz =
 1009                                 <50000000 200000000>,
 1010                                 <0 0>,
 1011                                 <0 0>,
 1012                                 <37500000 150000000>,
 1013                                 <0 0>,
 1014                                 <0 0>,
 1015                                 <0 0>,
 1016                                 <0 0>;
 1017 
 1018                         resets = <&gcc GCC_UFS_BCR>;
 1019                         reset-names = "rst";
 1020                 };
 1021 
 1022                 ufsphy: phy@1da7000 {
 1023                         compatible = "qcom,msm8998-qmp-ufs-phy";
 1024                         reg = <0x01da7000 0x18c>;
 1025                         #address-cells = <1>;
 1026                         #size-cells = <1>;
 1027                         status = "disabled";
 1028                         ranges;
 1029 
 1030                         clock-names =
 1031                                 "ref",
 1032                                 "ref_aux";
 1033                         clocks =
 1034                                 <&gcc GCC_UFS_CLKREF_CLK>,
 1035                                 <&gcc GCC_UFS_PHY_AUX_CLK>;
 1036 
 1037                         reset-names = "ufsphy";
 1038                         resets = <&ufshc 0>;
 1039 
 1040                         ufsphy_lanes: phy@1da7400 {
 1041                                 reg = <0x01da7400 0x128>,
 1042                                       <0x01da7600 0x1fc>,
 1043                                       <0x01da7c00 0x1dc>,
 1044                                       <0x01da7800 0x128>,
 1045                                       <0x01da7a00 0x1fc>;
 1046                                 #phy-cells = <0>;
 1047                         };
 1048                 };
 1049 
 1050                 tcsr_mutex_regs: syscon@1f40000 {
 1051                         compatible = "syscon";
 1052                         reg = <0x01f40000 0x40000>;
 1053                 };
 1054 
 1055                 tlmm: pinctrl@3400000 {
 1056                         compatible = "qcom,msm8998-pinctrl";
 1057                         reg = <0x03400000 0xc00000>;
 1058                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 1059                         gpio-controller;
 1060                         #gpio-cells = <2>;
 1061                         interrupt-controller;
 1062                         #interrupt-cells = <2>;
 1063 
 1064                         sdc2_on: sdc2-on {
 1065                                 clk {
 1066                                         pins = "sdc2_clk";
 1067                                         drive-strength = <16>;
 1068                                         bias-disable;
 1069                                 };
 1070 
 1071                                 cmd {
 1072                                         pins = "sdc2_cmd";
 1073                                         drive-strength = <10>;
 1074                                         bias-pull-up;
 1075                                 };
 1076 
 1077                                 data {
 1078                                         pins = "sdc2_data";
 1079                                         drive-strength = <10>;
 1080                                         bias-pull-up;
 1081                                 };
 1082                         };
 1083 
 1084                         sdc2_off: sdc2-off {
 1085                                 clk {
 1086                                         pins = "sdc2_clk";
 1087                                         drive-strength = <2>;
 1088                                         bias-disable;
 1089                                 };
 1090 
 1091                                 cmd {
 1092                                         pins = "sdc2_cmd";
 1093                                         drive-strength = <2>;
 1094                                         bias-pull-up;
 1095                                 };
 1096 
 1097                                 data {
 1098                                         pins = "sdc2_data";
 1099                                         drive-strength = <2>;
 1100                                         bias-pull-up;
 1101                                 };
 1102                         };
 1103 
 1104                         sdc2_cd: sdc2-cd {
 1105                                 pins = "gpio95";
 1106                                 function = "gpio";
 1107                                 bias-pull-up;
 1108                                 drive-strength = <2>;
 1109                         };
 1110 
 1111                         blsp1_uart3_on: blsp1-uart3-on {
 1112                                 tx {
 1113                                         pins = "gpio45";
 1114                                         function = "blsp_uart3_a";
 1115                                         drive-strength = <2>;
 1116                                         bias-disable;
 1117                                 };
 1118 
 1119                                 rx {
 1120                                         pins = "gpio46";
 1121                                         function = "blsp_uart3_a";
 1122                                         drive-strength = <2>;
 1123                                         bias-disable;
 1124                                 };
 1125 
 1126                                 cts {
 1127                                         pins = "gpio47";
 1128                                         function = "blsp_uart3_a";
 1129                                         drive-strength = <2>;
 1130                                         bias-disable;
 1131                                 };
 1132 
 1133                                 rfr {
 1134                                         pins = "gpio48";
 1135                                         function = "blsp_uart3_a";
 1136                                         drive-strength = <2>;
 1137                                         bias-disable;
 1138                                 };
 1139                         };
 1140 
 1141                         blsp1_i2c1_default: blsp1-i2c1-default {
 1142                                 pins = "gpio2", "gpio3";
 1143                                 function = "blsp_i2c1";
 1144                                 drive-strength = <2>;
 1145                                 bias-disable;
 1146                         };
 1147 
 1148                         blsp1_i2c1_sleep: blsp1-i2c1-sleep {
 1149                                 pins = "gpio2", "gpio3";
 1150                                 function = "blsp_i2c1";
 1151                                 drive-strength = <2>;
 1152                                 bias-pull-up;
 1153                         };
 1154 
 1155                         blsp1_i2c2_default: blsp1-i2c2-default {
 1156                                 pins = "gpio32", "gpio33";
 1157                                 function = "blsp_i2c2";
 1158                                 drive-strength = <2>;
 1159                                 bias-disable;
 1160                         };
 1161 
 1162                         blsp1_i2c2_sleep: blsp1-i2c2-sleep {
 1163                                 pins = "gpio32", "gpio33";
 1164                                 function = "blsp_i2c2";
 1165                                 drive-strength = <2>;
 1166                                 bias-pull-up;
 1167                         };
 1168 
 1169                         blsp1_i2c3_default: blsp1-i2c3-default {
 1170                                 pins = "gpio47", "gpio48";
 1171                                 function = "blsp_i2c3";
 1172                                 drive-strength = <2>;
 1173                                 bias-disable;
 1174                         };
 1175 
 1176                         blsp1_i2c3_sleep: blsp1-i2c3-sleep {
 1177                                 pins = "gpio47", "gpio48";
 1178                                 function = "blsp_i2c3";
 1179                                 drive-strength = <2>;
 1180                                 bias-pull-up;
 1181                         };
 1182 
 1183                         blsp1_i2c4_default: blsp1-i2c4-default {
 1184                                 pins = "gpio10", "gpio11";
 1185                                 function = "blsp_i2c4";
 1186                                 drive-strength = <2>;
 1187                                 bias-disable;
 1188                         };
 1189 
 1190                         blsp1_i2c4_sleep: blsp1-i2c4-sleep {
 1191                                 pins = "gpio10", "gpio11";
 1192                                 function = "blsp_i2c4";
 1193                                 drive-strength = <2>;
 1194                                 bias-pull-up;
 1195                         };
 1196 
 1197                         blsp1_i2c5_default: blsp1-i2c5-default {
 1198                                 pins = "gpio87", "gpio88";
 1199                                 function = "blsp_i2c5";
 1200                                 drive-strength = <2>;
 1201                                 bias-disable;
 1202                         };
 1203 
 1204                         blsp1_i2c5_sleep: blsp1-i2c5-sleep {
 1205                                 pins = "gpio87", "gpio88";
 1206                                 function = "blsp_i2c5";
 1207                                 drive-strength = <2>;
 1208                                 bias-pull-up;
 1209                         };
 1210 
 1211                         blsp1_i2c6_default: blsp1-i2c6-default {
 1212                                 pins = "gpio43", "gpio44";
 1213                                 function = "blsp_i2c6";
 1214                                 drive-strength = <2>;
 1215                                 bias-disable;
 1216                         };
 1217 
 1218                         blsp1_i2c6_sleep: blsp1-i2c6-sleep {
 1219                                 pins = "gpio43", "gpio44";
 1220                                 function = "blsp_i2c6";
 1221                                 drive-strength = <2>;
 1222                                 bias-pull-up;
 1223                         };
 1224                         /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */
 1225                         blsp2_i2c1_default: blsp2-i2c1-default {
 1226                                 pins = "gpio55", "gpio56";
 1227                                 function = "blsp_i2c7";
 1228                                 drive-strength = <2>;
 1229                                 bias-disable;
 1230                         };
 1231 
 1232                         blsp2_i2c1_sleep: blsp2-i2c1-sleep {
 1233                                 pins = "gpio55", "gpio56";
 1234                                 function = "blsp_i2c7";
 1235                                 drive-strength = <2>;
 1236                                 bias-pull-up;
 1237                         };
 1238 
 1239                         blsp2_i2c2_default: blsp2-i2c2-default {
 1240                                 pins = "gpio6", "gpio7";
 1241                                 function = "blsp_i2c8";
 1242                                 drive-strength = <2>;
 1243                                 bias-disable;
 1244                         };
 1245 
 1246                         blsp2_i2c2_sleep: blsp2-i2c2-sleep {
 1247                                 pins = "gpio6", "gpio7";
 1248                                 function = "blsp_i2c8";
 1249                                 drive-strength = <2>;
 1250                                 bias-pull-up;
 1251                         };
 1252 
 1253                         blsp2_i2c3_default: blsp2-i2c3-default {
 1254                                 pins = "gpio51", "gpio52";
 1255                                 function = "blsp_i2c9";
 1256                                 drive-strength = <2>;
 1257                                 bias-disable;
 1258                         };
 1259 
 1260                         blsp2_i2c3_sleep: blsp2-i2c3-sleep {
 1261                                 pins = "gpio51", "gpio52";
 1262                                 function = "blsp_i2c9";
 1263                                 drive-strength = <2>;
 1264                                 bias-pull-up;
 1265                         };
 1266 
 1267                         blsp2_i2c4_default: blsp2-i2c4-default {
 1268                                 pins = "gpio67", "gpio68";
 1269                                 function = "blsp_i2c10";
 1270                                 drive-strength = <2>;
 1271                                 bias-disable;
 1272                         };
 1273 
 1274                         blsp2_i2c4_sleep: blsp2-i2c4-sleep {
 1275                                 pins = "gpio67", "gpio68";
 1276                                 function = "blsp_i2c10";
 1277                                 drive-strength = <2>;
 1278                                 bias-pull-up;
 1279                         };
 1280 
 1281                         blsp2_i2c5_default: blsp2-i2c5-default {
 1282                                 pins = "gpio60", "gpio61";
 1283                                 function = "blsp_i2c11";
 1284                                 drive-strength = <2>;
 1285                                 bias-disable;
 1286                         };
 1287 
 1288                         blsp2_i2c5_sleep: blsp2-i2c5-sleep {
 1289                                 pins = "gpio60", "gpio61";
 1290                                 function = "blsp_i2c11";
 1291                                 drive-strength = <2>;
 1292                                 bias-pull-up;
 1293                         };
 1294 
 1295                         blsp2_i2c6_default: blsp2-i2c6-default {
 1296                                 pins = "gpio83", "gpio84";
 1297                                 function = "blsp_i2c12";
 1298                                 drive-strength = <2>;
 1299                                 bias-disable;
 1300                         };
 1301 
 1302                         blsp2_i2c6_sleep: blsp2-i2c6-sleep {
 1303                                 pins = "gpio83", "gpio84";
 1304                                 function = "blsp_i2c12";
 1305                                 drive-strength = <2>;
 1306                                 bias-pull-up;
 1307                         };
 1308                 };
 1309 
 1310                 remoteproc_mss: remoteproc@4080000 {
 1311                         compatible = "qcom,msm8998-mss-pil";
 1312                         reg = <0x04080000 0x100>, <0x04180000 0x20>;
 1313                         reg-names = "qdsp6", "rmb";
 1314 
 1315                         interrupts-extended =
 1316                                 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
 1317                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1318                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1319                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1320                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
 1321                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
 1322                         interrupt-names = "wdog", "fatal", "ready",
 1323                                           "handover", "stop-ack",
 1324                                           "shutdown-ack";
 1325 
 1326                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 1327                                  <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
 1328                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 1329                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
 1330                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
 1331                                  <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
 1332                                  <&rpmcc RPM_SMD_QDSS_CLK>,
 1333                                  <&rpmcc RPM_SMD_XO_CLK_SRC>;
 1334                         clock-names = "iface", "bus", "mem", "gpll0_mss",
 1335                                       "snoc_axi", "mnoc_axi", "qdss", "xo";
 1336 
 1337                         qcom,smem-states = <&modem_smp2p_out 0>;
 1338                         qcom,smem-state-names = "stop";
 1339 
 1340                         resets = <&gcc GCC_MSS_RESTART>;
 1341                         reset-names = "mss_restart";
 1342 
 1343                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
 1344 
 1345                         power-domains = <&rpmpd MSM8998_VDDCX>,
 1346                                         <&rpmpd MSM8998_VDDMX>;
 1347                         power-domain-names = "cx", "mx";
 1348 
 1349                         status = "disabled";
 1350 
 1351                         mba {
 1352                                 memory-region = <&mba_mem>;
 1353                         };
 1354 
 1355                         mpss {
 1356                                 memory-region = <&mpss_mem>;
 1357                         };
 1358 
 1359                         glink-edge {
 1360                                 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
 1361                                 label = "modem";
 1362                                 qcom,remote-pid = <1>;
 1363                                 mboxes = <&apcs_glb 15>;
 1364                         };
 1365                 };
 1366 
 1367                 adreno_gpu: gpu@5000000 {
 1368                         compatible = "qcom,adreno-540.1", "qcom,adreno";
 1369                         reg = <0x05000000 0x40000>;
 1370                         reg-names = "kgsl_3d0_reg_memory";
 1371 
 1372                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
 1373                                 <&gpucc RBBMTIMER_CLK>,
 1374                                 <&gcc GCC_BIMC_GFX_CLK>,
 1375                                 <&gcc GCC_GPU_BIMC_GFX_CLK>,
 1376                                 <&gpucc RBCPR_CLK>,
 1377                                 <&gpucc GFX3D_CLK>;
 1378                         clock-names = "iface",
 1379                                 "rbbmtimer",
 1380                                 "mem",
 1381                                 "mem_iface",
 1382                                 "rbcpr",
 1383                                 "core";
 1384 
 1385                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 1386                         iommus = <&adreno_smmu 0>;
 1387                         operating-points-v2 = <&gpu_opp_table>;
 1388                         power-domains = <&rpmpd MSM8998_VDDMX>;
 1389                         status = "disabled";
 1390 
 1391                         gpu_opp_table: opp-table {
 1392                                 compatible = "operating-points-v2";
 1393                                 opp-710000097 {
 1394                                         opp-hz = /bits/ 64 <710000097>;
 1395                                         opp-level = <RPM_SMD_LEVEL_TURBO>;
 1396                                         opp-supported-hw = <0xFF>;
 1397                                 };
 1398 
 1399                                 opp-670000048 {
 1400                                         opp-hz = /bits/ 64 <670000048>;
 1401                                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 1402                                         opp-supported-hw = <0xFF>;
 1403                                 };
 1404 
 1405                                 opp-596000097 {
 1406                                         opp-hz = /bits/ 64 <596000097>;
 1407                                         opp-level = <RPM_SMD_LEVEL_NOM>;
 1408                                         opp-supported-hw = <0xFF>;
 1409                                 };
 1410 
 1411                                 opp-515000097 {
 1412                                         opp-hz = /bits/ 64 <515000097>;
 1413                                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 1414                                         opp-supported-hw = <0xFF>;
 1415                                 };
 1416 
 1417                                 opp-414000000 {
 1418                                         opp-hz = /bits/ 64 <414000000>;
 1419                                         opp-level = <RPM_SMD_LEVEL_SVS>;
 1420                                         opp-supported-hw = <0xFF>;
 1421                                 };
 1422 
 1423                                 opp-342000000 {
 1424                                         opp-hz = /bits/ 64 <342000000>;
 1425                                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 1426                                         opp-supported-hw = <0xFF>;
 1427                                 };
 1428 
 1429                                 opp-257000000 {
 1430                                         opp-hz = /bits/ 64 <257000000>;
 1431                                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 1432                                         opp-supported-hw = <0xFF>;
 1433                                 };
 1434                         };
 1435                 };
 1436 
 1437                 adreno_smmu: iommu@5040000 {
 1438                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 1439                         reg = <0x05040000 0x10000>;
 1440                         clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
 1441                                  <&gcc GCC_BIMC_GFX_CLK>,
 1442                                  <&gcc GCC_GPU_BIMC_GFX_CLK>;
 1443                         clock-names = "iface", "mem", "mem_iface";
 1444 
 1445                         #global-interrupts = <0>;
 1446                         #iommu-cells = <1>;
 1447                         interrupts =
 1448                                 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 1449                                 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 1450                                 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
 1451                         /*
 1452                          * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
 1453                          * GPU-CX for SMMU but we need both of them up for Adreno.
 1454                          * Contemporarily, we also need to manage the VDDMX rpmpd
 1455                          * domain in the Adreno driver.
 1456                          * Enable GPU CX/GX GDSCs here so that we can manage the
 1457                          * SoC VDDMX RPM Power Domain in the Adreno driver.
 1458                          */
 1459                         power-domains = <&gpucc GPU_GX_GDSC>;
 1460                         status = "disabled";
 1461                 };
 1462 
 1463                 gpucc: clock-controller@5065000 {
 1464                         compatible = "qcom,msm8998-gpucc";
 1465                         #clock-cells = <1>;
 1466                         #reset-cells = <1>;
 1467                         #power-domain-cells = <1>;
 1468                         reg = <0x05065000 0x9000>;
 1469 
 1470                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 1471                                  <&gcc GPLL0_OUT_MAIN>;
 1472                         clock-names = "xo",
 1473                                       "gpll0";
 1474                 };
 1475 
 1476                 remoteproc_slpi: remoteproc@5800000 {
 1477                         compatible = "qcom,msm8998-slpi-pas";
 1478                         reg = <0x05800000 0x4040>;
 1479 
 1480                         interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
 1481                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1482                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1483                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1484                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 1485                         interrupt-names = "wdog", "fatal", "ready",
 1486                                           "handover", "stop-ack";
 1487 
 1488                         px-supply = <&vreg_lvs2a_1p8>;
 1489 
 1490                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 1491                                  <&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
 1492                         clock-names = "xo", "aggre2";
 1493 
 1494                         memory-region = <&slpi_mem>;
 1495 
 1496                         qcom,smem-states = <&slpi_smp2p_out 0>;
 1497                         qcom,smem-state-names = "stop";
 1498 
 1499                         power-domains = <&rpmpd MSM8998_SSCCX>;
 1500                         power-domain-names = "ssc_cx";
 1501 
 1502                         status = "disabled";
 1503 
 1504                         glink-edge {
 1505                                 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
 1506                                 label = "dsps";
 1507                                 qcom,remote-pid = <3>;
 1508                                 mboxes = <&apcs_glb 27>;
 1509                         };
 1510                 };
 1511 
 1512                 stm: stm@6002000 {
 1513                         compatible = "arm,coresight-stm", "arm,primecell";
 1514                         reg = <0x06002000 0x1000>,
 1515                               <0x16280000 0x180000>;
 1516                         reg-names = "stm-base", "stm-data-base";
 1517                         status = "disabled";
 1518 
 1519                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1520                         clock-names = "apb_pclk", "atclk";
 1521 
 1522                         out-ports {
 1523                                 port {
 1524                                         stm_out: endpoint {
 1525                                                 remote-endpoint = <&funnel0_in7>;
 1526                                         };
 1527                                 };
 1528                         };
 1529                 };
 1530 
 1531                 funnel1: funnel@6041000 {
 1532                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 1533                         reg = <0x06041000 0x1000>;
 1534                         status = "disabled";
 1535 
 1536                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1537                         clock-names = "apb_pclk", "atclk";
 1538 
 1539                         out-ports {
 1540                                 port {
 1541                                         funnel0_out: endpoint {
 1542                                                 remote-endpoint =
 1543                                                   <&merge_funnel_in0>;
 1544                                         };
 1545                                 };
 1546                         };
 1547 
 1548                         in-ports {
 1549                                 #address-cells = <1>;
 1550                                 #size-cells = <0>;
 1551 
 1552                                 port@7 {
 1553                                         reg = <7>;
 1554                                         funnel0_in7: endpoint {
 1555                                                 remote-endpoint = <&stm_out>;
 1556                                         };
 1557                                 };
 1558                         };
 1559                 };
 1560 
 1561                 funnel2: funnel@6042000 {
 1562                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 1563                         reg = <0x06042000 0x1000>;
 1564                         status = "disabled";
 1565 
 1566                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1567                         clock-names = "apb_pclk", "atclk";
 1568 
 1569                         out-ports {
 1570                                 port {
 1571                                         funnel1_out: endpoint {
 1572                                                 remote-endpoint =
 1573                                                   <&merge_funnel_in1>;
 1574                                         };
 1575                                 };
 1576                         };
 1577 
 1578                         in-ports {
 1579                                 #address-cells = <1>;
 1580                                 #size-cells = <0>;
 1581 
 1582                                 port@6 {
 1583                                         reg = <6>;
 1584                                         funnel1_in6: endpoint {
 1585                                                 remote-endpoint =
 1586                                                   <&apss_merge_funnel_out>;
 1587                                         };
 1588                                 };
 1589                         };
 1590                 };
 1591 
 1592                 funnel3: funnel@6045000 {
 1593                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 1594                         reg = <0x06045000 0x1000>;
 1595                         status = "disabled";
 1596 
 1597                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1598                         clock-names = "apb_pclk", "atclk";
 1599 
 1600                         out-ports {
 1601                                 port {
 1602                                         merge_funnel_out: endpoint {
 1603                                                 remote-endpoint =
 1604                                                   <&etf_in>;
 1605                                         };
 1606                                 };
 1607                         };
 1608 
 1609                         in-ports {
 1610                                 #address-cells = <1>;
 1611                                 #size-cells = <0>;
 1612 
 1613                                 port@0 {
 1614                                         reg = <0>;
 1615                                         merge_funnel_in0: endpoint {
 1616                                                 remote-endpoint =
 1617                                                   <&funnel0_out>;
 1618                                         };
 1619                                 };
 1620 
 1621                                 port@1 {
 1622                                         reg = <1>;
 1623                                         merge_funnel_in1: endpoint {
 1624                                                 remote-endpoint =
 1625                                                   <&funnel1_out>;
 1626                                         };
 1627                                 };
 1628                         };
 1629                 };
 1630 
 1631                 replicator1: replicator@6046000 {
 1632                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 1633                         reg = <0x06046000 0x1000>;
 1634                         status = "disabled";
 1635 
 1636                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1637                         clock-names = "apb_pclk", "atclk";
 1638 
 1639                         out-ports {
 1640                                 port {
 1641                                         replicator_out: endpoint {
 1642                                                 remote-endpoint = <&etr_in>;
 1643                                         };
 1644                                 };
 1645                         };
 1646 
 1647                         in-ports {
 1648                                 port {
 1649                                         replicator_in: endpoint {
 1650                                                 remote-endpoint = <&etf_out>;
 1651                                         };
 1652                                 };
 1653                         };
 1654                 };
 1655 
 1656                 etf: etf@6047000 {
 1657                         compatible = "arm,coresight-tmc", "arm,primecell";
 1658                         reg = <0x06047000 0x1000>;
 1659                         status = "disabled";
 1660 
 1661                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1662                         clock-names = "apb_pclk", "atclk";
 1663 
 1664                         out-ports {
 1665                                 port {
 1666                                         etf_out: endpoint {
 1667                                                 remote-endpoint =
 1668                                                   <&replicator_in>;
 1669                                         };
 1670                                 };
 1671                         };
 1672 
 1673                         in-ports {
 1674                                 port {
 1675                                         etf_in: endpoint {
 1676                                                 remote-endpoint =
 1677                                                   <&merge_funnel_out>;
 1678                                         };
 1679                                 };
 1680                         };
 1681                 };
 1682 
 1683                 etr: etr@6048000 {
 1684                         compatible = "arm,coresight-tmc", "arm,primecell";
 1685                         reg = <0x06048000 0x1000>;
 1686                         status = "disabled";
 1687 
 1688                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1689                         clock-names = "apb_pclk", "atclk";
 1690                         arm,scatter-gather;
 1691 
 1692                         in-ports {
 1693                                 port {
 1694                                         etr_in: endpoint {
 1695                                                 remote-endpoint =
 1696                                                   <&replicator_out>;
 1697                                         };
 1698                                 };
 1699                         };
 1700                 };
 1701 
 1702                 etm1: etm@7840000 {
 1703                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1704                         reg = <0x07840000 0x1000>;
 1705                         status = "disabled";
 1706 
 1707                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1708                         clock-names = "apb_pclk", "atclk";
 1709 
 1710                         cpu = <&CPU0>;
 1711 
 1712                         out-ports {
 1713                                 port {
 1714                                         etm0_out: endpoint {
 1715                                                 remote-endpoint =
 1716                                                   <&apss_funnel_in0>;
 1717                                         };
 1718                                 };
 1719                         };
 1720                 };
 1721 
 1722                 etm2: etm@7940000 {
 1723                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1724                         reg = <0x07940000 0x1000>;
 1725                         status = "disabled";
 1726 
 1727                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1728                         clock-names = "apb_pclk", "atclk";
 1729 
 1730                         cpu = <&CPU1>;
 1731 
 1732                         out-ports {
 1733                                 port {
 1734                                         etm1_out: endpoint {
 1735                                                 remote-endpoint =
 1736                                                   <&apss_funnel_in1>;
 1737                                         };
 1738                                 };
 1739                         };
 1740                 };
 1741 
 1742                 etm3: etm@7a40000 {
 1743                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1744                         reg = <0x07a40000 0x1000>;
 1745                         status = "disabled";
 1746 
 1747                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1748                         clock-names = "apb_pclk", "atclk";
 1749 
 1750                         cpu = <&CPU2>;
 1751 
 1752                         out-ports {
 1753                                 port {
 1754                                         etm2_out: endpoint {
 1755                                                 remote-endpoint =
 1756                                                   <&apss_funnel_in2>;
 1757                                         };
 1758                                 };
 1759                         };
 1760                 };
 1761 
 1762                 etm4: etm@7b40000 {
 1763                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1764                         reg = <0x07b40000 0x1000>;
 1765                         status = "disabled";
 1766 
 1767                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1768                         clock-names = "apb_pclk", "atclk";
 1769 
 1770                         cpu = <&CPU3>;
 1771 
 1772                         out-ports {
 1773                                 port {
 1774                                         etm3_out: endpoint {
 1775                                                 remote-endpoint =
 1776                                                   <&apss_funnel_in3>;
 1777                                         };
 1778                                 };
 1779                         };
 1780                 };
 1781 
 1782                 funnel4: funnel@7b60000 { /* APSS Funnel */
 1783                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1784                         reg = <0x07b60000 0x1000>;
 1785                         status = "disabled";
 1786 
 1787                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1788                         clock-names = "apb_pclk", "atclk";
 1789 
 1790                         out-ports {
 1791                                 port {
 1792                                         apss_funnel_out: endpoint {
 1793                                                 remote-endpoint =
 1794                                                   <&apss_merge_funnel_in>;
 1795                                         };
 1796                                 };
 1797                         };
 1798 
 1799                         in-ports {
 1800                                 #address-cells = <1>;
 1801                                 #size-cells = <0>;
 1802 
 1803                                 port@0 {
 1804                                         reg = <0>;
 1805                                         apss_funnel_in0: endpoint {
 1806                                                 remote-endpoint =
 1807                                                   <&etm0_out>;
 1808                                         };
 1809                                 };
 1810 
 1811                                 port@1 {
 1812                                         reg = <1>;
 1813                                         apss_funnel_in1: endpoint {
 1814                                                 remote-endpoint =
 1815                                                   <&etm1_out>;
 1816                                         };
 1817                                 };
 1818 
 1819                                 port@2 {
 1820                                         reg = <2>;
 1821                                         apss_funnel_in2: endpoint {
 1822                                                 remote-endpoint =
 1823                                                   <&etm2_out>;
 1824                                         };
 1825                                 };
 1826 
 1827                                 port@3 {
 1828                                         reg = <3>;
 1829                                         apss_funnel_in3: endpoint {
 1830                                                 remote-endpoint =
 1831                                                   <&etm3_out>;
 1832                                         };
 1833                                 };
 1834 
 1835                                 port@4 {
 1836                                         reg = <4>;
 1837                                         apss_funnel_in4: endpoint {
 1838                                                 remote-endpoint =
 1839                                                   <&etm4_out>;
 1840                                         };
 1841                                 };
 1842 
 1843                                 port@5 {
 1844                                         reg = <5>;
 1845                                         apss_funnel_in5: endpoint {
 1846                                                 remote-endpoint =
 1847                                                   <&etm5_out>;
 1848                                         };
 1849                                 };
 1850 
 1851                                 port@6 {
 1852                                         reg = <6>;
 1853                                         apss_funnel_in6: endpoint {
 1854                                                 remote-endpoint =
 1855                                                   <&etm6_out>;
 1856                                         };
 1857                                 };
 1858 
 1859                                 port@7 {
 1860                                         reg = <7>;
 1861                                         apss_funnel_in7: endpoint {
 1862                                                 remote-endpoint =
 1863                                                   <&etm7_out>;
 1864                                         };
 1865                                 };
 1866                         };
 1867                 };
 1868 
 1869                 funnel5: funnel@7b70000 {
 1870                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 1871                         reg = <0x07b70000 0x1000>;
 1872                         status = "disabled";
 1873 
 1874                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1875                         clock-names = "apb_pclk", "atclk";
 1876 
 1877                         out-ports {
 1878                                 port {
 1879                                         apss_merge_funnel_out: endpoint {
 1880                                                 remote-endpoint =
 1881                                                   <&funnel1_in6>;
 1882                                         };
 1883                                 };
 1884                         };
 1885 
 1886                         in-ports {
 1887                                 port {
 1888                                         apss_merge_funnel_in: endpoint {
 1889                                                 remote-endpoint =
 1890                                                   <&apss_funnel_out>;
 1891                                         };
 1892                                 };
 1893                         };
 1894                 };
 1895 
 1896                 etm5: etm@7c40000 {
 1897                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1898                         reg = <0x07c40000 0x1000>;
 1899                         status = "disabled";
 1900 
 1901                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1902                         clock-names = "apb_pclk", "atclk";
 1903 
 1904                         cpu = <&CPU4>;
 1905 
 1906                         port{
 1907                                 etm4_out: endpoint {
 1908                                         remote-endpoint = <&apss_funnel_in4>;
 1909                                 };
 1910                         };
 1911                 };
 1912 
 1913                 etm6: etm@7d40000 {
 1914                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1915                         reg = <0x07d40000 0x1000>;
 1916                         status = "disabled";
 1917 
 1918                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1919                         clock-names = "apb_pclk", "atclk";
 1920 
 1921                         cpu = <&CPU5>;
 1922 
 1923                         port{
 1924                                 etm5_out: endpoint {
 1925                                         remote-endpoint = <&apss_funnel_in5>;
 1926                                 };
 1927                         };
 1928                 };
 1929 
 1930                 etm7: etm@7e40000 {
 1931                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1932                         reg = <0x07e40000 0x1000>;
 1933                         status = "disabled";
 1934 
 1935                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1936                         clock-names = "apb_pclk", "atclk";
 1937 
 1938                         cpu = <&CPU6>;
 1939 
 1940                         port{
 1941                                 etm6_out: endpoint {
 1942                                         remote-endpoint = <&apss_funnel_in6>;
 1943                                 };
 1944                         };
 1945                 };
 1946 
 1947                 etm8: etm@7f40000 {
 1948                         compatible = "arm,coresight-etm4x", "arm,primecell";
 1949                         reg = <0x07f40000 0x1000>;
 1950                         status = "disabled";
 1951 
 1952                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
 1953                         clock-names = "apb_pclk", "atclk";
 1954 
 1955                         cpu = <&CPU7>;
 1956 
 1957                         port{
 1958                                 etm7_out: endpoint {
 1959                                         remote-endpoint = <&apss_funnel_in7>;
 1960                                 };
 1961                         };
 1962                 };
 1963 
 1964                 sram@290000 {
 1965                         compatible = "qcom,rpm-stats";
 1966                         reg = <0x00290000 0x10000>;
 1967                 };
 1968 
 1969                 spmi_bus: spmi@800f000 {
 1970                         compatible = "qcom,spmi-pmic-arb";
 1971                         reg =   <0x0800f000 0x1000>,
 1972                                 <0x08400000 0x1000000>,
 1973                                 <0x09400000 0x1000000>,
 1974                                 <0x0a400000 0x220000>,
 1975                                 <0x0800a000 0x3000>;
 1976                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 1977                         interrupt-names = "periph_irq";
 1978                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 1979                         qcom,ee = <0>;
 1980                         qcom,channel = <0>;
 1981                         #address-cells = <2>;
 1982                         #size-cells = <0>;
 1983                         interrupt-controller;
 1984                         #interrupt-cells = <4>;
 1985                         cell-index = <0>;
 1986                 };
 1987 
 1988                 usb3: usb@a8f8800 {
 1989                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
 1990                         reg = <0x0a8f8800 0x400>;
 1991                         status = "disabled";
 1992                         #address-cells = <1>;
 1993                         #size-cells = <1>;
 1994                         ranges;
 1995 
 1996                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
 1997                                  <&gcc GCC_USB30_MASTER_CLK>,
 1998                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
 1999                                  <&gcc GCC_USB30_SLEEP_CLK>,
 2000                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
 2001                         clock-names = "cfg_noc",
 2002                                       "core",
 2003                                       "iface",
 2004                                       "sleep",
 2005                                       "mock_utmi";
 2006 
 2007                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 2008                                           <&gcc GCC_USB30_MASTER_CLK>;
 2009                         assigned-clock-rates = <19200000>, <120000000>;
 2010 
 2011                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 2012                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 2013                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
 2014 
 2015                         power-domains = <&gcc USB_30_GDSC>;
 2016 
 2017                         resets = <&gcc GCC_USB_30_BCR>;
 2018 
 2019                         usb3_dwc3: usb@a800000 {
 2020                                 compatible = "snps,dwc3";
 2021                                 reg = <0x0a800000 0xcd00>;
 2022                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 2023                                 snps,dis_u2_susphy_quirk;
 2024                                 snps,dis_enblslpm_quirk;
 2025                                 phys = <&qusb2phy>, <&usb1_ssphy>;
 2026                                 phy-names = "usb2-phy", "usb3-phy";
 2027                                 snps,has-lpm-erratum;
 2028                                 snps,hird-threshold = /bits/ 8 <0x10>;
 2029                         };
 2030                 };
 2031 
 2032                 usb3phy: phy@c010000 {
 2033                         compatible = "qcom,msm8998-qmp-usb3-phy";
 2034                         reg = <0x0c010000 0x18c>;
 2035                         status = "disabled";
 2036                         #address-cells = <1>;
 2037                         #size-cells = <1>;
 2038                         ranges;
 2039 
 2040                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 2041                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 2042                                  <&gcc GCC_USB3_CLKREF_CLK>;
 2043                         clock-names = "aux", "cfg_ahb", "ref";
 2044 
 2045                         resets = <&gcc GCC_USB3_PHY_BCR>,
 2046                                  <&gcc GCC_USB3PHY_PHY_BCR>;
 2047                         reset-names = "phy", "common";
 2048 
 2049                         usb1_ssphy: phy@c010200 {
 2050                                 reg = <0xc010200 0x128>,
 2051                                       <0xc010400 0x200>,
 2052                                       <0xc010c00 0x20c>,
 2053                                       <0xc010600 0x128>,
 2054                                       <0xc010800 0x200>;
 2055                                 #phy-cells = <0>;
 2056                                 #clock-cells = <0>;
 2057                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 2058                                 clock-names = "pipe0";
 2059                                 clock-output-names = "usb3_phy_pipe_clk_src";
 2060                         };
 2061                 };
 2062 
 2063                 qusb2phy: phy@c012000 {
 2064                         compatible = "qcom,msm8998-qusb2-phy";
 2065                         reg = <0x0c012000 0x2a8>;
 2066                         status = "disabled";
 2067                         #phy-cells = <0>;
 2068 
 2069                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 2070                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 2071                         clock-names = "cfg_ahb", "ref";
 2072 
 2073                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 2074 
 2075                         nvmem-cells = <&qusb2_hstx_trim>;
 2076                 };
 2077 
 2078                 sdhc2: mmc@c0a4900 {
 2079                         compatible = "qcom,sdhci-msm-v4";
 2080                         reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
 2081                         reg-names = "hc_mem", "core_mem";
 2082 
 2083                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 2084                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 2085                         interrupt-names = "hc_irq", "pwr_irq";
 2086 
 2087                         clock-names = "iface", "core", "xo";
 2088                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 2089                                  <&gcc GCC_SDCC2_APPS_CLK>,
 2090                                  <&xo>;
 2091                         bus-width = <4>;
 2092                         status = "disabled";
 2093                 };
 2094 
 2095                 blsp1_dma: dma-controller@c144000 {
 2096                         compatible = "qcom,bam-v1.7.0";
 2097                         reg = <0x0c144000 0x25000>;
 2098                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 2099                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 2100                         clock-names = "bam_clk";
 2101                         #dma-cells = <1>;
 2102                         qcom,ee = <0>;
 2103                         qcom,controlled-remotely;
 2104                         num-channels = <18>;
 2105                         qcom,num-ees = <4>;
 2106                 };
 2107 
 2108                 blsp1_uart3: serial@c171000 {
 2109                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 2110                         reg = <0x0c171000 0x1000>;
 2111                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 2112                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 2113                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2114                         clock-names = "core", "iface";
 2115                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
 2116                         dma-names = "tx", "rx";
 2117                         pinctrl-names = "default";
 2118                         pinctrl-0 = <&blsp1_uart3_on>;
 2119                         status = "disabled";
 2120                 };
 2121 
 2122                 blsp1_i2c1: i2c@c175000 {
 2123                         compatible = "qcom,i2c-qup-v2.2.1";
 2124                         reg = <0x0c175000 0x600>;
 2125                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 2126 
 2127                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
 2128                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2129                         clock-names = "core", "iface";
 2130                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
 2131                         dma-names = "tx", "rx";
 2132                         pinctrl-names = "default", "sleep";
 2133                         pinctrl-0 = <&blsp1_i2c1_default>;
 2134                         pinctrl-1 = <&blsp1_i2c1_sleep>;
 2135                         clock-frequency = <400000>;
 2136 
 2137                         status = "disabled";
 2138                         #address-cells = <1>;
 2139                         #size-cells = <0>;
 2140                 };
 2141 
 2142                 blsp1_i2c2: i2c@c176000 {
 2143                         compatible = "qcom,i2c-qup-v2.2.1";
 2144                         reg = <0x0c176000 0x600>;
 2145                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 2146 
 2147                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 2148                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2149                         clock-names = "core", "iface";
 2150                         dmas = <&blsp1_dma 8>, <&blsp1_dma 9>;
 2151                         dma-names = "tx", "rx";
 2152                         pinctrl-names = "default", "sleep";
 2153                         pinctrl-0 = <&blsp1_i2c2_default>;
 2154                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 2155                         clock-frequency = <400000>;
 2156 
 2157                         status = "disabled";
 2158                         #address-cells = <1>;
 2159                         #size-cells = <0>;
 2160                 };
 2161 
 2162                 blsp1_i2c3: i2c@c177000 {
 2163                         compatible = "qcom,i2c-qup-v2.2.1";
 2164                         reg = <0x0c177000 0x600>;
 2165                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 2166 
 2167                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 2168                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2169                         clock-names = "core", "iface";
 2170                         dmas = <&blsp1_dma 10>, <&blsp1_dma 11>;
 2171                         dma-names = "tx", "rx";
 2172                         pinctrl-names = "default", "sleep";
 2173                         pinctrl-0 = <&blsp1_i2c3_default>;
 2174                         pinctrl-1 = <&blsp1_i2c3_sleep>;
 2175                         clock-frequency = <400000>;
 2176 
 2177                         status = "disabled";
 2178                         #address-cells = <1>;
 2179                         #size-cells = <0>;
 2180                 };
 2181 
 2182                 blsp1_i2c4: i2c@c178000 {
 2183                         compatible = "qcom,i2c-qup-v2.2.1";
 2184                         reg = <0x0c178000 0x600>;
 2185                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 2186 
 2187                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 2188                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2189                         clock-names = "core", "iface";
 2190                         dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
 2191                         dma-names = "tx", "rx";
 2192                         pinctrl-names = "default", "sleep";
 2193                         pinctrl-0 = <&blsp1_i2c4_default>;
 2194                         pinctrl-1 = <&blsp1_i2c4_sleep>;
 2195                         clock-frequency = <400000>;
 2196 
 2197                         status = "disabled";
 2198                         #address-cells = <1>;
 2199                         #size-cells = <0>;
 2200                 };
 2201 
 2202                 blsp1_i2c5: i2c@c179000 {
 2203                         compatible = "qcom,i2c-qup-v2.2.1";
 2204                         reg = <0x0c179000 0x600>;
 2205                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 2206 
 2207                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 2208                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2209                         clock-names = "core", "iface";
 2210                         dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
 2211                         dma-names = "tx", "rx";
 2212                         pinctrl-names = "default", "sleep";
 2213                         pinctrl-0 = <&blsp1_i2c5_default>;
 2214                         pinctrl-1 = <&blsp1_i2c5_sleep>;
 2215                         clock-frequency = <400000>;
 2216 
 2217                         status = "disabled";
 2218                         #address-cells = <1>;
 2219                         #size-cells = <0>;
 2220                 };
 2221 
 2222                 blsp1_i2c6: i2c@c17a000 {
 2223                         compatible = "qcom,i2c-qup-v2.2.1";
 2224                         reg = <0x0c17a000 0x600>;
 2225                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 2226 
 2227                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 2228                                  <&gcc GCC_BLSP1_AHB_CLK>;
 2229                         clock-names = "core", "iface";
 2230                         dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
 2231                         dma-names = "tx", "rx";
 2232                         pinctrl-names = "default", "sleep";
 2233                         pinctrl-0 = <&blsp1_i2c6_default>;
 2234                         pinctrl-1 = <&blsp1_i2c6_sleep>;
 2235                         clock-frequency = <400000>;
 2236 
 2237                         status = "disabled";
 2238                         #address-cells = <1>;
 2239                         #size-cells = <0>;
 2240                 };
 2241 
 2242                 blsp2_dma: dma-controller@c184000 {
 2243                         compatible = "qcom,bam-v1.7.0";
 2244                         reg = <0x0c184000 0x25000>;
 2245                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 2246                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 2247                         clock-names = "bam_clk";
 2248                         #dma-cells = <1>;
 2249                         qcom,ee = <0>;
 2250                         qcom,controlled-remotely;
 2251                         num-channels = <18>;
 2252                         qcom,num-ees = <4>;
 2253                 };
 2254 
 2255                 blsp2_uart1: serial@c1b0000 {
 2256                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 2257                         reg = <0x0c1b0000 0x1000>;
 2258                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 2259                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 2260                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2261                         clock-names = "core", "iface";
 2262                         status = "disabled";
 2263                 };
 2264 
 2265                 blsp2_i2c1: i2c@c1b5000 {
 2266                         compatible = "qcom,i2c-qup-v2.2.1";
 2267                         reg = <0x0c1b5000 0x600>;
 2268                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 2269 
 2270                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
 2271                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2272                         clock-names = "core", "iface";
 2273                         dmas = <&blsp2_dma 6>, <&blsp2_dma 7>;
 2274                         dma-names = "tx", "rx";
 2275                         pinctrl-names = "default", "sleep";
 2276                         pinctrl-0 = <&blsp2_i2c1_default>;
 2277                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 2278                         clock-frequency = <400000>;
 2279 
 2280                         status = "disabled";
 2281                         #address-cells = <1>;
 2282                         #size-cells = <0>;
 2283                 };
 2284 
 2285                 blsp2_i2c2: i2c@c1b6000 {
 2286                         compatible = "qcom,i2c-qup-v2.2.1";
 2287                         reg = <0x0c1b6000 0x600>;
 2288                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 2289 
 2290                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
 2291                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2292                         clock-names = "core", "iface";
 2293                         dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
 2294                         dma-names = "tx", "rx";
 2295                         pinctrl-names = "default", "sleep";
 2296                         pinctrl-0 = <&blsp2_i2c2_default>;
 2297                         pinctrl-1 = <&blsp2_i2c2_sleep>;
 2298                         clock-frequency = <400000>;
 2299 
 2300                         status = "disabled";
 2301                         #address-cells = <1>;
 2302                         #size-cells = <0>;
 2303                 };
 2304 
 2305                 blsp2_i2c3: i2c@c1b7000 {
 2306                         compatible = "qcom,i2c-qup-v2.2.1";
 2307                         reg = <0x0c1b7000 0x600>;
 2308                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 2309 
 2310                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
 2311                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2312                         clock-names = "core", "iface";
 2313                         dmas = <&blsp2_dma 10>, <&blsp2_dma 11>;
 2314                         dma-names = "tx", "rx";
 2315                         pinctrl-names = "default", "sleep";
 2316                         pinctrl-0 = <&blsp2_i2c3_default>;
 2317                         pinctrl-1 = <&blsp2_i2c3_sleep>;
 2318                         clock-frequency = <400000>;
 2319 
 2320                         status = "disabled";
 2321                         #address-cells = <1>;
 2322                         #size-cells = <0>;
 2323                 };
 2324 
 2325                 blsp2_i2c4: i2c@c1b8000 {
 2326                         compatible = "qcom,i2c-qup-v2.2.1";
 2327                         reg = <0x0c1b8000 0x600>;
 2328                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 2329 
 2330                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
 2331                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2332                         clock-names = "core", "iface";
 2333                         dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
 2334                         dma-names = "tx", "rx";
 2335                         pinctrl-names = "default", "sleep";
 2336                         pinctrl-0 = <&blsp2_i2c4_default>;
 2337                         pinctrl-1 = <&blsp2_i2c4_sleep>;
 2338                         clock-frequency = <400000>;
 2339 
 2340                         status = "disabled";
 2341                         #address-cells = <1>;
 2342                         #size-cells = <0>;
 2343                 };
 2344 
 2345                 blsp2_i2c5: i2c@c1b9000 {
 2346                         compatible = "qcom,i2c-qup-v2.2.1";
 2347                         reg = <0x0c1b9000 0x600>;
 2348                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 2349 
 2350                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
 2351                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2352                         clock-names = "core", "iface";
 2353                         dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
 2354                         dma-names = "tx", "rx";
 2355                         pinctrl-names = "default", "sleep";
 2356                         pinctrl-0 = <&blsp2_i2c5_default>;
 2357                         pinctrl-1 = <&blsp2_i2c5_sleep>;
 2358                         clock-frequency = <400000>;
 2359 
 2360                         status = "disabled";
 2361                         #address-cells = <1>;
 2362                         #size-cells = <0>;
 2363                 };
 2364 
 2365                 blsp2_i2c6: i2c@c1ba000 {
 2366                         compatible = "qcom,i2c-qup-v2.2.1";
 2367                         reg = <0x0c1ba000 0x600>;
 2368                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 2369 
 2370                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
 2371                                  <&gcc GCC_BLSP2_AHB_CLK>;
 2372                         clock-names = "core", "iface";
 2373                         dmas = <&blsp2_dma 16>, <&blsp2_dma 17>;
 2374                         dma-names = "tx", "rx";
 2375                         pinctrl-names = "default", "sleep";
 2376                         pinctrl-0 = <&blsp2_i2c6_default>;
 2377                         pinctrl-1 = <&blsp2_i2c6_sleep>;
 2378                         clock-frequency = <400000>;
 2379 
 2380                         status = "disabled";
 2381                         #address-cells = <1>;
 2382                         #size-cells = <0>;
 2383                 };
 2384 
 2385                 mmcc: clock-controller@c8c0000 {
 2386                         compatible = "qcom,mmcc-msm8998";
 2387                         #clock-cells = <1>;
 2388                         #reset-cells = <1>;
 2389                         #power-domain-cells = <1>;
 2390                         reg = <0xc8c0000 0x40000>;
 2391 
 2392                         clock-names = "xo",
 2393                                       "gpll0",
 2394                                       "dsi0dsi",
 2395                                       "dsi0byte",
 2396                                       "dsi1dsi",
 2397                                       "dsi1byte",
 2398                                       "hdmipll",
 2399                                       "dplink",
 2400                                       "dpvco",
 2401                                       "core_bi_pll_test_se";
 2402                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 2403                                  <&gcc GCC_MMSS_GPLL0_CLK>,
 2404                                  <0>,
 2405                                  <0>,
 2406                                  <0>,
 2407                                  <0>,
 2408                                  <0>,
 2409                                  <0>,
 2410                                  <0>,
 2411                                  <0>;
 2412                 };
 2413 
 2414                 mmss_smmu: iommu@cd00000 {
 2415                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 2416                         reg = <0x0cd00000 0x40000>;
 2417                         #iommu-cells = <1>;
 2418 
 2419                         clocks = <&mmcc MNOC_AHB_CLK>,
 2420                                  <&mmcc BIMC_SMMU_AHB_CLK>,
 2421                                  <&rpmcc RPM_SMD_MMAXI_CLK>,
 2422                                  <&mmcc BIMC_SMMU_AXI_CLK>;
 2423                         clock-names = "iface-mm", "iface-smmu",
 2424                                       "bus-mm", "bus-smmu";
 2425 
 2426                         #global-interrupts = <0>;
 2427                         interrupts =
 2428                                 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 2429                                 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 2430                                 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 2431                                 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
 2432                                 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 2433                                 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 2434                                 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 2435                                 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 2436                                 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 2437                                 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 2438                                 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 2439                                 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 2440                                 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 2441                                 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 2442                                 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 2443                                 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 2444                                 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 2445                                 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 2446                                 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 2447                                 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 2448                 };
 2449 
 2450                 remoteproc_adsp: remoteproc@17300000 {
 2451                         compatible = "qcom,msm8998-adsp-pas";
 2452                         reg = <0x17300000 0x4040>;
 2453 
 2454                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 2455                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 2456                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 2457                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 2458                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 2459                         interrupt-names = "wdog", "fatal", "ready",
 2460                                           "handover", "stop-ack";
 2461 
 2462                         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
 2463                         clock-names = "xo";
 2464 
 2465                         memory-region = <&adsp_mem>;
 2466 
 2467                         qcom,smem-states = <&adsp_smp2p_out 0>;
 2468                         qcom,smem-state-names = "stop";
 2469 
 2470                         power-domains = <&rpmpd MSM8998_VDDCX>;
 2471                         power-domain-names = "cx";
 2472 
 2473                         status = "disabled";
 2474 
 2475                         glink-edge {
 2476                                 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
 2477                                 label = "lpass";
 2478                                 qcom,remote-pid = <2>;
 2479                                 mboxes = <&apcs_glb 9>;
 2480                         };
 2481                 };
 2482 
 2483                 apcs_glb: mailbox@17911000 {
 2484                         compatible = "qcom,msm8998-apcs-hmss-global";
 2485                         reg = <0x17911000 0x1000>;
 2486 
 2487                         #mbox-cells = <1>;
 2488                 };
 2489 
 2490                 timer@17920000 {
 2491                         #address-cells = <1>;
 2492                         #size-cells = <1>;
 2493                         ranges;
 2494                         compatible = "arm,armv7-timer-mem";
 2495                         reg = <0x17920000 0x1000>;
 2496 
 2497                         frame@17921000 {
 2498                                 frame-number = <0>;
 2499                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 2500                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 2501                                 reg = <0x17921000 0x1000>,
 2502                                       <0x17922000 0x1000>;
 2503                         };
 2504 
 2505                         frame@17923000 {
 2506                                 frame-number = <1>;
 2507                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 2508                                 reg = <0x17923000 0x1000>;
 2509                                 status = "disabled";
 2510                         };
 2511 
 2512                         frame@17924000 {
 2513                                 frame-number = <2>;
 2514                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 2515                                 reg = <0x17924000 0x1000>;
 2516                                 status = "disabled";
 2517                         };
 2518 
 2519                         frame@17925000 {
 2520                                 frame-number = <3>;
 2521                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 2522                                 reg = <0x17925000 0x1000>;
 2523                                 status = "disabled";
 2524                         };
 2525 
 2526                         frame@17926000 {
 2527                                 frame-number = <4>;
 2528                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 2529                                 reg = <0x17926000 0x1000>;
 2530                                 status = "disabled";
 2531                         };
 2532 
 2533                         frame@17927000 {
 2534                                 frame-number = <5>;
 2535                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 2536                                 reg = <0x17927000 0x1000>;
 2537                                 status = "disabled";
 2538                         };
 2539 
 2540                         frame@17928000 {
 2541                                 frame-number = <6>;
 2542                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 2543                                 reg = <0x17928000 0x1000>;
 2544                                 status = "disabled";
 2545                         };
 2546                 };
 2547 
 2548                 intc: interrupt-controller@17a00000 {
 2549                         compatible = "arm,gic-v3";
 2550                         reg = <0x17a00000 0x10000>,       /* GICD */
 2551                               <0x17b00000 0x100000>;      /* GICR * 8 */
 2552                         #interrupt-cells = <3>;
 2553                         #address-cells = <1>;
 2554                         #size-cells = <1>;
 2555                         ranges;
 2556                         interrupt-controller;
 2557                         #redistributor-regions = <1>;
 2558                         redistributor-stride = <0x0 0x20000>;
 2559                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 2560                 };
 2561 
 2562                 wifi: wifi@18800000 {
 2563                         compatible = "qcom,wcn3990-wifi";
 2564                         status = "disabled";
 2565                         reg = <0x18800000 0x800000>;
 2566                         reg-names = "membase";
 2567                         memory-region = <&wlan_msa_mem>;
 2568                         clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
 2569                         clock-names = "cxo_ref_clk_pin";
 2570                         interrupts =
 2571                                 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
 2572                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
 2573                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
 2574                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 2575                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 2576                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 2577                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
 2578                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 2579                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 2580                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 2581                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 2582                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
 2583                         iommus = <&anoc2_smmu 0x1900>,
 2584                                  <&anoc2_smmu 0x1901>;
 2585                         qcom,snoc-host-cap-8bit-quirk;
 2586                 };
 2587         };
 2588 };
Cache object: 35530fc4b7870edbba93b1e30dc30a76
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/msm8998.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/msm8998.dtsi
