qcs404.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 // Copyright (c) 2018, Linaro Limited
    3 
    4 #include <dt-bindings/interrupt-controller/arm-gic.h>
    5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
    6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
    7 #include <dt-bindings/clock/qcom,rpmcc.h>
    8 #include <dt-bindings/power/qcom-rpmpd.h>
    9 #include <dt-bindings/thermal/thermal.h>
   10 
   11 / {
   12         interrupt-parent = <&intc>;
   13 
   14         #address-cells = <2>;
   15         #size-cells = <2>;
   16 
   17         chosen { };
   18 
   19         clocks {
   20                 xo_board: xo-board {
   21                         compatible = "fixed-clock";
   22                         #clock-cells = <0>;
   23                         clock-frequency = <19200000>;
   24                 };
   25 
   26                 sleep_clk: sleep-clk {
   27                         compatible = "fixed-clock";
   28                         #clock-cells = <0>;
   29                         clock-frequency = <32768>;
   30                 };
   31         };
   32 
   33         cpus {
   34                 #address-cells = <1>;
   35                 #size-cells = <0>;
   36 
   37                 CPU0: cpu@100 {
   38                         device_type = "cpu";
   39                         compatible = "arm,cortex-a53";
   40                         reg = <0x100>;
   41                         enable-method = "psci";
   42                         cpu-idle-states = <&CPU_SLEEP_0>;
   43                         next-level-cache = <&L2_0>;
   44                         #cooling-cells = <2>;
   45                         clocks = <&apcs_glb>;
   46                         operating-points-v2 = <&cpu_opp_table>;
   47                         power-domains = <&cpr>;
   48                         power-domain-names = "cpr";
   49                 };
   50 
   51                 CPU1: cpu@101 {
   52                         device_type = "cpu";
   53                         compatible = "arm,cortex-a53";
   54                         reg = <0x101>;
   55                         enable-method = "psci";
   56                         cpu-idle-states = <&CPU_SLEEP_0>;
   57                         next-level-cache = <&L2_0>;
   58                         #cooling-cells = <2>;
   59                         clocks = <&apcs_glb>;
   60                         operating-points-v2 = <&cpu_opp_table>;
   61                         power-domains = <&cpr>;
   62                         power-domain-names = "cpr";
   63                 };
   64 
   65                 CPU2: cpu@102 {
   66                         device_type = "cpu";
   67                         compatible = "arm,cortex-a53";
   68                         reg = <0x102>;
   69                         enable-method = "psci";
   70                         cpu-idle-states = <&CPU_SLEEP_0>;
   71                         next-level-cache = <&L2_0>;
   72                         #cooling-cells = <2>;
   73                         clocks = <&apcs_glb>;
   74                         operating-points-v2 = <&cpu_opp_table>;
   75                         power-domains = <&cpr>;
   76                         power-domain-names = "cpr";
   77                 };
   78 
   79                 CPU3: cpu@103 {
   80                         device_type = "cpu";
   81                         compatible = "arm,cortex-a53";
   82                         reg = <0x103>;
   83                         enable-method = "psci";
   84                         cpu-idle-states = <&CPU_SLEEP_0>;
   85                         next-level-cache = <&L2_0>;
   86                         #cooling-cells = <2>;
   87                         clocks = <&apcs_glb>;
   88                         operating-points-v2 = <&cpu_opp_table>;
   89                         power-domains = <&cpr>;
   90                         power-domain-names = "cpr";
   91                 };
   92 
   93                 L2_0: l2-cache {
   94                         compatible = "cache";
   95                         cache-level = <2>;
   96                 };
   97 
   98                 idle-states {
   99                         entry-method = "psci";
  100 
  101                         CPU_SLEEP_0: cpu-sleep-0 {
  102                                 compatible = "arm,idle-state";
  103                                 idle-state-name = "standalone-power-collapse";
  104                                 arm,psci-suspend-param = <0x40000003>;
  105                                 entry-latency-us = <125>;
  106                                 exit-latency-us = <180>;
  107                                 min-residency-us = <595>;
  108                                 local-timer-stop;
  109                         };
  110                 };
  111         };
  112 
  113         cpu_opp_table: opp-table-cpu {
  114                 compatible = "operating-points-v2-kryo-cpu";
  115                 opp-shared;
  116 
  117                 opp-1094400000 {
  118                         opp-hz = /bits/ 64 <1094400000>;
  119                         required-opps = <&cpr_opp1>;
  120                 };
  121                 opp-1248000000 {
  122                         opp-hz = /bits/ 64 <1248000000>;
  123                         required-opps = <&cpr_opp2>;
  124                 };
  125                 opp-1401600000 {
  126                         opp-hz = /bits/ 64 <1401600000>;
  127                         required-opps = <&cpr_opp3>;
  128                 };
  129         };
  130 
  131         cpr_opp_table: opp-table-cpr {
  132                 compatible = "operating-points-v2-qcom-level";
  133 
  134                 cpr_opp1: opp1 {
  135                         opp-level = <1>;
  136                         qcom,opp-fuse-level = <1>;
  137                 };
  138                 cpr_opp2: opp2 {
  139                         opp-level = <2>;
  140                         qcom,opp-fuse-level = <2>;
  141                 };
  142                 cpr_opp3: opp3 {
  143                         opp-level = <3>;
  144                         qcom,opp-fuse-level = <3>;
  145                 };
  146         };
  147 
  148         firmware {
  149                 scm: scm {
  150                         compatible = "qcom,scm-qcs404", "qcom,scm";
  151                         #reset-cells = <1>;
  152                 };
  153         };
  154 
  155         memory@80000000 {
  156                 device_type = "memory";
  157                 /* We expect the bootloader to fill in the size */
  158                 reg = <0 0x80000000 0 0>;
  159         };
  160 
  161         psci {
  162                 compatible = "arm,psci-1.0";
  163                 method = "smc";
  164         };
  165 
  166         reserved-memory {
  167                 #address-cells = <2>;
  168                 #size-cells = <2>;
  169                 ranges;
  170 
  171                 tz_apps_mem: memory@85900000 {
  172                         reg = <0 0x85900000 0 0x500000>;
  173                         no-map;
  174                 };
  175 
  176                 xbl_mem: memory@85e00000 {
  177                         reg = <0 0x85e00000 0 0x100000>;
  178                         no-map;
  179                 };
  180 
  181                 smem_region: memory@85f00000 {
  182                         reg = <0 0x85f00000 0 0x200000>;
  183                         no-map;
  184                 };
  185 
  186                 tz_mem: memory@86100000 {
  187                         reg = <0 0x86100000 0 0x300000>;
  188                         no-map;
  189                 };
  190 
  191                 wlan_fw_mem: memory@86400000 {
  192                         reg = <0 0x86400000 0 0x1100000>;
  193                         no-map;
  194                 };
  195 
  196                 adsp_fw_mem: memory@87500000 {
  197                         reg = <0 0x87500000 0 0x1a00000>;
  198                         no-map;
  199                 };
  200 
  201                 cdsp_fw_mem: memory@88f00000 {
  202                         reg = <0 0x88f00000 0 0x600000>;
  203                         no-map;
  204                 };
  205 
  206                 wlan_msa_mem: memory@89500000 {
  207                         reg = <0 0x89500000 0 0x100000>;
  208                         no-map;
  209                 };
  210 
  211                 uefi_mem: memory@9f800000 {
  212                         reg = <0 0x9f800000 0 0x800000>;
  213                         no-map;
  214                 };
  215         };
  216 
  217         rpm-glink {
  218                 compatible = "qcom,glink-rpm";
  219 
  220                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
  221                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
  222                 mboxes = <&apcs_glb 0>;
  223 
  224                 rpm_requests: glink-channel {
  225                         compatible = "qcom,rpm-qcs404";
  226                         qcom,glink-channels = "rpm_requests";
  227 
  228                         rpmcc: clock-controller {
  229                                 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc";
  230                                 #clock-cells = <1>;
  231                         };
  232 
  233                         rpmpd: power-controller {
  234                                 compatible = "qcom,qcs404-rpmpd";
  235                                 #power-domain-cells = <1>;
  236                                 operating-points-v2 = <&rpmpd_opp_table>;
  237 
  238                                 rpmpd_opp_table: opp-table {
  239                                         compatible = "operating-points-v2";
  240 
  241                                         rpmpd_opp_ret: opp1 {
  242                                                 opp-level = <16>;
  243                                         };
  244 
  245                                         rpmpd_opp_ret_plus: opp2 {
  246                                                 opp-level = <32>;
  247                                         };
  248 
  249                                         rpmpd_opp_min_svs: opp3 {
  250                                                 opp-level = <48>;
  251                                         };
  252 
  253                                         rpmpd_opp_low_svs: opp4 {
  254                                                 opp-level = <64>;
  255                                         };
  256 
  257                                         rpmpd_opp_svs: opp5 {
  258                                                 opp-level = <128>;
  259                                         };
  260 
  261                                         rpmpd_opp_svs_plus: opp6 {
  262                                                 opp-level = <192>;
  263                                         };
  264 
  265                                         rpmpd_opp_nom: opp7 {
  266                                                 opp-level = <256>;
  267                                         };
  268 
  269                                         rpmpd_opp_nom_plus: opp8 {
  270                                                 opp-level = <320>;
  271                                         };
  272 
  273                                         rpmpd_opp_turbo: opp9 {
  274                                                 opp-level = <384>;
  275                                         };
  276 
  277                                         rpmpd_opp_turbo_no_cpr: opp10 {
  278                                                 opp-level = <416>;
  279                                         };
  280 
  281                                         rpmpd_opp_turbo_plus: opp11 {
  282                                                 opp-level = <512>;
  283                                         };
  284                                 };
  285                         };
  286                 };
  287         };
  288 
  289         smem {
  290                 compatible = "qcom,smem";
  291 
  292                 memory-region = <&smem_region>;
  293                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
  294 
  295                 hwlocks = <&tcsr_mutex 3>;
  296         };
  297 
  298         tcsr_mutex: hwlock {
  299                 compatible = "qcom,tcsr-mutex";
  300                 syscon = <&tcsr_mutex_regs 0 0x1000>;
  301                 #hwlock-cells = <1>;
  302         };
  303 
  304         soc: soc@0 {
  305                 #address-cells = <1>;
  306                 #size-cells = <1>;
  307                 ranges = <0 0 0 0xffffffff>;
  308                 compatible = "simple-bus";
  309 
  310                 turingcc: clock-controller@800000 {
  311                         compatible = "qcom,qcs404-turingcc";
  312                         reg = <0x00800000 0x30000>;
  313                         clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
  314 
  315                         #clock-cells = <1>;
  316                         #reset-cells = <1>;
  317 
  318                         status = "disabled";
  319                 };
  320 
  321                 rpm_msg_ram: sram@60000 {
  322                         compatible = "qcom,rpm-msg-ram";
  323                         reg = <0x00060000 0x6000>;
  324                 };
  325 
  326                 usb3_phy: phy@78000 {
  327                         compatible = "qcom,usb-ss-28nm-phy";
  328                         reg = <0x00078000 0x400>;
  329                         #phy-cells = <0>;
  330                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
  331                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
  332                                  <&gcc GCC_USB3_PHY_PIPE_CLK>;
  333                         clock-names = "ref", "ahb", "pipe";
  334                         resets = <&gcc GCC_USB3_PHY_BCR>,
  335                                  <&gcc GCC_USB3PHY_PHY_BCR>;
  336                         reset-names = "com", "phy";
  337                         status = "disabled";
  338                 };
  339 
  340                 usb2_phy_prim: phy@7a000 {
  341                         compatible = "qcom,usb-hs-28nm-femtophy";
  342                         reg = <0x0007a000 0x200>;
  343                         #phy-cells = <0>;
  344                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
  345                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
  346                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
  347                         clock-names = "ref", "ahb", "sleep";
  348                         resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
  349                                  <&gcc GCC_USB2A_PHY_BCR>;
  350                         reset-names = "phy", "por";
  351                         status = "disabled";
  352                 };
  353 
  354                 usb2_phy_sec: phy@7c000 {
  355                         compatible = "qcom,usb-hs-28nm-femtophy";
  356                         reg = <0x0007c000 0x200>;
  357                         #phy-cells = <0>;
  358                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
  359                                  <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
  360                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
  361                         clock-names = "ref", "ahb", "sleep";
  362                         resets = <&gcc GCC_QUSB2_PHY_BCR>,
  363                                  <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
  364                         reset-names = "phy", "por";
  365                         status = "disabled";
  366                 };
  367 
  368                 qfprom: qfprom@a4000 {
  369                         compatible = "qcom,qcs404-qfprom", "qcom,qfprom";
  370                         reg = <0x000a4000 0x1000>;
  371                         #address-cells = <1>;
  372                         #size-cells = <1>;
  373                         tsens_caldata: caldata@d0 {
  374                                 reg = <0x1f8 0x14>;
  375                         };
  376                         cpr_efuse_speedbin: speedbin@13c {
  377                                 reg = <0x13c 0x4>;
  378                                 bits = <2 3>;
  379                         };
  380                         cpr_efuse_quot_offset1: qoffset1@231 {
  381                                 reg = <0x231 0x4>;
  382                                 bits = <4 7>;
  383                         };
  384                         cpr_efuse_quot_offset2: qoffset2@232 {
  385                                 reg = <0x232 0x4>;
  386                                 bits = <3 7>;
  387                         };
  388                         cpr_efuse_quot_offset3: qoffset3@233 {
  389                                 reg = <0x233 0x4>;
  390                                 bits = <2 7>;
  391                         };
  392                         cpr_efuse_init_voltage1: ivoltage1@229 {
  393                                 reg = <0x229 0x4>;
  394                                 bits = <4 6>;
  395                         };
  396                         cpr_efuse_init_voltage2: ivoltage2@22a {
  397                                 reg = <0x22a 0x4>;
  398                                 bits = <2 6>;
  399                         };
  400                         cpr_efuse_init_voltage3: ivoltage3@22b {
  401                                 reg = <0x22b 0x4>;
  402                                 bits = <0 6>;
  403                         };
  404                         cpr_efuse_quot1: quot1@22b {
  405                                 reg = <0x22b 0x4>;
  406                                 bits = <6 12>;
  407                         };
  408                         cpr_efuse_quot2: quot2@22d {
  409                                 reg = <0x22d 0x4>;
  410                                 bits = <2 12>;
  411                         };
  412                         cpr_efuse_quot3: quot3@230 {
  413                                 reg = <0x230 0x4>;
  414                                 bits = <0 12>;
  415                         };
  416                         cpr_efuse_ring1: ring1@228 {
  417                                 reg = <0x228 0x4>;
  418                                 bits = <0 3>;
  419                         };
  420                         cpr_efuse_ring2: ring2@228 {
  421                                 reg = <0x228 0x4>;
  422                                 bits = <4 3>;
  423                         };
  424                         cpr_efuse_ring3: ring3@229 {
  425                                 reg = <0x229 0x4>;
  426                                 bits = <0 3>;
  427                         };
  428                         cpr_efuse_revision: revision@218 {
  429                                 reg = <0x218 0x4>;
  430                                 bits = <3 3>;
  431                         };
  432                 };
  433 
  434                 rng: rng@e3000 {
  435                         compatible = "qcom,prng-ee";
  436                         reg = <0x000e3000 0x1000>;
  437                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
  438                         clock-names = "core";
  439                 };
  440 
  441                 bimc: interconnect@400000 {
  442                         reg = <0x00400000 0x80000>;
  443                         compatible = "qcom,qcs404-bimc";
  444                         #interconnect-cells = <1>;
  445                         clock-names = "bus", "bus_a";
  446                         clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
  447                                 <&rpmcc RPM_SMD_BIMC_A_CLK>;
  448                 };
  449 
  450                 tsens: thermal-sensor@4a9000 {
  451                         compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
  452                         reg = <0x004a9000 0x1000>, /* TM */
  453                               <0x004a8000 0x1000>; /* SROT */
  454                         nvmem-cells = <&tsens_caldata>;
  455                         nvmem-cell-names = "calib";
  456                         #qcom,sensors = <10>;
  457                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
  458                         interrupt-names = "uplow";
  459                         #thermal-sensor-cells = <1>;
  460                 };
  461 
  462                 pcnoc: interconnect@500000 {
  463                         reg = <0x00500000 0x15080>;
  464                         compatible = "qcom,qcs404-pcnoc";
  465                         #interconnect-cells = <1>;
  466                         clock-names = "bus", "bus_a";
  467                         clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
  468                                 <&rpmcc RPM_SMD_PNOC_A_CLK>;
  469                 };
  470 
  471                 snoc: interconnect@580000 {
  472                         reg = <0x00580000 0x23080>;
  473                         compatible = "qcom,qcs404-snoc";
  474                         #interconnect-cells = <1>;
  475                         clock-names = "bus", "bus_a";
  476                         clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
  477                                 <&rpmcc RPM_SMD_SNOC_A_CLK>;
  478                 };
  479 
  480                 remoteproc_cdsp: remoteproc@b00000 {
  481                         compatible = "qcom,qcs404-cdsp-pas";
  482                         reg = <0x00b00000 0x4040>;
  483 
  484                         interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
  485                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  486                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  487                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  488                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  489                         interrupt-names = "wdog", "fatal", "ready",
  490                                           "handover", "stop-ack";
  491 
  492                         clocks = <&xo_board>,
  493                                  <&gcc GCC_CDSP_CFG_AHB_CLK>,
  494                                  <&gcc GCC_CDSP_TBU_CLK>,
  495                                  <&gcc GCC_BIMC_CDSP_CLK>,
  496                                  <&turingcc TURING_WRAPPER_AON_CLK>,
  497                                  <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
  498                                  <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
  499                                  <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
  500                         clock-names = "xo",
  501                                       "sway",
  502                                       "tbu",
  503                                       "bimc",
  504                                       "ahb_aon",
  505                                       "q6ss_slave",
  506                                       "q6ss_master",
  507                                       "q6_axim";
  508 
  509                         resets = <&gcc GCC_CDSP_RESTART>;
  510                         reset-names = "restart";
  511 
  512                         qcom,halt-regs = <&tcsr 0x19004>;
  513 
  514                         memory-region = <&cdsp_fw_mem>;
  515 
  516                         qcom,smem-states = <&cdsp_smp2p_out 0>;
  517                         qcom,smem-state-names = "stop";
  518 
  519                         status = "disabled";
  520 
  521                         glink-edge {
  522                                 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
  523 
  524                                 qcom,remote-pid = <5>;
  525                                 mboxes = <&apcs_glb 12>;
  526 
  527                                 label = "cdsp";
  528                         };
  529                 };
  530 
  531                 usb3: usb@7678800 {
  532                         compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
  533                         reg = <0x07678800 0x400>;
  534                         #address-cells = <1>;
  535                         #size-cells = <1>;
  536                         ranges;
  537                         clocks = <&gcc GCC_USB30_MASTER_CLK>,
  538                                  <&gcc GCC_SYS_NOC_USB3_CLK>,
  539                                  <&gcc GCC_USB30_SLEEP_CLK>,
  540                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>;
  541                         clock-names = "core", "iface", "sleep", "mock_utmi";
  542                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
  543                                           <&gcc GCC_USB30_MASTER_CLK>;
  544                         assigned-clock-rates = <19200000>, <200000000>;
  545                         status = "disabled";
  546 
  547                         usb3_dwc3: usb@7580000 {
  548                                 compatible = "snps,dwc3";
  549                                 reg = <0x07580000 0xcd00>;
  550                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  551                                 phys = <&usb2_phy_prim>, <&usb3_phy>;
  552                                 phy-names = "usb2-phy", "usb3-phy";
  553                                 snps,has-lpm-erratum;
  554                                 snps,hird-threshold = /bits/ 8 <0x10>;
  555                                 snps,usb3_lpm_capable;
  556                                 dr_mode = "otg";
  557                         };
  558                 };
  559 
  560                 usb2: usb@79b8800 {
  561                         compatible = "qcom,qcs404-dwc3", "qcom,dwc3";
  562                         reg = <0x079b8800 0x400>;
  563                         #address-cells = <1>;
  564                         #size-cells = <1>;
  565                         ranges;
  566                         clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
  567                                  <&gcc GCC_PCNOC_USB2_CLK>,
  568                                  <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
  569                                  <&gcc GCC_USB20_MOCK_UTMI_CLK>;
  570                         clock-names = "core", "iface", "sleep", "mock_utmi";
  571                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
  572                                           <&gcc GCC_USB_HS_SYSTEM_CLK>;
  573                         assigned-clock-rates = <19200000>, <133333333>;
  574                         status = "disabled";
  575 
  576                         usb@78c0000 {
  577                                 compatible = "snps,dwc3";
  578                                 reg = <0x078c0000 0xcc00>;
  579                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  580                                 phys = <&usb2_phy_sec>;
  581                                 phy-names = "usb2-phy";
  582                                 snps,has-lpm-erratum;
  583                                 snps,hird-threshold = /bits/ 8 <0x10>;
  584                                 snps,usb3_lpm_capable;
  585                                 dr_mode = "peripheral";
  586                         };
  587                 };
  588 
  589                 tlmm: pinctrl@1000000 {
  590                         compatible = "qcom,qcs404-pinctrl";
  591                         reg = <0x01000000 0x200000>,
  592                               <0x01300000 0x200000>,
  593                               <0x07b00000 0x200000>;
  594                         reg-names = "south", "north", "east";
  595                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
  596                         gpio-ranges = <&tlmm 0 0 120>;
  597                         gpio-controller;
  598                         #gpio-cells = <2>;
  599                         interrupt-controller;
  600                         #interrupt-cells = <2>;
  601 
  602                         blsp1_i2c0_default: blsp1-i2c0-default {
  603                                 pins = "gpio32", "gpio33";
  604                                 function = "blsp_i2c0";
  605                         };
  606 
  607                         blsp1_i2c1_default: blsp1-i2c1-default {
  608                                 pins = "gpio24", "gpio25";
  609                                 function = "blsp_i2c1";
  610                         };
  611 
  612                         blsp1_i2c2_default: blsp1-i2c2-default {
  613                                 sda {
  614                                         pins = "gpio19";
  615                                         function = "blsp_i2c_sda_a2";
  616                                 };
  617 
  618                                 scl {
  619                                         pins = "gpio20";
  620                                         function = "blsp_i2c_scl_a2";
  621                                 };
  622                         };
  623 
  624                         blsp1_i2c3_default: blsp1-i2c3-default {
  625                                 pins = "gpio84", "gpio85";
  626                                 function = "blsp_i2c3";
  627                         };
  628 
  629                         blsp1_i2c4_default: blsp1-i2c4-default {
  630                                 pins = "gpio117", "gpio118";
  631                                 function = "blsp_i2c4";
  632                         };
  633 
  634                         blsp1_uart0_default: blsp1-uart0-default {
  635                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
  636                                 function = "blsp_uart0";
  637                         };
  638 
  639                         blsp1_uart1_default: blsp1-uart1-default {
  640                                 pins = "gpio22", "gpio23";
  641                                 function = "blsp_uart1";
  642                         };
  643 
  644                         blsp1_uart2_default: blsp1-uart2-default {
  645                                 rx {
  646                                         pins = "gpio18";
  647                                         function = "blsp_uart_rx_a2";
  648                                 };
  649 
  650                                 tx {
  651                                         pins = "gpio17";
  652                                         function = "blsp_uart_tx_a2";
  653                                 };
  654                         };
  655 
  656                         blsp1_uart3_default: blsp1-uart3-default {
  657                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
  658                                 function = "blsp_uart3";
  659                         };
  660 
  661                         blsp2_i2c0_default: blsp2-i2c0-default {
  662                                 pins = "gpio28", "gpio29";
  663                                 function = "blsp_i2c5";
  664                         };
  665 
  666                         blsp1_spi0_default: blsp1-spi0-default {
  667                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
  668                                 function = "blsp_spi0";
  669                         };
  670 
  671                         blsp1_spi1_default: blsp1-spi1-default {
  672                                 mosi {
  673                                         pins = "gpio22";
  674                                         function = "blsp_spi_mosi_a1";
  675                                 };
  676 
  677                                 miso {
  678                                         pins = "gpio23";
  679                                         function = "blsp_spi_miso_a1";
  680                                 };
  681 
  682                                 cs_n {
  683                                         pins = "gpio24";
  684                                         function = "blsp_spi_cs_n_a1";
  685                                 };
  686 
  687                                 clk {
  688                                         pins = "gpio25";
  689                                         function = "blsp_spi_clk_a1";
  690                                 };
  691                         };
  692 
  693                         blsp1_spi2_default: blsp1-spi2-default {
  694                                 pins = "gpio17", "gpio18", "gpio19", "gpio20";
  695                                 function = "blsp_spi2";
  696                         };
  697 
  698                         blsp1_spi3_default: blsp1-spi3-default {
  699                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
  700                                 function = "blsp_spi3";
  701                         };
  702 
  703                         blsp1_spi4_default: blsp1-spi4-default {
  704                                 pins = "gpio37", "gpio38", "gpio117", "gpio118";
  705                                 function = "blsp_spi4";
  706                         };
  707 
  708                         blsp2_spi0_default: blsp2-spi0-default {
  709                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
  710                                 function = "blsp_spi5";
  711                         };
  712 
  713                         blsp2_uart0_default: blsp2-uart0-default {
  714                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
  715                                 function = "blsp_uart5";
  716                         };
  717                 };
  718 
  719                 gcc: clock-controller@1800000 {
  720                         compatible = "qcom,gcc-qcs404";
  721                         reg = <0x01800000 0x80000>;
  722                         #clock-cells = <1>;
  723                         #reset-cells = <1>;
  724 
  725                         assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
  726                         assigned-clock-rates = <19200000>;
  727                 };
  728 
  729                 tcsr_mutex_regs: syscon@1905000 {
  730                         compatible = "syscon";
  731                         reg = <0x01905000 0x20000>;
  732                 };
  733 
  734                 tcsr: syscon@1937000 {
  735                         compatible = "syscon";
  736                         reg = <0x01937000 0x25000>;
  737                 };
  738 
  739                 sram@290000 {
  740                         compatible = "qcom,rpm-stats";
  741                         reg = <0x00290000 0x10000>;
  742                 };
  743 
  744                 spmi_bus: spmi@200f000 {
  745                         compatible = "qcom,spmi-pmic-arb";
  746                         reg = <0x0200f000 0x001000>,
  747                               <0x02400000 0x800000>,
  748                               <0x02c00000 0x800000>,
  749                               <0x03800000 0x200000>,
  750                               <0x0200a000 0x002100>;
  751                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
  752                         interrupt-names = "periph_irq";
  753                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
  754                         qcom,ee = <0>;
  755                         qcom,channel = <0>;
  756                         #address-cells = <2>;
  757                         #size-cells = <0>;
  758                         interrupt-controller;
  759                         #interrupt-cells = <4>;
  760                 };
  761 
  762                 remoteproc_wcss: remoteproc@7400000 {
  763                         compatible = "qcom,qcs404-wcss-pas";
  764                         reg = <0x07400000 0x4040>;
  765 
  766                         interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
  767                                               <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  768                                               <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  769                                               <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  770                                               <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  771                         interrupt-names = "wdog", "fatal", "ready",
  772                                           "handover", "stop-ack";
  773 
  774                         clocks = <&xo_board>;
  775                         clock-names = "xo";
  776 
  777                         memory-region = <&wlan_fw_mem>;
  778 
  779                         qcom,smem-states = <&wcss_smp2p_out 0>;
  780                         qcom,smem-state-names = "stop";
  781 
  782                         status = "disabled";
  783 
  784                         glink-edge {
  785                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
  786 
  787                                 qcom,remote-pid = <1>;
  788                                 mboxes = <&apcs_glb 16>;
  789 
  790                                 label = "wcss";
  791                         };
  792                 };
  793 
  794                 pcie_phy: phy@7786000 {
  795                         compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
  796                         reg = <0x07786000 0xb8>;
  797 
  798                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
  799                         resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
  800                                  <&gcc 21>;
  801                         reset-names = "phy", "pipe";
  802 
  803                         clock-output-names = "pcie_0_pipe_clk";
  804                         #phy-cells = <0>;
  805 
  806                         status = "disabled";
  807                 };
  808 
  809                 sdcc1: mmc@7804000 {
  810                         compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
  811                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
  812                         reg-names = "hc", "cqhci";
  813 
  814                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  815                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
  816                         interrupt-names = "hc_irq", "pwr_irq";
  817 
  818                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
  819                                  <&gcc GCC_SDCC1_APPS_CLK>,
  820                                  <&xo_board>;
  821                         clock-names = "iface", "core", "xo";
  822 
  823                         status = "disabled";
  824                 };
  825 
  826                 blsp1_dma: dma-controller@7884000 {
  827                         compatible = "qcom,bam-v1.7.0";
  828                         reg = <0x07884000 0x25000>;
  829                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
  830                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
  831                         clock-names = "bam_clk";
  832                         #dma-cells = <1>;
  833                         qcom,ee = <0>;
  834                         status = "okay";
  835                 };
  836 
  837                 blsp1_uart0: serial@78af000 {
  838                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  839                         reg = <0x078af000 0x200>;
  840                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  841                         clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  842                         clock-names = "core", "iface";
  843                         dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
  844                         dma-names = "tx", "rx";
  845                         pinctrl-names = "default";
  846                         pinctrl-0 = <&blsp1_uart0_default>;
  847                         status = "disabled";
  848                 };
  849 
  850                 blsp1_uart1: serial@78b0000 {
  851                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  852                         reg = <0x078b0000 0x200>;
  853                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  854                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  855                         clock-names = "core", "iface";
  856                         dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
  857                         dma-names = "tx", "rx";
  858                         pinctrl-names = "default";
  859                         pinctrl-0 = <&blsp1_uart1_default>;
  860                         status = "disabled";
  861                 };
  862 
  863                 blsp1_uart2: serial@78b1000 {
  864                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  865                         reg = <0x078b1000 0x200>;
  866                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
  867                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  868                         clock-names = "core", "iface";
  869                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
  870                         dma-names = "tx", "rx";
  871                         pinctrl-names = "default";
  872                         pinctrl-0 = <&blsp1_uart2_default>;
  873                         status = "okay";
  874                 };
  875 
  876                 ethernet: ethernet@7a80000 {
  877                         compatible = "qcom,qcs404-ethqos";
  878                         reg = <0x07a80000 0x10000>,
  879                                 <0x07a96000 0x100>;
  880                         reg-names = "stmmaceth", "rgmii";
  881                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
  882                         clocks = <&gcc GCC_ETH_AXI_CLK>,
  883                                 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
  884                                 <&gcc GCC_ETH_PTP_CLK>,
  885                                 <&gcc GCC_ETH_RGMII_CLK>;
  886                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
  887                                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  888                         interrupt-names = "macirq", "eth_lpi";
  889 
  890                         snps,tso;
  891                         rx-fifo-depth = <4096>;
  892                         tx-fifo-depth = <4096>;
  893 
  894                         status = "disabled";
  895                 };
  896 
  897                 wifi: wifi@a000000 {
  898                         compatible = "qcom,wcn3990-wifi";
  899                         reg = <0xa000000 0x800000>;
  900                         reg-names = "membase";
  901                         memory-region = <&wlan_msa_mem>;
  902                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
  903                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
  904                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
  905                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
  906                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
  907                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
  908                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
  909                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
  910                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
  911                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
  912                                      <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
  913                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
  914                         status = "disabled";
  915                 };
  916 
  917                 blsp1_uart3: serial@78b2000 {
  918                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  919                         reg = <0x078b2000 0x200>;
  920                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  921                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
  922                         clock-names = "core", "iface";
  923                         dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
  924                         dma-names = "tx", "rx";
  925                         pinctrl-names = "default";
  926                         pinctrl-0 = <&blsp1_uart3_default>;
  927                         status = "disabled";
  928                 };
  929 
  930                 blsp1_i2c0: i2c@78b5000 {
  931                         compatible = "qcom,i2c-qup-v2.2.1";
  932                         reg = <0x078b5000 0x600>;
  933                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  934                         clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
  935                                  <&gcc GCC_BLSP1_AHB_CLK>;
  936                         clock-names = "core", "iface";
  937                         pinctrl-names = "default";
  938                         pinctrl-0 = <&blsp1_i2c0_default>;
  939                         #address-cells = <1>;
  940                         #size-cells = <0>;
  941                         status = "disabled";
  942                 };
  943 
  944                 blsp1_spi0: spi@78b5000 {
  945                         compatible = "qcom,spi-qup-v2.2.1";
  946                         reg = <0x078b5000 0x600>;
  947                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  948                         clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
  949                                  <&gcc GCC_BLSP1_AHB_CLK>;
  950                         clock-names = "core", "iface";
  951                         pinctrl-names = "default";
  952                         pinctrl-0 = <&blsp1_spi0_default>;
  953                         #address-cells = <1>;
  954                         #size-cells = <0>;
  955                         status = "disabled";
  956                 };
  957 
  958                 blsp1_i2c1: i2c@78b6000 {
  959                         compatible = "qcom,i2c-qup-v2.2.1";
  960                         reg = <0x078b6000 0x600>;
  961                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  962                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
  963                                  <&gcc GCC_BLSP1_AHB_CLK>;
  964                         clock-names = "core", "iface";
  965                         pinctrl-names = "default";
  966                         pinctrl-0 = <&blsp1_i2c1_default>;
  967                         #address-cells = <1>;
  968                         #size-cells = <0>;
  969                         status = "disabled";
  970                 };
  971 
  972                 blsp1_spi1: spi@78b6000 {
  973                         compatible = "qcom,spi-qup-v2.2.1";
  974                         reg = <0x078b6000 0x600>;
  975                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  976                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
  977                                  <&gcc GCC_BLSP1_AHB_CLK>;
  978                         clock-names = "core", "iface";
  979                         pinctrl-names = "default";
  980                         pinctrl-0 = <&blsp1_spi1_default>;
  981                         #address-cells = <1>;
  982                         #size-cells = <0>;
  983                         status = "disabled";
  984                 };
  985 
  986                 blsp1_i2c2: i2c@78b7000 {
  987                         compatible = "qcom,i2c-qup-v2.2.1";
  988                         reg = <0x078b7000 0x600>;
  989                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  990                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
  991                                  <&gcc GCC_BLSP1_AHB_CLK>;
  992                         clock-names = "core", "iface";
  993                         pinctrl-names = "default";
  994                         pinctrl-0 = <&blsp1_i2c2_default>;
  995                         #address-cells = <1>;
  996                         #size-cells = <0>;
  997                         status = "disabled";
  998                 };
  999 
 1000                 blsp1_spi2: spi@78b7000 {
 1001                         compatible = "qcom,spi-qup-v2.2.1";
 1002                         reg = <0x078b7000 0x600>;
 1003                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 1004                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 1005                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1006                         clock-names = "core", "iface";
 1007                         pinctrl-names = "default";
 1008                         pinctrl-0 = <&blsp1_spi2_default>;
 1009                         #address-cells = <1>;
 1010                         #size-cells = <0>;
 1011                         status = "disabled";
 1012                 };
 1013 
 1014                 blsp1_i2c3: i2c@78b8000 {
 1015                         compatible = "qcom,i2c-qup-v2.2.1";
 1016                         reg = <0x078b8000 0x600>;
 1017                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 1018                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 1019                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1020                         clock-names = "core", "iface";
 1021                         pinctrl-names = "default";
 1022                         pinctrl-0 = <&blsp1_i2c3_default>;
 1023                         #address-cells = <1>;
 1024                         #size-cells = <0>;
 1025                         status = "disabled";
 1026                 };
 1027 
 1028                 blsp1_spi3: spi@78b8000 {
 1029                         compatible = "qcom,spi-qup-v2.2.1";
 1030                         reg = <0x078b8000 0x600>;
 1031                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 1032                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 1033                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1034                         clock-names = "core", "iface";
 1035                         pinctrl-names = "default";
 1036                         pinctrl-0 = <&blsp1_spi3_default>;
 1037                         #address-cells = <1>;
 1038                         #size-cells = <0>;
 1039                         status = "disabled";
 1040                 };
 1041 
 1042                 blsp1_i2c4: i2c@78b9000 {
 1043                         compatible = "qcom,i2c-qup-v2.2.1";
 1044                         reg = <0x078b9000 0x600>;
 1045                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 1046                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 1047                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1048                         clock-names = "core", "iface";
 1049                         pinctrl-names = "default";
 1050                         pinctrl-0 = <&blsp1_i2c4_default>;
 1051                         #address-cells = <1>;
 1052                         #size-cells = <0>;
 1053                         status = "disabled";
 1054                 };
 1055 
 1056                 blsp1_spi4: spi@78b9000 {
 1057                         compatible = "qcom,spi-qup-v2.2.1";
 1058                         reg = <0x078b9000 0x600>;
 1059                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 1060                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 1061                                  <&gcc GCC_BLSP1_AHB_CLK>;
 1062                         clock-names = "core", "iface";
 1063                         pinctrl-names = "default";
 1064                         pinctrl-0 = <&blsp1_spi4_default>;
 1065                         #address-cells = <1>;
 1066                         #size-cells = <0>;
 1067                         status = "disabled";
 1068                 };
 1069 
 1070                 blsp2_dma: dma-controller@7ac4000 {
 1071                         compatible = "qcom,bam-v1.7.0";
 1072                         reg = <0x07ac4000 0x17000>;
 1073                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 1074                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 1075                         clock-names = "bam_clk";
 1076                         #dma-cells = <1>;
 1077                         qcom,ee = <0>;
 1078                         status = "disabled";
 1079                 };
 1080 
 1081                 blsp2_uart0: serial@7aef000 {
 1082                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 1083                         reg = <0x07aef000 0x200>;
 1084                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 1085                         clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 1086                         clock-names = "core", "iface";
 1087                         dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
 1088                         dma-names = "tx", "rx";
 1089                         pinctrl-names = "default";
 1090                         pinctrl-0 = <&blsp2_uart0_default>;
 1091                         status = "disabled";
 1092                 };
 1093 
 1094                 blsp2_i2c0: i2c@7af5000 {
 1095                         compatible = "qcom,i2c-qup-v2.2.1";
 1096                         reg = <0x07af5000 0x600>;
 1097                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 1098                         clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
 1099                                  <&gcc GCC_BLSP2_AHB_CLK>;
 1100                         clock-names = "core", "iface";
 1101                         pinctrl-names = "default";
 1102                         pinctrl-0 = <&blsp2_i2c0_default>;
 1103                         #address-cells = <1>;
 1104                         #size-cells = <0>;
 1105                         status = "disabled";
 1106                 };
 1107 
 1108                 blsp2_spi0: spi@7af5000 {
 1109                         compatible = "qcom,spi-qup-v2.2.1";
 1110                         reg = <0x07af5000 0x600>;
 1111                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 1112                         clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
 1113                                  <&gcc GCC_BLSP2_AHB_CLK>;
 1114                         clock-names = "core", "iface";
 1115                         pinctrl-names = "default";
 1116                         pinctrl-0 = <&blsp2_spi0_default>;
 1117                         #address-cells = <1>;
 1118                         #size-cells = <0>;
 1119                         status = "disabled";
 1120                 };
 1121 
 1122                 sram@8600000 {
 1123                         compatible = "qcom,qcs404-imem", "syscon", "simple-mfd";
 1124                         reg = <0x08600000 0x1000>;
 1125 
 1126                         #address-cells = <1>;
 1127                         #size-cells = <1>;
 1128 
 1129                         ranges = <0 0x08600000 0x1000>;
 1130 
 1131                         pil-reloc@94c {
 1132                                 compatible = "qcom,pil-reloc-info";
 1133                                 reg = <0x94c 0xc8>;
 1134                         };
 1135                 };
 1136 
 1137                 intc: interrupt-controller@b000000 {
 1138                         compatible = "qcom,msm-qgic2";
 1139                         interrupt-controller;
 1140                         #interrupt-cells = <3>;
 1141                         reg = <0x0b000000 0x1000>,
 1142                               <0x0b002000 0x1000>;
 1143                 };
 1144 
 1145                 apcs_glb: mailbox@b011000 {
 1146                         compatible = "qcom,qcs404-apcs-apps-global", "syscon";
 1147                         reg = <0x0b011000 0x1000>;
 1148                         #mbox-cells = <1>;
 1149                         clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
 1150                         clock-names = "pll", "aux";
 1151                         #clock-cells = <0>;
 1152                 };
 1153 
 1154                 apcs_hfpll: clock-controller@b016000 {
 1155                         compatible = "qcom,hfpll";
 1156                         reg = <0x0b016000 0x30>;
 1157                         #clock-cells = <0>;
 1158                         clock-output-names = "apcs_hfpll";
 1159                         clocks = <&xo_board>;
 1160                         clock-names = "xo";
 1161                 };
 1162 
 1163                 watchdog@b017000 {
 1164                         compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
 1165                         reg = <0x0b017000 0x1000>;
 1166                         clocks = <&sleep_clk>;
 1167                 };
 1168 
 1169                 cpr: power-controller@b018000 {
 1170                         compatible = "qcom,qcs404-cpr", "qcom,cpr";
 1171                         reg = <0x0b018000 0x1000>;
 1172                         interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
 1173                         clocks = <&xo_board>;
 1174                         clock-names = "ref";
 1175                         vdd-apc-supply = <&pms405_s3>;
 1176                         #power-domain-cells = <0>;
 1177                         operating-points-v2 = <&cpr_opp_table>;
 1178                         acc-syscon = <&tcsr>;
 1179 
 1180                         nvmem-cells = <&cpr_efuse_quot_offset1>,
 1181                                 <&cpr_efuse_quot_offset2>,
 1182                                 <&cpr_efuse_quot_offset3>,
 1183                                 <&cpr_efuse_init_voltage1>,
 1184                                 <&cpr_efuse_init_voltage2>,
 1185                                 <&cpr_efuse_init_voltage3>,
 1186                                 <&cpr_efuse_quot1>,
 1187                                 <&cpr_efuse_quot2>,
 1188                                 <&cpr_efuse_quot3>,
 1189                                 <&cpr_efuse_ring1>,
 1190                                 <&cpr_efuse_ring2>,
 1191                                 <&cpr_efuse_ring3>,
 1192                                 <&cpr_efuse_revision>;
 1193                         nvmem-cell-names = "cpr_quotient_offset1",
 1194                                 "cpr_quotient_offset2",
 1195                                 "cpr_quotient_offset3",
 1196                                 "cpr_init_voltage1",
 1197                                 "cpr_init_voltage2",
 1198                                 "cpr_init_voltage3",
 1199                                 "cpr_quotient1",
 1200                                 "cpr_quotient2",
 1201                                 "cpr_quotient3",
 1202                                 "cpr_ring_osc1",
 1203                                 "cpr_ring_osc2",
 1204                                 "cpr_ring_osc3",
 1205                                 "cpr_fuse_revision";
 1206                 };
 1207 
 1208                 timer@b120000 {
 1209                         #address-cells = <1>;
 1210                         #size-cells = <1>;
 1211                         ranges;
 1212                         compatible = "arm,armv7-timer-mem";
 1213                         reg = <0x0b120000 0x1000>;
 1214                         clock-frequency = <19200000>;
 1215 
 1216                         frame@b121000 {
 1217                                 frame-number = <0>;
 1218                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 1219                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 1220                                 reg = <0x0b121000 0x1000>,
 1221                                       <0x0b122000 0x1000>;
 1222                         };
 1223 
 1224                         frame@b123000 {
 1225                                 frame-number = <1>;
 1226                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 1227                                 reg = <0x0b123000 0x1000>;
 1228                                 status = "disabled";
 1229                         };
 1230 
 1231                         frame@b124000 {
 1232                                 frame-number = <2>;
 1233                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 1234                                 reg = <0x0b124000 0x1000>;
 1235                                 status = "disabled";
 1236                         };
 1237 
 1238                         frame@b125000 {
 1239                                 frame-number = <3>;
 1240                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 1241                                 reg = <0x0b125000 0x1000>;
 1242                                 status = "disabled";
 1243                         };
 1244 
 1245                         frame@b126000 {
 1246                                 frame-number = <4>;
 1247                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 1248                                 reg = <0x0b126000 0x1000>;
 1249                                 status = "disabled";
 1250                         };
 1251 
 1252                         frame@b127000 {
 1253                                 frame-number = <5>;
 1254                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 1255                                 reg = <0xb127000 0x1000>;
 1256                                 status = "disabled";
 1257                         };
 1258 
 1259                         frame@b128000 {
 1260                                 frame-number = <6>;
 1261                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 1262                                 reg = <0x0b128000 0x1000>;
 1263                                 status = "disabled";
 1264                         };
 1265                 };
 1266 
 1267                 remoteproc_adsp: remoteproc@c700000 {
 1268                         compatible = "qcom,qcs404-adsp-pas";
 1269                         reg = <0x0c700000 0x4040>;
 1270 
 1271                         interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
 1272                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 1273                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 1274                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 1275                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 1276                         interrupt-names = "wdog", "fatal", "ready",
 1277                                           "handover", "stop-ack";
 1278 
 1279                         clocks = <&xo_board>;
 1280                         clock-names = "xo";
 1281 
 1282                         memory-region = <&adsp_fw_mem>;
 1283 
 1284                         qcom,smem-states = <&adsp_smp2p_out 0>;
 1285                         qcom,smem-state-names = "stop";
 1286 
 1287                         status = "disabled";
 1288 
 1289                         glink-edge {
 1290                                 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
 1291 
 1292                                 qcom,remote-pid = <2>;
 1293                                 mboxes = <&apcs_glb 8>;
 1294 
 1295                                 label = "adsp";
 1296                         };
 1297                 };
 1298 
 1299                 pcie: pci@10000000 {
 1300                         compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
 1301                         reg =  <0x10000000 0xf1d>,
 1302                                <0x10000f20 0xa8>,
 1303                                <0x07780000 0x2000>,
 1304                                <0x10001000 0x2000>;
 1305                         reg-names = "dbi", "elbi", "parf", "config";
 1306                         device_type = "pci";
 1307                         linux,pci-domain = <0>;
 1308                         bus-range = <0x00 0xff>;
 1309                         num-lanes = <1>;
 1310                         #address-cells = <3>;
 1311                         #size-cells = <2>;
 1312 
 1313                         ranges = <0x81000000 0 0          0x10003000 0 0x00010000>, /* I/O */
 1314                                  <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
 1315 
 1316                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 1317                         interrupt-names = "msi";
 1318                         #interrupt-cells = <1>;
 1319                         interrupt-map-mask = <0 0 0 0x7>;
 1320                         interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 1321                                         <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 1322                                         <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 1323                                         <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 1324                         clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 1325                                  <&gcc GCC_PCIE_0_AUX_CLK>,
 1326                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 1327                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 1328                         clock-names = "iface", "aux", "master_bus", "slave_bus";
 1329 
 1330                         resets = <&gcc 18>,
 1331                                  <&gcc 17>,
 1332                                  <&gcc 15>,
 1333                                  <&gcc 19>,
 1334                                  <&gcc GCC_PCIE_0_BCR>,
 1335                                  <&gcc 16>;
 1336                         reset-names = "axi_m",
 1337                                       "axi_s",
 1338                                       "axi_m_sticky",
 1339                                       "pipe_sticky",
 1340                                       "pwr",
 1341                                       "ahb";
 1342 
 1343                         phys = <&pcie_phy>;
 1344                         phy-names = "pciephy";
 1345 
 1346                         status = "disabled";
 1347                 };
 1348         };
 1349 
 1350         timer {
 1351                 compatible = "arm,armv8-timer";
 1352                 interrupts = <GIC_PPI 2 0xff08>,
 1353                              <GIC_PPI 3 0xff08>,
 1354                              <GIC_PPI 4 0xff08>,
 1355                              <GIC_PPI 1 0xff08>;
 1356         };
 1357 
 1358         smp2p-adsp {
 1359                 compatible = "qcom,smp2p";
 1360                 qcom,smem = <443>, <429>;
 1361                 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
 1362                 mboxes = <&apcs_glb 10>;
 1363                 qcom,local-pid = <0>;
 1364                 qcom,remote-pid = <2>;
 1365 
 1366                 adsp_smp2p_out: master-kernel {
 1367                         qcom,entry-name = "master-kernel";
 1368                         #qcom,smem-state-cells = <1>;
 1369                 };
 1370 
 1371                 adsp_smp2p_in: slave-kernel {
 1372                         qcom,entry-name = "slave-kernel";
 1373                         interrupt-controller;
 1374                         #interrupt-cells = <2>;
 1375                 };
 1376         };
 1377 
 1378         smp2p-cdsp {
 1379                 compatible = "qcom,smp2p";
 1380                 qcom,smem = <94>, <432>;
 1381                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
 1382                 mboxes = <&apcs_glb 14>;
 1383                 qcom,local-pid = <0>;
 1384                 qcom,remote-pid = <5>;
 1385 
 1386                 cdsp_smp2p_out: master-kernel {
 1387                         qcom,entry-name = "master-kernel";
 1388                         #qcom,smem-state-cells = <1>;
 1389                 };
 1390 
 1391                 cdsp_smp2p_in: slave-kernel {
 1392                         qcom,entry-name = "slave-kernel";
 1393                         interrupt-controller;
 1394                         #interrupt-cells = <2>;
 1395                 };
 1396         };
 1397 
 1398         smp2p-wcss {
 1399                 compatible = "qcom,smp2p";
 1400                 qcom,smem = <435>, <428>;
 1401                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 1402                 mboxes = <&apcs_glb 18>;
 1403                 qcom,local-pid = <0>;
 1404                 qcom,remote-pid = <1>;
 1405 
 1406                 wcss_smp2p_out: master-kernel {
 1407                         qcom,entry-name = "master-kernel";
 1408                         #qcom,smem-state-cells = <1>;
 1409                 };
 1410 
 1411                 wcss_smp2p_in: slave-kernel {
 1412                         qcom,entry-name = "slave-kernel";
 1413                         interrupt-controller;
 1414                         #interrupt-cells = <2>;
 1415                 };
 1416         };
 1417 
 1418         thermal-zones {
 1419                 aoss-thermal {
 1420                         polling-delay-passive = <250>;
 1421                         polling-delay = <1000>;
 1422 
 1423                         thermal-sensors = <&tsens 0>;
 1424 
 1425                         trips {
 1426                                 aoss_alert0: trip-point0 {
 1427                                         temperature = <105000>;
 1428                                         hysteresis = <2000>;
 1429                                         type = "hot";
 1430                                 };
 1431                         };
 1432                 };
 1433 
 1434                 q6-hvx-thermal {
 1435                         polling-delay-passive = <250>;
 1436                         polling-delay = <1000>;
 1437 
 1438                         thermal-sensors = <&tsens 1>;
 1439 
 1440                         trips {
 1441                                 q6_hvx_alert0: trip-point0 {
 1442                                         temperature = <105000>;
 1443                                         hysteresis = <2000>;
 1444                                         type = "hot";
 1445                                 };
 1446                         };
 1447                 };
 1448 
 1449                 lpass-thermal {
 1450                         polling-delay-passive = <250>;
 1451                         polling-delay = <1000>;
 1452 
 1453                         thermal-sensors = <&tsens 2>;
 1454 
 1455                         trips {
 1456                                 lpass_alert0: trip-point0 {
 1457                                         temperature = <105000>;
 1458                                         hysteresis = <2000>;
 1459                                         type = "hot";
 1460                                 };
 1461                         };
 1462                 };
 1463 
 1464                 wlan-thermal {
 1465                         polling-delay-passive = <250>;
 1466                         polling-delay = <1000>;
 1467 
 1468                         thermal-sensors = <&tsens 3>;
 1469 
 1470                         trips {
 1471                                 wlan_alert0: trip-point0 {
 1472                                         temperature = <105000>;
 1473                                         hysteresis = <2000>;
 1474                                         type = "hot";
 1475                                 };
 1476                         };
 1477                 };
 1478 
 1479                 cluster-thermal {
 1480                         polling-delay-passive = <250>;
 1481                         polling-delay = <1000>;
 1482 
 1483                         thermal-sensors = <&tsens 4>;
 1484 
 1485                         trips {
 1486                                 cluster_alert0: trip-point0 {
 1487                                         temperature = <95000>;
 1488                                         hysteresis = <2000>;
 1489                                         type = "hot";
 1490                                 };
 1491                                 cluster_alert1: trip-point1 {
 1492                                         temperature = <105000>;
 1493                                         hysteresis = <2000>;
 1494                                         type = "passive";
 1495                                 };
 1496                                 cluster_crit: cluster_crit {
 1497                                         temperature = <120000>;
 1498                                         hysteresis = <2000>;
 1499                                         type = "critical";
 1500                                 };
 1501                         };
 1502                         cooling-maps {
 1503                                 map0 {
 1504                                         trip = <&cluster_alert1>;
 1505                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1506                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1507                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1508                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1509                                 };
 1510                         };
 1511                 };
 1512 
 1513                 cpu0-thermal {
 1514                         polling-delay-passive = <250>;
 1515                         polling-delay = <1000>;
 1516 
 1517                         thermal-sensors = <&tsens 5>;
 1518 
 1519                         trips {
 1520                                 cpu0_alert0: trip-point0 {
 1521                                         temperature = <95000>;
 1522                                         hysteresis = <2000>;
 1523                                         type = "hot";
 1524                                 };
 1525                                 cpu0_alert1: trip-point1 {
 1526                                         temperature = <105000>;
 1527                                         hysteresis = <2000>;
 1528                                         type = "passive";
 1529                                 };
 1530                                 cpu0_crit: cpu_crit {
 1531                                         temperature = <120000>;
 1532                                         hysteresis = <2000>;
 1533                                         type = "critical";
 1534                                 };
 1535                         };
 1536                         cooling-maps {
 1537                                 map0 {
 1538                                         trip = <&cpu0_alert1>;
 1539                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1540                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1541                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1542                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1543                                 };
 1544                         };
 1545                 };
 1546 
 1547                 cpu1-thermal {
 1548                         polling-delay-passive = <250>;
 1549                         polling-delay = <1000>;
 1550 
 1551                         thermal-sensors = <&tsens 6>;
 1552 
 1553                         trips {
 1554                                 cpu1_alert0: trip-point0 {
 1555                                         temperature = <95000>;
 1556                                         hysteresis = <2000>;
 1557                                         type = "hot";
 1558                                 };
 1559                                 cpu1_alert1: trip-point1 {
 1560                                         temperature = <105000>;
 1561                                         hysteresis = <2000>;
 1562                                         type = "passive";
 1563                                 };
 1564                                 cpu1_crit: cpu_crit {
 1565                                         temperature = <120000>;
 1566                                         hysteresis = <2000>;
 1567                                         type = "critical";
 1568                                 };
 1569                         };
 1570                         cooling-maps {
 1571                                 map0 {
 1572                                         trip = <&cpu1_alert1>;
 1573                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1574                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1575                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1576                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1577                                 };
 1578                         };
 1579                 };
 1580 
 1581                 cpu2-thermal {
 1582                         polling-delay-passive = <250>;
 1583                         polling-delay = <1000>;
 1584 
 1585                         thermal-sensors = <&tsens 7>;
 1586 
 1587                         trips {
 1588                                 cpu2_alert0: trip-point0 {
 1589                                         temperature = <95000>;
 1590                                         hysteresis = <2000>;
 1591                                         type = "hot";
 1592                                 };
 1593                                 cpu2_alert1: trip-point1 {
 1594                                         temperature = <105000>;
 1595                                         hysteresis = <2000>;
 1596                                         type = "passive";
 1597                                 };
 1598                                 cpu2_crit: cpu_crit {
 1599                                         temperature = <120000>;
 1600                                         hysteresis = <2000>;
 1601                                         type = "critical";
 1602                                 };
 1603                         };
 1604                         cooling-maps {
 1605                                 map0 {
 1606                                         trip = <&cpu2_alert1>;
 1607                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1608                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1609                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1610                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1611                                 };
 1612                         };
 1613                 };
 1614 
 1615                 cpu3-thermal {
 1616                         polling-delay-passive = <250>;
 1617                         polling-delay = <1000>;
 1618 
 1619                         thermal-sensors = <&tsens 8>;
 1620 
 1621                         trips {
 1622                                 cpu3_alert0: trip-point0 {
 1623                                         temperature = <95000>;
 1624                                         hysteresis = <2000>;
 1625                                         type = "hot";
 1626                                 };
 1627                                 cpu3_alert1: trip-point1 {
 1628                                         temperature = <105000>;
 1629                                         hysteresis = <2000>;
 1630                                         type = "passive";
 1631                                 };
 1632                                 cpu3_crit: cpu_crit {
 1633                                         temperature = <120000>;
 1634                                         hysteresis = <2000>;
 1635                                         type = "critical";
 1636                                 };
 1637                         };
 1638                         cooling-maps {
 1639                                 map0 {
 1640                                         trip = <&cpu3_alert1>;
 1641                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1642                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1643                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1644                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1645                                 };
 1646                         };
 1647                 };
 1648 
 1649                 gpu-thermal {
 1650                         polling-delay-passive = <250>;
 1651                         polling-delay = <1000>;
 1652 
 1653                         thermal-sensors = <&tsens 9>;
 1654 
 1655                         trips {
 1656                                 gpu_alert0: trip-point0 {
 1657                                         temperature = <95000>;
 1658                                         hysteresis = <2000>;
 1659                                         type = "hot";
 1660                                 };
 1661                         };
 1662                 };
 1663         };
 1664 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/qcs404.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/qcs404.dtsi
