sc7280.dtsi

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    1 // SPDX-License-Identifier: BSD-3-Clause
    2 /*
    3  * sc7280 SoC device tree source
    4  *
    5  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
    6  */
    7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
    8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
    9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
   10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
   11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
   12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
   13 #include <dt-bindings/clock/qcom,rpmh.h>
   14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
   15 #include <dt-bindings/dma/qcom-gpi.h>
   16 #include <dt-bindings/gpio/gpio.h>
   17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
   18 #include <dt-bindings/interconnect/qcom,sc7280.h>
   19 #include <dt-bindings/interrupt-controller/arm-gic.h>
   20 #include <dt-bindings/mailbox/qcom-ipcc.h>
   21 #include <dt-bindings/power/qcom-rpmpd.h>
   22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
   23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
   24 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
   25 #include <dt-bindings/thermal/thermal.h>
   26 
   27 / {
   28         interrupt-parent = <&intc>;
   29 
   30         #address-cells = <2>;
   31         #size-cells = <2>;
   32 
   33         chosen { };
   34 
   35         aliases {
   36                 i2c0 = &i2c0;
   37                 i2c1 = &i2c1;
   38                 i2c2 = &i2c2;
   39                 i2c3 = &i2c3;
   40                 i2c4 = &i2c4;
   41                 i2c5 = &i2c5;
   42                 i2c6 = &i2c6;
   43                 i2c7 = &i2c7;
   44                 i2c8 = &i2c8;
   45                 i2c9 = &i2c9;
   46                 i2c10 = &i2c10;
   47                 i2c11 = &i2c11;
   48                 i2c12 = &i2c12;
   49                 i2c13 = &i2c13;
   50                 i2c14 = &i2c14;
   51                 i2c15 = &i2c15;
   52                 mmc1 = &sdhc_1;
   53                 mmc2 = &sdhc_2;
   54                 spi0 = &spi0;
   55                 spi1 = &spi1;
   56                 spi2 = &spi2;
   57                 spi3 = &spi3;
   58                 spi4 = &spi4;
   59                 spi5 = &spi5;
   60                 spi6 = &spi6;
   61                 spi7 = &spi7;
   62                 spi8 = &spi8;
   63                 spi9 = &spi9;
   64                 spi10 = &spi10;
   65                 spi11 = &spi11;
   66                 spi12 = &spi12;
   67                 spi13 = &spi13;
   68                 spi14 = &spi14;
   69                 spi15 = &spi15;
   70         };
   71 
   72         clocks {
   73                 xo_board: xo-board {
   74                         compatible = "fixed-clock";
   75                         clock-frequency = <76800000>;
   76                         #clock-cells = <0>;
   77                 };
   78 
   79                 sleep_clk: sleep-clk {
   80                         compatible = "fixed-clock";
   81                         clock-frequency = <32000>;
   82                         #clock-cells = <0>;
   83                 };
   84         };
   85 
   86         reserved-memory {
   87                 #address-cells = <2>;
   88                 #size-cells = <2>;
   89                 ranges;
   90 
   91                 wlan_ce_mem: memory@4cd000 {
   92                         no-map;
   93                         reg = <0x0 0x004cd000 0x0 0x1000>;
   94                 };
   95 
   96                 hyp_mem: memory@80000000 {
   97                         reg = <0x0 0x80000000 0x0 0x600000>;
   98                         no-map;
   99                 };
  100 
  101                 xbl_mem: memory@80600000 {
  102                         reg = <0x0 0x80600000 0x0 0x200000>;
  103                         no-map;
  104                 };
  105 
  106                 aop_mem: memory@80800000 {
  107                         reg = <0x0 0x80800000 0x0 0x60000>;
  108                         no-map;
  109                 };
  110 
  111                 aop_cmd_db_mem: memory@80860000 {
  112                         reg = <0x0 0x80860000 0x0 0x20000>;
  113                         compatible = "qcom,cmd-db";
  114                         no-map;
  115                 };
  116 
  117                 reserved_xbl_uefi_log: memory@80880000 {
  118                         reg = <0x0 0x80884000 0x0 0x10000>;
  119                         no-map;
  120                 };
  121 
  122                 sec_apps_mem: memory@808ff000 {
  123                         reg = <0x0 0x808ff000 0x0 0x1000>;
  124                         no-map;
  125                 };
  126 
  127                 smem_mem: memory@80900000 {
  128                         reg = <0x0 0x80900000 0x0 0x200000>;
  129                         no-map;
  130                 };
  131 
  132                 cpucp_mem: memory@80b00000 {
  133                         no-map;
  134                         reg = <0x0 0x80b00000 0x0 0x100000>;
  135                 };
  136 
  137                 wlan_fw_mem: memory@80c00000 {
  138                         reg = <0x0 0x80c00000 0x0 0xc00000>;
  139                         no-map;
  140                 };
  141 
  142                 video_mem: memory@8b200000 {
  143                         reg = <0x0 0x8b200000 0x0 0x500000>;
  144                         no-map;
  145                 };
  146 
  147                 ipa_fw_mem: memory@8b700000 {
  148                         reg = <0 0x8b700000 0 0x10000>;
  149                         no-map;
  150                 };
  151 
  152                 rmtfs_mem: memory@9c900000 {
  153                         compatible = "qcom,rmtfs-mem";
  154                         reg = <0x0 0x9c900000 0x0 0x280000>;
  155                         no-map;
  156 
  157                         qcom,client-id = <1>;
  158                         qcom,vmid = <15>;
  159                 };
  160         };
  161 
  162         cpus {
  163                 #address-cells = <2>;
  164                 #size-cells = <0>;
  165 
  166                 CPU0: cpu@0 {
  167                         device_type = "cpu";
  168                         compatible = "arm,kryo";
  169                         reg = <0x0 0x0>;
  170                         enable-method = "psci";
  171                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  172                                            &LITTLE_CPU_SLEEP_1
  173                                            &CLUSTER_SLEEP_0>;
  174                         next-level-cache = <&L2_0>;
  175                         operating-points-v2 = <&cpu0_opp_table>;
  176                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  177                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  178                         qcom,freq-domain = <&cpufreq_hw 0>;
  179                         #cooling-cells = <2>;
  180                         L2_0: l2-cache {
  181                                 compatible = "cache";
  182                                 next-level-cache = <&L3_0>;
  183                                 L3_0: l3-cache {
  184                                         compatible = "cache";
  185                                 };
  186                         };
  187                 };
  188 
  189                 CPU1: cpu@100 {
  190                         device_type = "cpu";
  191                         compatible = "arm,kryo";
  192                         reg = <0x0 0x100>;
  193                         enable-method = "psci";
  194                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  195                                            &LITTLE_CPU_SLEEP_1
  196                                            &CLUSTER_SLEEP_0>;
  197                         next-level-cache = <&L2_100>;
  198                         operating-points-v2 = <&cpu0_opp_table>;
  199                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  200                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  201                         qcom,freq-domain = <&cpufreq_hw 0>;
  202                         #cooling-cells = <2>;
  203                         L2_100: l2-cache {
  204                                 compatible = "cache";
  205                                 next-level-cache = <&L3_0>;
  206                         };
  207                 };
  208 
  209                 CPU2: cpu@200 {
  210                         device_type = "cpu";
  211                         compatible = "arm,kryo";
  212                         reg = <0x0 0x200>;
  213                         enable-method = "psci";
  214                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  215                                            &LITTLE_CPU_SLEEP_1
  216                                            &CLUSTER_SLEEP_0>;
  217                         next-level-cache = <&L2_200>;
  218                         operating-points-v2 = <&cpu0_opp_table>;
  219                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  220                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  221                         qcom,freq-domain = <&cpufreq_hw 0>;
  222                         #cooling-cells = <2>;
  223                         L2_200: l2-cache {
  224                                 compatible = "cache";
  225                                 next-level-cache = <&L3_0>;
  226                         };
  227                 };
  228 
  229                 CPU3: cpu@300 {
  230                         device_type = "cpu";
  231                         compatible = "arm,kryo";
  232                         reg = <0x0 0x300>;
  233                         enable-method = "psci";
  234                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
  235                                            &LITTLE_CPU_SLEEP_1
  236                                            &CLUSTER_SLEEP_0>;
  237                         next-level-cache = <&L2_300>;
  238                         operating-points-v2 = <&cpu0_opp_table>;
  239                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  240                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  241                         qcom,freq-domain = <&cpufreq_hw 0>;
  242                         #cooling-cells = <2>;
  243                         L2_300: l2-cache {
  244                                 compatible = "cache";
  245                                 next-level-cache = <&L3_0>;
  246                         };
  247                 };
  248 
  249                 CPU4: cpu@400 {
  250                         device_type = "cpu";
  251                         compatible = "arm,kryo";
  252                         reg = <0x0 0x400>;
  253                         enable-method = "psci";
  254                         cpu-idle-states = <&BIG_CPU_SLEEP_0
  255                                            &BIG_CPU_SLEEP_1
  256                                            &CLUSTER_SLEEP_0>;
  257                         next-level-cache = <&L2_400>;
  258                         operating-points-v2 = <&cpu4_opp_table>;
  259                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  260                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  261                         qcom,freq-domain = <&cpufreq_hw 1>;
  262                         #cooling-cells = <2>;
  263                         L2_400: l2-cache {
  264                                 compatible = "cache";
  265                                 next-level-cache = <&L3_0>;
  266                         };
  267                 };
  268 
  269                 CPU5: cpu@500 {
  270                         device_type = "cpu";
  271                         compatible = "arm,kryo";
  272                         reg = <0x0 0x500>;
  273                         enable-method = "psci";
  274                         cpu-idle-states = <&BIG_CPU_SLEEP_0
  275                                            &BIG_CPU_SLEEP_1
  276                                            &CLUSTER_SLEEP_0>;
  277                         next-level-cache = <&L2_500>;
  278                         operating-points-v2 = <&cpu4_opp_table>;
  279                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  280                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  281                         qcom,freq-domain = <&cpufreq_hw 1>;
  282                         #cooling-cells = <2>;
  283                         L2_500: l2-cache {
  284                                 compatible = "cache";
  285                                 next-level-cache = <&L3_0>;
  286                         };
  287                 };
  288 
  289                 CPU6: cpu@600 {
  290                         device_type = "cpu";
  291                         compatible = "arm,kryo";
  292                         reg = <0x0 0x600>;
  293                         enable-method = "psci";
  294                         cpu-idle-states = <&BIG_CPU_SLEEP_0
  295                                            &BIG_CPU_SLEEP_1
  296                                            &CLUSTER_SLEEP_0>;
  297                         next-level-cache = <&L2_600>;
  298                         operating-points-v2 = <&cpu4_opp_table>;
  299                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  300                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  301                         qcom,freq-domain = <&cpufreq_hw 1>;
  302                         #cooling-cells = <2>;
  303                         L2_600: l2-cache {
  304                                 compatible = "cache";
  305                                 next-level-cache = <&L3_0>;
  306                         };
  307                 };
  308 
  309                 CPU7: cpu@700 {
  310                         device_type = "cpu";
  311                         compatible = "arm,kryo";
  312                         reg = <0x0 0x700>;
  313                         enable-method = "psci";
  314                         cpu-idle-states = <&BIG_CPU_SLEEP_0
  315                                            &BIG_CPU_SLEEP_1
  316                                            &CLUSTER_SLEEP_0>;
  317                         next-level-cache = <&L2_700>;
  318                         operating-points-v2 = <&cpu7_opp_table>;
  319                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
  320                                         <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  321                         qcom,freq-domain = <&cpufreq_hw 2>;
  322                         #cooling-cells = <2>;
  323                         L2_700: l2-cache {
  324                                 compatible = "cache";
  325                                 next-level-cache = <&L3_0>;
  326                         };
  327                 };
  328 
  329                 cpu-map {
  330                         cluster0 {
  331                                 core0 {
  332                                         cpu = <&CPU0>;
  333                                 };
  334 
  335                                 core1 {
  336                                         cpu = <&CPU1>;
  337                                 };
  338 
  339                                 core2 {
  340                                         cpu = <&CPU2>;
  341                                 };
  342 
  343                                 core3 {
  344                                         cpu = <&CPU3>;
  345                                 };
  346 
  347                                 core4 {
  348                                         cpu = <&CPU4>;
  349                                 };
  350 
  351                                 core5 {
  352                                         cpu = <&CPU5>;
  353                                 };
  354 
  355                                 core6 {
  356                                         cpu = <&CPU6>;
  357                                 };
  358 
  359                                 core7 {
  360                                         cpu = <&CPU7>;
  361                                 };
  362                         };
  363                 };
  364 
  365                 idle-states {
  366                         entry-method = "psci";
  367 
  368                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
  369                                 compatible = "arm,idle-state";
  370                                 idle-state-name = "little-power-down";
  371                                 arm,psci-suspend-param = <0x40000003>;
  372                                 entry-latency-us = <549>;
  373                                 exit-latency-us = <901>;
  374                                 min-residency-us = <1774>;
  375                                 local-timer-stop;
  376                         };
  377 
  378                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
  379                                 compatible = "arm,idle-state";
  380                                 idle-state-name = "little-rail-power-down";
  381                                 arm,psci-suspend-param = <0x40000004>;
  382                                 entry-latency-us = <702>;
  383                                 exit-latency-us = <915>;
  384                                 min-residency-us = <4001>;
  385                                 local-timer-stop;
  386                         };
  387 
  388                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
  389                                 compatible = "arm,idle-state";
  390                                 idle-state-name = "big-power-down";
  391                                 arm,psci-suspend-param = <0x40000003>;
  392                                 entry-latency-us = <523>;
  393                                 exit-latency-us = <1244>;
  394                                 min-residency-us = <2207>;
  395                                 local-timer-stop;
  396                         };
  397 
  398                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
  399                                 compatible = "arm,idle-state";
  400                                 idle-state-name = "big-rail-power-down";
  401                                 arm,psci-suspend-param = <0x40000004>;
  402                                 entry-latency-us = <526>;
  403                                 exit-latency-us = <1854>;
  404                                 min-residency-us = <5555>;
  405                                 local-timer-stop;
  406                         };
  407 
  408                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  409                                 compatible = "arm,idle-state";
  410                                 idle-state-name = "cluster-power-down";
  411                                 arm,psci-suspend-param = <0x40003444>;
  412                                 entry-latency-us = <3263>;
  413                                 exit-latency-us = <6562>;
  414                                 min-residency-us = <9926>;
  415                                 local-timer-stop;
  416                         };
  417                 };
  418         };
  419 
  420         cpu0_opp_table: opp-table-cpu0 {
  421                 compatible = "operating-points-v2";
  422                 opp-shared;
  423 
  424                 cpu0_opp_300mhz: opp-300000000 {
  425                         opp-hz = /bits/ 64 <300000000>;
  426                         opp-peak-kBps = <800000 9600000>;
  427                 };
  428 
  429                 cpu0_opp_691mhz: opp-691200000 {
  430                         opp-hz = /bits/ 64 <691200000>;
  431                         opp-peak-kBps = <800000 17817600>;
  432                 };
  433 
  434                 cpu0_opp_806mhz: opp-806400000 {
  435                         opp-hz = /bits/ 64 <806400000>;
  436                         opp-peak-kBps = <800000 20889600>;
  437                 };
  438 
  439                 cpu0_opp_941mhz: opp-940800000 {
  440                         opp-hz = /bits/ 64 <940800000>;
  441                         opp-peak-kBps = <1804000 24576000>;
  442                 };
  443 
  444                 cpu0_opp_1152mhz: opp-1152000000 {
  445                         opp-hz = /bits/ 64 <1152000000>;
  446                         opp-peak-kBps = <2188000 27033600>;
  447                 };
  448 
  449                 cpu0_opp_1325mhz: opp-1324800000 {
  450                         opp-hz = /bits/ 64 <1324800000>;
  451                         opp-peak-kBps = <2188000 33792000>;
  452                 };
  453 
  454                 cpu0_opp_1517mhz: opp-1516800000 {
  455                         opp-hz = /bits/ 64 <1516800000>;
  456                         opp-peak-kBps = <3072000 38092800>;
  457                 };
  458 
  459                 cpu0_opp_1651mhz: opp-1651200000 {
  460                         opp-hz = /bits/ 64 <1651200000>;
  461                         opp-peak-kBps = <3072000 41779200>;
  462                 };
  463 
  464                 cpu0_opp_1805mhz: opp-1804800000 {
  465                         opp-hz = /bits/ 64 <1804800000>;
  466                         opp-peak-kBps = <4068000 48537600>;
  467                 };
  468 
  469                 cpu0_opp_1958mhz: opp-1958400000 {
  470                         opp-hz = /bits/ 64 <1958400000>;
  471                         opp-peak-kBps = <4068000 48537600>;
  472                 };
  473 
  474                 cpu0_opp_2016mhz: opp-2016000000 {
  475                         opp-hz = /bits/ 64 <2016000000>;
  476                         opp-peak-kBps = <6220000 48537600>;
  477                 };
  478         };
  479 
  480         cpu4_opp_table: opp-table-cpu4 {
  481                 compatible = "operating-points-v2";
  482                 opp-shared;
  483 
  484                 cpu4_opp_691mhz: opp-691200000 {
  485                         opp-hz = /bits/ 64 <691200000>;
  486                         opp-peak-kBps = <1804000 9600000>;
  487                 };
  488 
  489                 cpu4_opp_941mhz: opp-940800000 {
  490                         opp-hz = /bits/ 64 <940800000>;
  491                         opp-peak-kBps = <2188000 17817600>;
  492                 };
  493 
  494                 cpu4_opp_1229mhz: opp-1228800000 {
  495                         opp-hz = /bits/ 64 <1228800000>;
  496                         opp-peak-kBps = <4068000 24576000>;
  497                 };
  498 
  499                 cpu4_opp_1344mhz: opp-1344000000 {
  500                         opp-hz = /bits/ 64 <1344000000>;
  501                         opp-peak-kBps = <4068000 24576000>;
  502                 };
  503 
  504                 cpu4_opp_1517mhz: opp-1516800000 {
  505                         opp-hz = /bits/ 64 <1516800000>;
  506                         opp-peak-kBps = <4068000 24576000>;
  507                 };
  508 
  509                 cpu4_opp_1651mhz: opp-1651200000 {
  510                         opp-hz = /bits/ 64 <1651200000>;
  511                         opp-peak-kBps = <6220000 38092800>;
  512                 };
  513 
  514                 cpu4_opp_1901mhz: opp-1900800000 {
  515                         opp-hz = /bits/ 64 <1900800000>;
  516                         opp-peak-kBps = <6220000 44851200>;
  517                 };
  518 
  519                 cpu4_opp_2054mhz: opp-2054400000 {
  520                         opp-hz = /bits/ 64 <2054400000>;
  521                         opp-peak-kBps = <6220000 44851200>;
  522                 };
  523 
  524                 cpu4_opp_2112mhz: opp-2112000000 {
  525                         opp-hz = /bits/ 64 <2112000000>;
  526                         opp-peak-kBps = <6220000 44851200>;
  527                 };
  528 
  529                 cpu4_opp_2131mhz: opp-2131200000 {
  530                         opp-hz = /bits/ 64 <2131200000>;
  531                         opp-peak-kBps = <6220000 44851200>;
  532                 };
  533 
  534                 cpu4_opp_2208mhz: opp-2208000000 {
  535                         opp-hz = /bits/ 64 <2208000000>;
  536                         opp-peak-kBps = <6220000 44851200>;
  537                 };
  538 
  539                 cpu4_opp_2400mhz: opp-2400000000 {
  540                         opp-hz = /bits/ 64 <2400000000>;
  541                         opp-peak-kBps = <8532000 48537600>;
  542                 };
  543 
  544                 cpu4_opp_2611mhz: opp-2611200000 {
  545                         opp-hz = /bits/ 64 <2611200000>;
  546                         opp-peak-kBps = <8532000 48537600>;
  547                 };
  548         };
  549 
  550         cpu7_opp_table: opp-table-cpu7 {
  551                 compatible = "operating-points-v2";
  552                 opp-shared;
  553 
  554                 cpu7_opp_806mhz: opp-806400000 {
  555                         opp-hz = /bits/ 64 <806400000>;
  556                         opp-peak-kBps = <1804000 9600000>;
  557                 };
  558 
  559                 cpu7_opp_1056mhz: opp-1056000000 {
  560                         opp-hz = /bits/ 64 <1056000000>;
  561                         opp-peak-kBps = <2188000 17817600>;
  562                 };
  563 
  564                 cpu7_opp_1325mhz: opp-1324800000 {
  565                         opp-hz = /bits/ 64 <1324800000>;
  566                         opp-peak-kBps = <4068000 24576000>;
  567                 };
  568 
  569                 cpu7_opp_1517mhz: opp-1516800000 {
  570                         opp-hz = /bits/ 64 <1516800000>;
  571                         opp-peak-kBps = <4068000 24576000>;
  572                 };
  573 
  574                 cpu7_opp_1766mhz: opp-1766400000 {
  575                         opp-hz = /bits/ 64 <1766400000>;
  576                         opp-peak-kBps = <6220000 38092800>;
  577                 };
  578 
  579                 cpu7_opp_1862mhz: opp-1862400000 {
  580                         opp-hz = /bits/ 64 <1862400000>;
  581                         opp-peak-kBps = <6220000 38092800>;
  582                 };
  583 
  584                 cpu7_opp_2035mhz: opp-2035200000 {
  585                         opp-hz = /bits/ 64 <2035200000>;
  586                         opp-peak-kBps = <6220000 38092800>;
  587                 };
  588 
  589                 cpu7_opp_2112mhz: opp-2112000000 {
  590                         opp-hz = /bits/ 64 <2112000000>;
  591                         opp-peak-kBps = <6220000 44851200>;
  592                 };
  593 
  594                 cpu7_opp_2208mhz: opp-2208000000 {
  595                         opp-hz = /bits/ 64 <2208000000>;
  596                         opp-peak-kBps = <6220000 44851200>;
  597                 };
  598 
  599                 cpu7_opp_2381mhz: opp-2380800000 {
  600                         opp-hz = /bits/ 64 <2380800000>;
  601                         opp-peak-kBps = <6832000 44851200>;
  602                 };
  603 
  604                 cpu7_opp_2400mhz: opp-2400000000 {
  605                         opp-hz = /bits/ 64 <2400000000>;
  606                         opp-peak-kBps = <8532000 48537600>;
  607                 };
  608 
  609                 cpu7_opp_2515mhz: opp-2515200000 {
  610                         opp-hz = /bits/ 64 <2515200000>;
  611                         opp-peak-kBps = <8532000 48537600>;
  612                 };
  613 
  614                 cpu7_opp_2707mhz: opp-2707200000 {
  615                         opp-hz = /bits/ 64 <2707200000>;
  616                         opp-peak-kBps = <8532000 48537600>;
  617                 };
  618 
  619                 cpu7_opp_3014mhz: opp-3014400000 {
  620                         opp-hz = /bits/ 64 <3014400000>;
  621                         opp-peak-kBps = <8532000 48537600>;
  622                 };
  623         };
  624 
  625         memory@80000000 {
  626                 device_type = "memory";
  627                 /* We expect the bootloader to fill in the size */
  628                 reg = <0 0x80000000 0 0>;
  629         };
  630 
  631         firmware {
  632                 scm {
  633                         compatible = "qcom,scm-sc7280", "qcom,scm";
  634                 };
  635         };
  636 
  637         clk_virt: interconnect {
  638                 compatible = "qcom,sc7280-clk-virt";
  639                 #interconnect-cells = <2>;
  640                 qcom,bcm-voters = <&apps_bcm_voter>;
  641         };
  642 
  643         smem {
  644                 compatible = "qcom,smem";
  645                 memory-region = <&smem_mem>;
  646                 hwlocks = <&tcsr_mutex 3>;
  647         };
  648 
  649         smp2p-adsp {
  650                 compatible = "qcom,smp2p";
  651                 qcom,smem = <443>, <429>;
  652                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
  653                                              IPCC_MPROC_SIGNAL_SMP2P
  654                                              IRQ_TYPE_EDGE_RISING>;
  655                 mboxes = <&ipcc IPCC_CLIENT_LPASS
  656                                 IPCC_MPROC_SIGNAL_SMP2P>;
  657 
  658                 qcom,local-pid = <0>;
  659                 qcom,remote-pid = <2>;
  660 
  661                 adsp_smp2p_out: master-kernel {
  662                         qcom,entry-name = "master-kernel";
  663                         #qcom,smem-state-cells = <1>;
  664                 };
  665 
  666                 adsp_smp2p_in: slave-kernel {
  667                         qcom,entry-name = "slave-kernel";
  668                         interrupt-controller;
  669                         #interrupt-cells = <2>;
  670                 };
  671         };
  672 
  673         smp2p-cdsp {
  674                 compatible = "qcom,smp2p";
  675                 qcom,smem = <94>, <432>;
  676                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
  677                                              IPCC_MPROC_SIGNAL_SMP2P
  678                                              IRQ_TYPE_EDGE_RISING>;
  679                 mboxes = <&ipcc IPCC_CLIENT_CDSP
  680                                 IPCC_MPROC_SIGNAL_SMP2P>;
  681 
  682                 qcom,local-pid = <0>;
  683                 qcom,remote-pid = <5>;
  684 
  685                 cdsp_smp2p_out: master-kernel {
  686                         qcom,entry-name = "master-kernel";
  687                         #qcom,smem-state-cells = <1>;
  688                 };
  689 
  690                 cdsp_smp2p_in: slave-kernel {
  691                         qcom,entry-name = "slave-kernel";
  692                         interrupt-controller;
  693                         #interrupt-cells = <2>;
  694                 };
  695         };
  696 
  697         smp2p-mpss {
  698                 compatible = "qcom,smp2p";
  699                 qcom,smem = <435>, <428>;
  700                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
  701                                              IPCC_MPROC_SIGNAL_SMP2P
  702                                              IRQ_TYPE_EDGE_RISING>;
  703                 mboxes = <&ipcc IPCC_CLIENT_MPSS
  704                                 IPCC_MPROC_SIGNAL_SMP2P>;
  705 
  706                 qcom,local-pid = <0>;
  707                 qcom,remote-pid = <1>;
  708 
  709                 modem_smp2p_out: master-kernel {
  710                         qcom,entry-name = "master-kernel";
  711                         #qcom,smem-state-cells = <1>;
  712                 };
  713 
  714                 modem_smp2p_in: slave-kernel {
  715                         qcom,entry-name = "slave-kernel";
  716                         interrupt-controller;
  717                         #interrupt-cells = <2>;
  718                 };
  719 
  720                 ipa_smp2p_out: ipa-ap-to-modem {
  721                         qcom,entry-name = "ipa";
  722                         #qcom,smem-state-cells = <1>;
  723                 };
  724 
  725                 ipa_smp2p_in: ipa-modem-to-ap {
  726                         qcom,entry-name = "ipa";
  727                         interrupt-controller;
  728                         #interrupt-cells = <2>;
  729                 };
  730         };
  731 
  732         smp2p-wpss {
  733                 compatible = "qcom,smp2p";
  734                 qcom,smem = <617>, <616>;
  735                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
  736                                              IPCC_MPROC_SIGNAL_SMP2P
  737                                              IRQ_TYPE_EDGE_RISING>;
  738                 mboxes = <&ipcc IPCC_CLIENT_WPSS
  739                                 IPCC_MPROC_SIGNAL_SMP2P>;
  740 
  741                 qcom,local-pid = <0>;
  742                 qcom,remote-pid = <13>;
  743 
  744                 wpss_smp2p_out: master-kernel {
  745                         qcom,entry-name = "master-kernel";
  746                         #qcom,smem-state-cells = <1>;
  747                 };
  748 
  749                 wpss_smp2p_in: slave-kernel {
  750                         qcom,entry-name = "slave-kernel";
  751                         interrupt-controller;
  752                         #interrupt-cells = <2>;
  753                 };
  754         };
  755 
  756         pmu {
  757                 compatible = "arm,armv8-pmuv3";
  758                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
  759         };
  760 
  761         psci {
  762                 compatible = "arm,psci-1.0";
  763                 method = "smc";
  764         };
  765 
  766         qspi_opp_table: opp-table-qspi {
  767                 compatible = "operating-points-v2";
  768 
  769                 opp-75000000 {
  770                         opp-hz = /bits/ 64 <75000000>;
  771                         required-opps = <&rpmhpd_opp_low_svs>;
  772                 };
  773 
  774                 opp-150000000 {
  775                         opp-hz = /bits/ 64 <150000000>;
  776                         required-opps = <&rpmhpd_opp_svs>;
  777                 };
  778 
  779                 opp-200000000 {
  780                         opp-hz = /bits/ 64 <200000000>;
  781                         required-opps = <&rpmhpd_opp_svs_l1>;
  782                 };
  783 
  784                 opp-300000000 {
  785                         opp-hz = /bits/ 64 <300000000>;
  786                         required-opps = <&rpmhpd_opp_nom>;
  787                 };
  788         };
  789 
  790         qup_opp_table: opp-table-qup {
  791                 compatible = "operating-points-v2";
  792 
  793                 opp-75000000 {
  794                         opp-hz = /bits/ 64 <75000000>;
  795                         required-opps = <&rpmhpd_opp_low_svs>;
  796                 };
  797 
  798                 opp-100000000 {
  799                         opp-hz = /bits/ 64 <100000000>;
  800                         required-opps = <&rpmhpd_opp_svs>;
  801                 };
  802 
  803                 opp-128000000 {
  804                         opp-hz = /bits/ 64 <128000000>;
  805                         required-opps = <&rpmhpd_opp_nom>;
  806                 };
  807         };
  808 
  809         soc: soc@0 {
  810                 #address-cells = <2>;
  811                 #size-cells = <2>;
  812                 ranges = <0 0 0 0 0x10 0>;
  813                 dma-ranges = <0 0 0 0 0x10 0>;
  814                 compatible = "simple-bus";
  815 
  816                 gcc: clock-controller@100000 {
  817                         compatible = "qcom,gcc-sc7280";
  818                         reg = <0 0x00100000 0 0x1f0000>;
  819                         clocks = <&rpmhcc RPMH_CXO_CLK>,
  820                                  <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
  821                                  <0>, <&pcie1_lane>,
  822                                  <0>, <0>, <0>, <0>;
  823                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
  824                                       "pcie_0_pipe_clk", "pcie_1_pipe_clk",
  825                                       "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
  826                                       "ufs_phy_tx_symbol_0_clk",
  827                                       "usb3_phy_wrapper_gcc_usb30_pipe_clk";
  828                         #clock-cells = <1>;
  829                         #reset-cells = <1>;
  830                         #power-domain-cells = <1>;
  831                 };
  832 
  833                 ipcc: mailbox@408000 {
  834                         compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
  835                         reg = <0 0x00408000 0 0x1000>;
  836                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
  837                         interrupt-controller;
  838                         #interrupt-cells = <3>;
  839                         #mbox-cells = <2>;
  840                 };
  841 
  842                 qfprom: efuse@784000 {
  843                         compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
  844                         reg = <0 0x00784000 0 0xa20>,
  845                               <0 0x00780000 0 0xa20>,
  846                               <0 0x00782000 0 0x120>,
  847                               <0 0x00786000 0 0x1fff>;
  848                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
  849                         clock-names = "core";
  850                         power-domains = <&rpmhpd SC7280_MX>;
  851                         #address-cells = <1>;
  852                         #size-cells = <1>;
  853 
  854                         gpu_speed_bin: gpu_speed_bin@1e9 {
  855                                 reg = <0x1e9 0x2>;
  856                                 bits = <5 8>;
  857                         };
  858                 };
  859 
  860                 sdhc_1: mmc@7c4000 {
  861                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
  862                         pinctrl-names = "default", "sleep";
  863                         pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
  864                         pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
  865                         status = "disabled";
  866 
  867                         reg = <0 0x007c4000 0 0x1000>,
  868                               <0 0x007c5000 0 0x1000>;
  869                         reg-names = "hc", "cqhci";
  870 
  871                         iommus = <&apps_smmu 0xc0 0x0>;
  872                         interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
  873                                      <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
  874                         interrupt-names = "hc_irq", "pwr_irq";
  875 
  876                         clocks = <&gcc GCC_SDCC1_AHB_CLK>,
  877                                  <&gcc GCC_SDCC1_APPS_CLK>,
  878                                  <&rpmhcc RPMH_CXO_CLK>;
  879                         clock-names = "iface", "core", "xo";
  880                         interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
  881                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
  882                         interconnect-names = "sdhc-ddr","cpu-sdhc";
  883                         power-domains = <&rpmhpd SC7280_CX>;
  884                         operating-points-v2 = <&sdhc1_opp_table>;
  885 
  886                         bus-width = <8>;
  887                         supports-cqe;
  888 
  889                         qcom,dll-config = <0x0007642c>;
  890                         qcom,ddr-config = <0x80040868>;
  891 
  892                         mmc-ddr-1_8v;
  893                         mmc-hs200-1_8v;
  894                         mmc-hs400-1_8v;
  895                         mmc-hs400-enhanced-strobe;
  896 
  897                         resets = <&gcc GCC_SDCC1_BCR>;
  898 
  899                         sdhc1_opp_table: opp-table {
  900                                 compatible = "operating-points-v2";
  901 
  902                                 opp-100000000 {
  903                                         opp-hz = /bits/ 64 <100000000>;
  904                                         required-opps = <&rpmhpd_opp_low_svs>;
  905                                         opp-peak-kBps = <1800000 400000>;
  906                                         opp-avg-kBps = <100000 0>;
  907                                 };
  908 
  909                                 opp-384000000 {
  910                                         opp-hz = /bits/ 64 <384000000>;
  911                                         required-opps = <&rpmhpd_opp_nom>;
  912                                         opp-peak-kBps = <5400000 1600000>;
  913                                         opp-avg-kBps = <390000 0>;
  914                                 };
  915                         };
  916 
  917                 };
  918 
  919                 gpi_dma0: dma-controller@900000 {
  920                         #dma-cells = <3>;
  921                         compatible = "qcom,sc7280-gpi-dma";
  922                         reg = <0 0x00900000 0 0x60000>;
  923                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
  924                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
  925                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
  926                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
  927                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
  928                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
  929                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
  930                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
  931                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
  932                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
  933                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
  934                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
  935                         dma-channels = <12>;
  936                         dma-channel-mask = <0x7f>;
  937                         iommus = <&apps_smmu 0x0136 0x0>;
  938                         status = "disabled";
  939                 };
  940 
  941                 qupv3_id_0: geniqup@9c0000 {
  942                         compatible = "qcom,geni-se-qup";
  943                         reg = <0 0x009c0000 0 0x2000>;
  944                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
  945                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
  946                         clock-names = "m-ahb", "s-ahb";
  947                         #address-cells = <2>;
  948                         #size-cells = <2>;
  949                         ranges;
  950                         iommus = <&apps_smmu 0x123 0x0>;
  951                         status = "disabled";
  952 
  953                         i2c0: i2c@980000 {
  954                                 compatible = "qcom,geni-i2c";
  955                                 reg = <0 0x00980000 0 0x4000>;
  956                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
  957                                 clock-names = "se";
  958                                 pinctrl-names = "default";
  959                                 pinctrl-0 = <&qup_i2c0_data_clk>;
  960                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
  961                                 #address-cells = <1>;
  962                                 #size-cells = <0>;
  963                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
  964                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
  965                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
  966                                 interconnect-names = "qup-core", "qup-config",
  967                                                         "qup-memory";
  968                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
  969                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
  970                                 dma-names = "tx", "rx";
  971                                 status = "disabled";
  972                         };
  973 
  974                         spi0: spi@980000 {
  975                                 compatible = "qcom,geni-spi";
  976                                 reg = <0 0x00980000 0 0x4000>;
  977                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
  978                                 clock-names = "se";
  979                                 pinctrl-names = "default";
  980                                 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
  981                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
  982                                 #address-cells = <1>;
  983                                 #size-cells = <0>;
  984                                 power-domains = <&rpmhpd SC7280_CX>;
  985                                 operating-points-v2 = <&qup_opp_table>;
  986                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
  987                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
  988                                 interconnect-names = "qup-core", "qup-config";
  989                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
  990                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
  991                                 dma-names = "tx", "rx";
  992                                 status = "disabled";
  993                         };
  994 
  995                         uart0: serial@980000 {
  996                                 compatible = "qcom,geni-uart";
  997                                 reg = <0 0x00980000 0 0x4000>;
  998                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
  999                                 clock-names = "se";
 1000                                 pinctrl-names = "default";
 1001                                 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
 1002                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 1003                                 power-domains = <&rpmhpd SC7280_CX>;
 1004                                 operating-points-v2 = <&qup_opp_table>;
 1005                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1006                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1007                                 interconnect-names = "qup-core", "qup-config";
 1008                                 status = "disabled";
 1009                         };
 1010 
 1011                         i2c1: i2c@984000 {
 1012                                 compatible = "qcom,geni-i2c";
 1013                                 reg = <0 0x00984000 0 0x4000>;
 1014                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 1015                                 clock-names = "se";
 1016                                 pinctrl-names = "default";
 1017                                 pinctrl-0 = <&qup_i2c1_data_clk>;
 1018                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 1019                                 #address-cells = <1>;
 1020                                 #size-cells = <0>;
 1021                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1022                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1023                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1024                                 interconnect-names = "qup-core", "qup-config",
 1025                                                         "qup-memory";
 1026                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 1027                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 1028                                 dma-names = "tx", "rx";
 1029                                 status = "disabled";
 1030                         };
 1031 
 1032                         spi1: spi@984000 {
 1033                                 compatible = "qcom,geni-spi";
 1034                                 reg = <0 0x00984000 0 0x4000>;
 1035                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 1036                                 clock-names = "se";
 1037                                 pinctrl-names = "default";
 1038                                 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
 1039                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 1040                                 #address-cells = <1>;
 1041                                 #size-cells = <0>;
 1042                                 power-domains = <&rpmhpd SC7280_CX>;
 1043                                 operating-points-v2 = <&qup_opp_table>;
 1044                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1045                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1046                                 interconnect-names = "qup-core", "qup-config";
 1047                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 1048                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 1049                                 dma-names = "tx", "rx";
 1050                                 status = "disabled";
 1051                         };
 1052 
 1053                         uart1: serial@984000 {
 1054                                 compatible = "qcom,geni-uart";
 1055                                 reg = <0 0x00984000 0 0x4000>;
 1056                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 1057                                 clock-names = "se";
 1058                                 pinctrl-names = "default";
 1059                                 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
 1060                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 1061                                 power-domains = <&rpmhpd SC7280_CX>;
 1062                                 operating-points-v2 = <&qup_opp_table>;
 1063                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1064                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1065                                 interconnect-names = "qup-core", "qup-config";
 1066                                 status = "disabled";
 1067                         };
 1068 
 1069                         i2c2: i2c@988000 {
 1070                                 compatible = "qcom,geni-i2c";
 1071                                 reg = <0 0x00988000 0 0x4000>;
 1072                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 1073                                 clock-names = "se";
 1074                                 pinctrl-names = "default";
 1075                                 pinctrl-0 = <&qup_i2c2_data_clk>;
 1076                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 1077                                 #address-cells = <1>;
 1078                                 #size-cells = <0>;
 1079                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1080                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1081                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1082                                 interconnect-names = "qup-core", "qup-config",
 1083                                                         "qup-memory";
 1084                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 1085                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 1086                                 dma-names = "tx", "rx";
 1087                                 status = "disabled";
 1088                         };
 1089 
 1090                         spi2: spi@988000 {
 1091                                 compatible = "qcom,geni-spi";
 1092                                 reg = <0 0x00988000 0 0x4000>;
 1093                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 1094                                 clock-names = "se";
 1095                                 pinctrl-names = "default";
 1096                                 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
 1097                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 1098                                 #address-cells = <1>;
 1099                                 #size-cells = <0>;
 1100                                 power-domains = <&rpmhpd SC7280_CX>;
 1101                                 operating-points-v2 = <&qup_opp_table>;
 1102                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1103                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1104                                 interconnect-names = "qup-core", "qup-config";
 1105                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
 1106                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
 1107                                 dma-names = "tx", "rx";
 1108                                 status = "disabled";
 1109                         };
 1110 
 1111                         uart2: serial@988000 {
 1112                                 compatible = "qcom,geni-uart";
 1113                                 reg = <0 0x00988000 0 0x4000>;
 1114                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 1115                                 clock-names = "se";
 1116                                 pinctrl-names = "default";
 1117                                 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
 1118                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 1119                                 power-domains = <&rpmhpd SC7280_CX>;
 1120                                 operating-points-v2 = <&qup_opp_table>;
 1121                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1122                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1123                                 interconnect-names = "qup-core", "qup-config";
 1124                                 status = "disabled";
 1125                         };
 1126 
 1127                         i2c3: i2c@98c000 {
 1128                                 compatible = "qcom,geni-i2c";
 1129                                 reg = <0 0x0098c000 0 0x4000>;
 1130                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 1131                                 clock-names = "se";
 1132                                 pinctrl-names = "default";
 1133                                 pinctrl-0 = <&qup_i2c3_data_clk>;
 1134                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 1135                                 #address-cells = <1>;
 1136                                 #size-cells = <0>;
 1137                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1138                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1139                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1140                                 interconnect-names = "qup-core", "qup-config",
 1141                                                         "qup-memory";
 1142                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 1143                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 1144                                 dma-names = "tx", "rx";
 1145                                 status = "disabled";
 1146                         };
 1147 
 1148                         spi3: spi@98c000 {
 1149                                 compatible = "qcom,geni-spi";
 1150                                 reg = <0 0x0098c000 0 0x4000>;
 1151                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 1152                                 clock-names = "se";
 1153                                 pinctrl-names = "default";
 1154                                 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
 1155                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 1156                                 #address-cells = <1>;
 1157                                 #size-cells = <0>;
 1158                                 power-domains = <&rpmhpd SC7280_CX>;
 1159                                 operating-points-v2 = <&qup_opp_table>;
 1160                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1161                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1162                                 interconnect-names = "qup-core", "qup-config";
 1163                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
 1164                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
 1165                                 dma-names = "tx", "rx";
 1166                                 status = "disabled";
 1167                         };
 1168 
 1169                         uart3: serial@98c000 {
 1170                                 compatible = "qcom,geni-uart";
 1171                                 reg = <0 0x0098c000 0 0x4000>;
 1172                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 1173                                 clock-names = "se";
 1174                                 pinctrl-names = "default";
 1175                                 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
 1176                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 1177                                 power-domains = <&rpmhpd SC7280_CX>;
 1178                                 operating-points-v2 = <&qup_opp_table>;
 1179                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1180                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1181                                 interconnect-names = "qup-core", "qup-config";
 1182                                 status = "disabled";
 1183                         };
 1184 
 1185                         i2c4: i2c@990000 {
 1186                                 compatible = "qcom,geni-i2c";
 1187                                 reg = <0 0x00990000 0 0x4000>;
 1188                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 1189                                 clock-names = "se";
 1190                                 pinctrl-names = "default";
 1191                                 pinctrl-0 = <&qup_i2c4_data_clk>;
 1192                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 1193                                 #address-cells = <1>;
 1194                                 #size-cells = <0>;
 1195                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1196                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1197                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1198                                 interconnect-names = "qup-core", "qup-config",
 1199                                                         "qup-memory";
 1200                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 1201                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 1202                                 dma-names = "tx", "rx";
 1203                                 status = "disabled";
 1204                         };
 1205 
 1206                         spi4: spi@990000 {
 1207                                 compatible = "qcom,geni-spi";
 1208                                 reg = <0 0x00990000 0 0x4000>;
 1209                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 1210                                 clock-names = "se";
 1211                                 pinctrl-names = "default";
 1212                                 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
 1213                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 1214                                 #address-cells = <1>;
 1215                                 #size-cells = <0>;
 1216                                 power-domains = <&rpmhpd SC7280_CX>;
 1217                                 operating-points-v2 = <&qup_opp_table>;
 1218                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1219                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1220                                 interconnect-names = "qup-core", "qup-config";
 1221                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
 1222                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
 1223                                 dma-names = "tx", "rx";
 1224                                 status = "disabled";
 1225                         };
 1226 
 1227                         uart4: serial@990000 {
 1228                                 compatible = "qcom,geni-uart";
 1229                                 reg = <0 0x00990000 0 0x4000>;
 1230                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 1231                                 clock-names = "se";
 1232                                 pinctrl-names = "default";
 1233                                 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
 1234                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 1235                                 power-domains = <&rpmhpd SC7280_CX>;
 1236                                 operating-points-v2 = <&qup_opp_table>;
 1237                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1238                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1239                                 interconnect-names = "qup-core", "qup-config";
 1240                                 status = "disabled";
 1241                         };
 1242 
 1243                         i2c5: i2c@994000 {
 1244                                 compatible = "qcom,geni-i2c";
 1245                                 reg = <0 0x00994000 0 0x4000>;
 1246                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 1247                                 clock-names = "se";
 1248                                 pinctrl-names = "default";
 1249                                 pinctrl-0 = <&qup_i2c5_data_clk>;
 1250                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 1251                                 #address-cells = <1>;
 1252                                 #size-cells = <0>;
 1253                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1254                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1255                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1256                                 interconnect-names = "qup-core", "qup-config",
 1257                                                         "qup-memory";
 1258                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
 1259                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
 1260                                 dma-names = "tx", "rx";
 1261                                 status = "disabled";
 1262                         };
 1263 
 1264                         spi5: spi@994000 {
 1265                                 compatible = "qcom,geni-spi";
 1266                                 reg = <0 0x00994000 0 0x4000>;
 1267                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 1268                                 clock-names = "se";
 1269                                 pinctrl-names = "default";
 1270                                 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
 1271                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 1272                                 #address-cells = <1>;
 1273                                 #size-cells = <0>;
 1274                                 power-domains = <&rpmhpd SC7280_CX>;
 1275                                 operating-points-v2 = <&qup_opp_table>;
 1276                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1277                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1278                                 interconnect-names = "qup-core", "qup-config";
 1279                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
 1280                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
 1281                                 dma-names = "tx", "rx";
 1282                                 status = "disabled";
 1283                         };
 1284 
 1285                         uart5: serial@994000 {
 1286                                 compatible = "qcom,geni-uart";
 1287                                 reg = <0 0x00994000 0 0x4000>;
 1288                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 1289                                 clock-names = "se";
 1290                                 pinctrl-names = "default";
 1291                                 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
 1292                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 1293                                 power-domains = <&rpmhpd SC7280_CX>;
 1294                                 operating-points-v2 = <&qup_opp_table>;
 1295                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1296                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1297                                 interconnect-names = "qup-core", "qup-config";
 1298                                 status = "disabled";
 1299                         };
 1300 
 1301                         i2c6: i2c@998000 {
 1302                                 compatible = "qcom,geni-i2c";
 1303                                 reg = <0 0x00998000 0 0x4000>;
 1304                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 1305                                 clock-names = "se";
 1306                                 pinctrl-names = "default";
 1307                                 pinctrl-0 = <&qup_i2c6_data_clk>;
 1308                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 1309                                 #address-cells = <1>;
 1310                                 #size-cells = <0>;
 1311                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1312                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1313                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1314                                 interconnect-names = "qup-core", "qup-config",
 1315                                                         "qup-memory";
 1316                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
 1317                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
 1318                                 dma-names = "tx", "rx";
 1319                                 status = "disabled";
 1320                         };
 1321 
 1322                         spi6: spi@998000 {
 1323                                 compatible = "qcom,geni-spi";
 1324                                 reg = <0 0x00998000 0 0x4000>;
 1325                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 1326                                 clock-names = "se";
 1327                                 pinctrl-names = "default";
 1328                                 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
 1329                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 1330                                 #address-cells = <1>;
 1331                                 #size-cells = <0>;
 1332                                 power-domains = <&rpmhpd SC7280_CX>;
 1333                                 operating-points-v2 = <&qup_opp_table>;
 1334                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1335                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1336                                 interconnect-names = "qup-core", "qup-config";
 1337                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
 1338                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
 1339                                 dma-names = "tx", "rx";
 1340                                 status = "disabled";
 1341                         };
 1342 
 1343                         uart6: serial@998000 {
 1344                                 compatible = "qcom,geni-uart";
 1345                                 reg = <0 0x00998000 0 0x4000>;
 1346                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 1347                                 clock-names = "se";
 1348                                 pinctrl-names = "default";
 1349                                 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
 1350                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 1351                                 power-domains = <&rpmhpd SC7280_CX>;
 1352                                 operating-points-v2 = <&qup_opp_table>;
 1353                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1354                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1355                                 interconnect-names = "qup-core", "qup-config";
 1356                                 status = "disabled";
 1357                         };
 1358 
 1359                         i2c7: i2c@99c000 {
 1360                                 compatible = "qcom,geni-i2c";
 1361                                 reg = <0 0x0099c000 0 0x4000>;
 1362                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 1363                                 clock-names = "se";
 1364                                 pinctrl-names = "default";
 1365                                 pinctrl-0 = <&qup_i2c7_data_clk>;
 1366                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 1367                                 #address-cells = <1>;
 1368                                 #size-cells = <0>;
 1369                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1370                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
 1371                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 1372                                 interconnect-names = "qup-core", "qup-config",
 1373                                                         "qup-memory";
 1374                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
 1375                                        <&gpi_dma0 1 7 QCOM_GPI_I2C>;
 1376                                 dma-names = "tx", "rx";
 1377                                 status = "disabled";
 1378                         };
 1379 
 1380                         spi7: spi@99c000 {
 1381                                 compatible = "qcom,geni-spi";
 1382                                 reg = <0 0x0099c000 0 0x4000>;
 1383                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 1384                                 clock-names = "se";
 1385                                 pinctrl-names = "default";
 1386                                 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
 1387                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 1388                                 #address-cells = <1>;
 1389                                 #size-cells = <0>;
 1390                                 power-domains = <&rpmhpd SC7280_CX>;
 1391                                 operating-points-v2 = <&qup_opp_table>;
 1392                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1393                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1394                                 interconnect-names = "qup-core", "qup-config";
 1395                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
 1396                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
 1397                                 dma-names = "tx", "rx";
 1398                                 status = "disabled";
 1399                         };
 1400 
 1401                         uart7: serial@99c000 {
 1402                                 compatible = "qcom,geni-uart";
 1403                                 reg = <0 0x0099c000 0 0x4000>;
 1404                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 1405                                 clock-names = "se";
 1406                                 pinctrl-names = "default";
 1407                                 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
 1408                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 1409                                 power-domains = <&rpmhpd SC7280_CX>;
 1410                                 operating-points-v2 = <&qup_opp_table>;
 1411                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
 1412                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
 1413                                 interconnect-names = "qup-core", "qup-config";
 1414                                 status = "disabled";
 1415                         };
 1416                 };
 1417 
 1418                 gpi_dma1: dma-controller@a00000 {
 1419                         #dma-cells = <3>;
 1420                         compatible = "qcom,sc7280-gpi-dma";
 1421                         reg = <0 0x00a00000 0 0x60000>;
 1422                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 1423                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 1424                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 1425                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 1426                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 1427                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 1428                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
 1429                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
 1430                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
 1431                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 1432                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 1433                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
 1434                         dma-channels = <12>;
 1435                         dma-channel-mask = <0x1e>;
 1436                         iommus = <&apps_smmu 0x56 0x0>;
 1437                         status = "disabled";
 1438                 };
 1439 
 1440                 qupv3_id_1: geniqup@ac0000 {
 1441                         compatible = "qcom,geni-se-qup";
 1442                         reg = <0 0x00ac0000 0 0x2000>;
 1443                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 1444                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 1445                         clock-names = "m-ahb", "s-ahb";
 1446                         #address-cells = <2>;
 1447                         #size-cells = <2>;
 1448                         ranges;
 1449                         iommus = <&apps_smmu 0x43 0x0>;
 1450                         status = "disabled";
 1451 
 1452                         i2c8: i2c@a80000 {
 1453                                 compatible = "qcom,geni-i2c";
 1454                                 reg = <0 0x00a80000 0 0x4000>;
 1455                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 1456                                 clock-names = "se";
 1457                                 pinctrl-names = "default";
 1458                                 pinctrl-0 = <&qup_i2c8_data_clk>;
 1459                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 1460                                 #address-cells = <1>;
 1461                                 #size-cells = <0>;
 1462                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1463                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1464                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1465                                 interconnect-names = "qup-core", "qup-config",
 1466                                                         "qup-memory";
 1467                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
 1468                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
 1469                                 dma-names = "tx", "rx";
 1470                                 status = "disabled";
 1471                         };
 1472 
 1473                         spi8: spi@a80000 {
 1474                                 compatible = "qcom,geni-spi";
 1475                                 reg = <0 0x00a80000 0 0x4000>;
 1476                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 1477                                 clock-names = "se";
 1478                                 pinctrl-names = "default";
 1479                                 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
 1480                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 1481                                 #address-cells = <1>;
 1482                                 #size-cells = <0>;
 1483                                 power-domains = <&rpmhpd SC7280_CX>;
 1484                                 operating-points-v2 = <&qup_opp_table>;
 1485                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1486                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1487                                 interconnect-names = "qup-core", "qup-config";
 1488                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
 1489                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
 1490                                 dma-names = "tx", "rx";
 1491                                 status = "disabled";
 1492                         };
 1493 
 1494                         uart8: serial@a80000 {
 1495                                 compatible = "qcom,geni-uart";
 1496                                 reg = <0 0x00a80000 0 0x4000>;
 1497                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 1498                                 clock-names = "se";
 1499                                 pinctrl-names = "default";
 1500                                 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
 1501                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 1502                                 power-domains = <&rpmhpd SC7280_CX>;
 1503                                 operating-points-v2 = <&qup_opp_table>;
 1504                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1505                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1506                                 interconnect-names = "qup-core", "qup-config";
 1507                                 status = "disabled";
 1508                         };
 1509 
 1510                         i2c9: i2c@a84000 {
 1511                                 compatible = "qcom,geni-i2c";
 1512                                 reg = <0 0x00a84000 0 0x4000>;
 1513                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 1514                                 clock-names = "se";
 1515                                 pinctrl-names = "default";
 1516                                 pinctrl-0 = <&qup_i2c9_data_clk>;
 1517                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 1518                                 #address-cells = <1>;
 1519                                 #size-cells = <0>;
 1520                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1521                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1522                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1523                                 interconnect-names = "qup-core", "qup-config",
 1524                                                         "qup-memory";
 1525                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
 1526                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
 1527                                 dma-names = "tx", "rx";
 1528                                 status = "disabled";
 1529                         };
 1530 
 1531                         spi9: spi@a84000 {
 1532                                 compatible = "qcom,geni-spi";
 1533                                 reg = <0 0x00a84000 0 0x4000>;
 1534                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 1535                                 clock-names = "se";
 1536                                 pinctrl-names = "default";
 1537                                 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
 1538                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 1539                                 #address-cells = <1>;
 1540                                 #size-cells = <0>;
 1541                                 power-domains = <&rpmhpd SC7280_CX>;
 1542                                 operating-points-v2 = <&qup_opp_table>;
 1543                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1544                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1545                                 interconnect-names = "qup-core", "qup-config";
 1546                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
 1547                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
 1548                                 dma-names = "tx", "rx";
 1549                                 status = "disabled";
 1550                         };
 1551 
 1552                         uart9: serial@a84000 {
 1553                                 compatible = "qcom,geni-uart";
 1554                                 reg = <0 0x00a84000 0 0x4000>;
 1555                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 1556                                 clock-names = "se";
 1557                                 pinctrl-names = "default";
 1558                                 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
 1559                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 1560                                 power-domains = <&rpmhpd SC7280_CX>;
 1561                                 operating-points-v2 = <&qup_opp_table>;
 1562                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1563                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1564                                 interconnect-names = "qup-core", "qup-config";
 1565                                 status = "disabled";
 1566                         };
 1567 
 1568                         i2c10: i2c@a88000 {
 1569                                 compatible = "qcom,geni-i2c";
 1570                                 reg = <0 0x00a88000 0 0x4000>;
 1571                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 1572                                 clock-names = "se";
 1573                                 pinctrl-names = "default";
 1574                                 pinctrl-0 = <&qup_i2c10_data_clk>;
 1575                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 1576                                 #address-cells = <1>;
 1577                                 #size-cells = <0>;
 1578                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1579                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1580                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1581                                 interconnect-names = "qup-core", "qup-config",
 1582                                                         "qup-memory";
 1583                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
 1584                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
 1585                                 dma-names = "tx", "rx";
 1586                                 status = "disabled";
 1587                         };
 1588 
 1589                         spi10: spi@a88000 {
 1590                                 compatible = "qcom,geni-spi";
 1591                                 reg = <0 0x00a88000 0 0x4000>;
 1592                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 1593                                 clock-names = "se";
 1594                                 pinctrl-names = "default";
 1595                                 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
 1596                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 1597                                 #address-cells = <1>;
 1598                                 #size-cells = <0>;
 1599                                 power-domains = <&rpmhpd SC7280_CX>;
 1600                                 operating-points-v2 = <&qup_opp_table>;
 1601                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1602                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1603                                 interconnect-names = "qup-core", "qup-config";
 1604                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
 1605                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
 1606                                 dma-names = "tx", "rx";
 1607                                 status = "disabled";
 1608                         };
 1609 
 1610                         uart10: serial@a88000 {
 1611                                 compatible = "qcom,geni-uart";
 1612                                 reg = <0 0x00a88000 0 0x4000>;
 1613                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 1614                                 clock-names = "se";
 1615                                 pinctrl-names = "default";
 1616                                 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
 1617                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 1618                                 power-domains = <&rpmhpd SC7280_CX>;
 1619                                 operating-points-v2 = <&qup_opp_table>;
 1620                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1621                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1622                                 interconnect-names = "qup-core", "qup-config";
 1623                                 status = "disabled";
 1624                         };
 1625 
 1626                         i2c11: i2c@a8c000 {
 1627                                 compatible = "qcom,geni-i2c";
 1628                                 reg = <0 0x00a8c000 0 0x4000>;
 1629                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 1630                                 clock-names = "se";
 1631                                 pinctrl-names = "default";
 1632                                 pinctrl-0 = <&qup_i2c11_data_clk>;
 1633                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 1634                                 #address-cells = <1>;
 1635                                 #size-cells = <0>;
 1636                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1637                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1638                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1639                                 interconnect-names = "qup-core", "qup-config",
 1640                                                         "qup-memory";
 1641                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
 1642                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
 1643                                 dma-names = "tx", "rx";
 1644                                 status = "disabled";
 1645                         };
 1646 
 1647                         spi11: spi@a8c000 {
 1648                                 compatible = "qcom,geni-spi";
 1649                                 reg = <0 0x00a8c000 0 0x4000>;
 1650                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 1651                                 clock-names = "se";
 1652                                 pinctrl-names = "default";
 1653                                 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
 1654                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 1655                                 #address-cells = <1>;
 1656                                 #size-cells = <0>;
 1657                                 power-domains = <&rpmhpd SC7280_CX>;
 1658                                 operating-points-v2 = <&qup_opp_table>;
 1659                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1660                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1661                                 interconnect-names = "qup-core", "qup-config";
 1662                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
 1663                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
 1664                                 dma-names = "tx", "rx";
 1665                                 status = "disabled";
 1666                         };
 1667 
 1668                         uart11: serial@a8c000 {
 1669                                 compatible = "qcom,geni-uart";
 1670                                 reg = <0 0x00a8c000 0 0x4000>;
 1671                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 1672                                 clock-names = "se";
 1673                                 pinctrl-names = "default";
 1674                                 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
 1675                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 1676                                 power-domains = <&rpmhpd SC7280_CX>;
 1677                                 operating-points-v2 = <&qup_opp_table>;
 1678                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1679                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1680                                 interconnect-names = "qup-core", "qup-config";
 1681                                 status = "disabled";
 1682                         };
 1683 
 1684                         i2c12: i2c@a90000 {
 1685                                 compatible = "qcom,geni-i2c";
 1686                                 reg = <0 0x00a90000 0 0x4000>;
 1687                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 1688                                 clock-names = "se";
 1689                                 pinctrl-names = "default";
 1690                                 pinctrl-0 = <&qup_i2c12_data_clk>;
 1691                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 1692                                 #address-cells = <1>;
 1693                                 #size-cells = <0>;
 1694                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1695                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1696                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1697                                 interconnect-names = "qup-core", "qup-config",
 1698                                                         "qup-memory";
 1699                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
 1700                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
 1701                                 dma-names = "tx", "rx";
 1702                                 status = "disabled";
 1703                         };
 1704 
 1705                         spi12: spi@a90000 {
 1706                                 compatible = "qcom,geni-spi";
 1707                                 reg = <0 0x00a90000 0 0x4000>;
 1708                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 1709                                 clock-names = "se";
 1710                                 pinctrl-names = "default";
 1711                                 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
 1712                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 1713                                 #address-cells = <1>;
 1714                                 #size-cells = <0>;
 1715                                 power-domains = <&rpmhpd SC7280_CX>;
 1716                                 operating-points-v2 = <&qup_opp_table>;
 1717                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1718                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1719                                 interconnect-names = "qup-core", "qup-config";
 1720                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
 1721                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
 1722                                 dma-names = "tx", "rx";
 1723                                 status = "disabled";
 1724                         };
 1725 
 1726                         uart12: serial@a90000 {
 1727                                 compatible = "qcom,geni-uart";
 1728                                 reg = <0 0x00a90000 0 0x4000>;
 1729                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 1730                                 clock-names = "se";
 1731                                 pinctrl-names = "default";
 1732                                 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
 1733                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 1734                                 power-domains = <&rpmhpd SC7280_CX>;
 1735                                 operating-points-v2 = <&qup_opp_table>;
 1736                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1737                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1738                                 interconnect-names = "qup-core", "qup-config";
 1739                                 status = "disabled";
 1740                         };
 1741 
 1742                         i2c13: i2c@a94000 {
 1743                                 compatible = "qcom,geni-i2c";
 1744                                 reg = <0 0x00a94000 0 0x4000>;
 1745                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 1746                                 clock-names = "se";
 1747                                 pinctrl-names = "default";
 1748                                 pinctrl-0 = <&qup_i2c13_data_clk>;
 1749                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 1750                                 #address-cells = <1>;
 1751                                 #size-cells = <0>;
 1752                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1753                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1754                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1755                                 interconnect-names = "qup-core", "qup-config",
 1756                                                         "qup-memory";
 1757                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
 1758                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
 1759                                 dma-names = "tx", "rx";
 1760                                 status = "disabled";
 1761                         };
 1762 
 1763                         spi13: spi@a94000 {
 1764                                 compatible = "qcom,geni-spi";
 1765                                 reg = <0 0x00a94000 0 0x4000>;
 1766                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 1767                                 clock-names = "se";
 1768                                 pinctrl-names = "default";
 1769                                 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
 1770                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 1771                                 #address-cells = <1>;
 1772                                 #size-cells = <0>;
 1773                                 power-domains = <&rpmhpd SC7280_CX>;
 1774                                 operating-points-v2 = <&qup_opp_table>;
 1775                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1776                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1777                                 interconnect-names = "qup-core", "qup-config";
 1778                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
 1779                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
 1780                                 dma-names = "tx", "rx";
 1781                                 status = "disabled";
 1782                         };
 1783 
 1784                         uart13: serial@a94000 {
 1785                                 compatible = "qcom,geni-uart";
 1786                                 reg = <0 0x00a94000 0 0x4000>;
 1787                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 1788                                 clock-names = "se";
 1789                                 pinctrl-names = "default";
 1790                                 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
 1791                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 1792                                 power-domains = <&rpmhpd SC7280_CX>;
 1793                                 operating-points-v2 = <&qup_opp_table>;
 1794                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1795                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1796                                 interconnect-names = "qup-core", "qup-config";
 1797                                 status = "disabled";
 1798                         };
 1799 
 1800                         i2c14: i2c@a98000 {
 1801                                 compatible = "qcom,geni-i2c";
 1802                                 reg = <0 0x00a98000 0 0x4000>;
 1803                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 1804                                 clock-names = "se";
 1805                                 pinctrl-names = "default";
 1806                                 pinctrl-0 = <&qup_i2c14_data_clk>;
 1807                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 1808                                 #address-cells = <1>;
 1809                                 #size-cells = <0>;
 1810                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1811                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1812                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1813                                 interconnect-names = "qup-core", "qup-config",
 1814                                                         "qup-memory";
 1815                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
 1816                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
 1817                                 dma-names = "tx", "rx";
 1818                                 status = "disabled";
 1819                         };
 1820 
 1821                         spi14: spi@a98000 {
 1822                                 compatible = "qcom,geni-spi";
 1823                                 reg = <0 0x00a98000 0 0x4000>;
 1824                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 1825                                 clock-names = "se";
 1826                                 pinctrl-names = "default";
 1827                                 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
 1828                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 1829                                 #address-cells = <1>;
 1830                                 #size-cells = <0>;
 1831                                 power-domains = <&rpmhpd SC7280_CX>;
 1832                                 operating-points-v2 = <&qup_opp_table>;
 1833                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1834                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1835                                 interconnect-names = "qup-core", "qup-config";
 1836                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
 1837                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
 1838                                 dma-names = "tx", "rx";
 1839                                 status = "disabled";
 1840                         };
 1841 
 1842                         uart14: serial@a98000 {
 1843                                 compatible = "qcom,geni-uart";
 1844                                 reg = <0 0x00a98000 0 0x4000>;
 1845                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 1846                                 clock-names = "se";
 1847                                 pinctrl-names = "default";
 1848                                 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
 1849                                 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 1850                                 power-domains = <&rpmhpd SC7280_CX>;
 1851                                 operating-points-v2 = <&qup_opp_table>;
 1852                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1853                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1854                                 interconnect-names = "qup-core", "qup-config";
 1855                                 status = "disabled";
 1856                         };
 1857 
 1858                         i2c15: i2c@a9c000 {
 1859                                 compatible = "qcom,geni-i2c";
 1860                                 reg = <0 0x00a9c000 0 0x4000>;
 1861                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 1862                                 clock-names = "se";
 1863                                 pinctrl-names = "default";
 1864                                 pinctrl-0 = <&qup_i2c15_data_clk>;
 1865                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
 1866                                 #address-cells = <1>;
 1867                                 #size-cells = <0>;
 1868                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1869                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
 1870                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
 1871                                 interconnect-names = "qup-core", "qup-config",
 1872                                                         "qup-memory";
 1873                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
 1874                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
 1875                                 dma-names = "tx", "rx";
 1876                                 status = "disabled";
 1877                         };
 1878 
 1879                         spi15: spi@a9c000 {
 1880                                 compatible = "qcom,geni-spi";
 1881                                 reg = <0 0x00a9c000 0 0x4000>;
 1882                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 1883                                 clock-names = "se";
 1884                                 pinctrl-names = "default";
 1885                                 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
 1886                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
 1887                                 #address-cells = <1>;
 1888                                 #size-cells = <0>;
 1889                                 power-domains = <&rpmhpd SC7280_CX>;
 1890                                 operating-points-v2 = <&qup_opp_table>;
 1891                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1892                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1893                                 interconnect-names = "qup-core", "qup-config";
 1894                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
 1895                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
 1896                                 dma-names = "tx", "rx";
 1897                                 status = "disabled";
 1898                         };
 1899 
 1900                         uart15: serial@a9c000 {
 1901                                 compatible = "qcom,geni-uart";
 1902                                 reg = <0 0x00a9c000 0 0x4000>;
 1903                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 1904                                 clock-names = "se";
 1905                                 pinctrl-names = "default";
 1906                                 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
 1907                                 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
 1908                                 power-domains = <&rpmhpd SC7280_CX>;
 1909                                 operating-points-v2 = <&qup_opp_table>;
 1910                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
 1911                                                 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
 1912                                 interconnect-names = "qup-core", "qup-config";
 1913                                 status = "disabled";
 1914                         };
 1915                 };
 1916 
 1917                 cnoc2: interconnect@1500000 {
 1918                         reg = <0 0x01500000 0 0x1000>;
 1919                         compatible = "qcom,sc7280-cnoc2";
 1920                         #interconnect-cells = <2>;
 1921                         qcom,bcm-voters = <&apps_bcm_voter>;
 1922                 };
 1923 
 1924                 cnoc3: interconnect@1502000 {
 1925                         reg = <0 0x01502000 0 0x1000>;
 1926                         compatible = "qcom,sc7280-cnoc3";
 1927                         #interconnect-cells = <2>;
 1928                         qcom,bcm-voters = <&apps_bcm_voter>;
 1929                 };
 1930 
 1931                 mc_virt: interconnect@1580000 {
 1932                         reg = <0 0x01580000 0 0x4>;
 1933                         compatible = "qcom,sc7280-mc-virt";
 1934                         #interconnect-cells = <2>;
 1935                         qcom,bcm-voters = <&apps_bcm_voter>;
 1936                 };
 1937 
 1938                 system_noc: interconnect@1680000 {
 1939                         reg = <0 0x01680000 0 0x15480>;
 1940                         compatible = "qcom,sc7280-system-noc";
 1941                         #interconnect-cells = <2>;
 1942                         qcom,bcm-voters = <&apps_bcm_voter>;
 1943                 };
 1944 
 1945                 aggre1_noc: interconnect@16e0000 {
 1946                         compatible = "qcom,sc7280-aggre1-noc";
 1947                         reg = <0 0x016e0000 0 0x1c080>;
 1948                         #interconnect-cells = <2>;
 1949                         qcom,bcm-voters = <&apps_bcm_voter>;
 1950                 };
 1951 
 1952                 aggre2_noc: interconnect@1700000 {
 1953                         reg = <0 0x01700000 0 0x2b080>;
 1954                         compatible = "qcom,sc7280-aggre2-noc";
 1955                         #interconnect-cells = <2>;
 1956                         qcom,bcm-voters = <&apps_bcm_voter>;
 1957                 };
 1958 
 1959                 mmss_noc: interconnect@1740000 {
 1960                         reg = <0 0x01740000 0 0x1e080>;
 1961                         compatible = "qcom,sc7280-mmss-noc";
 1962                         #interconnect-cells = <2>;
 1963                         qcom,bcm-voters = <&apps_bcm_voter>;
 1964                 };
 1965 
 1966                 wifi: wifi@17a10040 {
 1967                         compatible = "qcom,wcn6750-wifi";
 1968                         reg = <0 0x17a10040 0 0x0>;
 1969                         iommus = <&apps_smmu 0x1c00 0x1>;
 1970                         interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
 1971                                      <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
 1972                                      <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
 1973                                      <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
 1974                                      <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
 1975                                      <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
 1976                                      <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
 1977                                      <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
 1978                                      <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
 1979                                      <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
 1980                                      <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
 1981                                      <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
 1982                                      <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
 1983                                      <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
 1984                                      <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
 1985                                      <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
 1986                                      <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
 1987                                      <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
 1988                                      <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
 1989                                      <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
 1990                                      <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
 1991                                      <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
 1992                                      <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
 1993                                      <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
 1994                                      <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
 1995                                      <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
 1996                                      <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
 1997                                      <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
 1998                                      <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
 1999                                      <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
 2000                                      <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
 2001                                      <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
 2002                         qcom,rproc = <&remoteproc_wpss>;
 2003                         memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
 2004                         status = "disabled";
 2005                 };
 2006 
 2007                 pcie1: pci@1c08000 {
 2008                         compatible = "qcom,pcie-sc7280";
 2009                         reg = <0 0x01c08000 0 0x3000>,
 2010                               <0 0x40000000 0 0xf1d>,
 2011                               <0 0x40000f20 0 0xa8>,
 2012                               <0 0x40001000 0 0x1000>,
 2013                               <0 0x40100000 0 0x100000>;
 2014 
 2015                         reg-names = "parf", "dbi", "elbi", "atu", "config";
 2016                         device_type = "pci";
 2017                         linux,pci-domain = <1>;
 2018                         bus-range = <0x00 0xff>;
 2019                         num-lanes = <2>;
 2020 
 2021                         #address-cells = <3>;
 2022                         #size-cells = <2>;
 2023 
 2024                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
 2025                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
 2026 
 2027                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
 2028                         interrupt-names = "msi";
 2029                         #interrupt-cells = <1>;
 2030                         interrupt-map-mask = <0 0 0 0x7>;
 2031                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
 2032                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
 2033                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
 2034                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
 2035 
 2036                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 2037                                  <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
 2038                                  <&pcie1_lane>,
 2039                                  <&rpmhcc RPMH_CXO_CLK>,
 2040                                  <&gcc GCC_PCIE_1_AUX_CLK>,
 2041                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 2042                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 2043                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
 2044                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
 2045                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
 2046                                  <&gcc GCC_DDRSS_PCIE_SF_CLK>;
 2047 
 2048                         clock-names = "pipe",
 2049                                       "pipe_mux",
 2050                                       "phy_pipe",
 2051                                       "ref",
 2052                                       "aux",
 2053                                       "cfg",
 2054                                       "bus_master",
 2055                                       "bus_slave",
 2056                                       "slave_q2a",
 2057                                       "tbu",
 2058                                       "ddrss_sf_tbu";
 2059 
 2060                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
 2061                         assigned-clock-rates = <19200000>;
 2062 
 2063                         resets = <&gcc GCC_PCIE_1_BCR>;
 2064                         reset-names = "pci";
 2065 
 2066                         power-domains = <&gcc GCC_PCIE_1_GDSC>;
 2067 
 2068                         phys = <&pcie1_lane>;
 2069                         phy-names = "pciephy";
 2070 
 2071                         pinctrl-names = "default";
 2072                         pinctrl-0 = <&pcie1_clkreq_n>;
 2073 
 2074                         iommus = <&apps_smmu 0x1c80 0x1>;
 2075 
 2076                         iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
 2077                                     <0x100 &apps_smmu 0x1c81 0x1>;
 2078 
 2079                         status = "disabled";
 2080                 };
 2081 
 2082                 pcie1_phy: phy@1c0e000 {
 2083                         compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
 2084                         reg = <0 0x01c0e000 0 0x1c0>;
 2085                         #address-cells = <2>;
 2086                         #size-cells = <2>;
 2087                         ranges;
 2088                         clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
 2089                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 2090                                  <&gcc GCC_PCIE_CLKREF_EN>,
 2091                                  <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
 2092                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
 2093 
 2094                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 2095                         reset-names = "phy";
 2096 
 2097                         assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
 2098                         assigned-clock-rates = <100000000>;
 2099 
 2100                         status = "disabled";
 2101 
 2102                         pcie1_lane: phy@1c0e200 {
 2103                                 reg = <0 0x01c0e200 0 0x170>,
 2104                                       <0 0x01c0e400 0 0x200>,
 2105                                       <0 0x01c0ea00 0 0x1f0>,
 2106                                       <0 0x01c0e600 0 0x170>,
 2107                                       <0 0x01c0e800 0 0x200>,
 2108                                       <0 0x01c0ee00 0 0xf4>;
 2109                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 2110                                 clock-names = "pipe0";
 2111 
 2112                                 #phy-cells = <0>;
 2113                                 #clock-cells = <0>;
 2114                                 clock-output-names = "pcie_1_pipe_clk";
 2115                         };
 2116                 };
 2117 
 2118                 ipa: ipa@1e40000 {
 2119                         compatible = "qcom,sc7280-ipa";
 2120 
 2121                         iommus = <&apps_smmu 0x480 0x0>,
 2122                                  <&apps_smmu 0x482 0x0>;
 2123                         reg = <0 0x1e40000 0 0x8000>,
 2124                               <0 0x1e50000 0 0x4ad0>,
 2125                               <0 0x1e04000 0 0x23000>;
 2126                         reg-names = "ipa-reg",
 2127                                     "ipa-shared",
 2128                                     "gsi";
 2129 
 2130                         interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
 2131                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
 2132                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 2133                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
 2134                         interrupt-names = "ipa",
 2135                                           "gsi",
 2136                                           "ipa-clock-query",
 2137                                           "ipa-setup-ready";
 2138 
 2139                         clocks = <&rpmhcc RPMH_IPA_CLK>;
 2140                         clock-names = "core";
 2141 
 2142                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
 2143                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
 2144                         interconnect-names = "memory",
 2145                                              "config";
 2146 
 2147                         qcom,qmp = <&aoss_qmp>;
 2148 
 2149                         qcom,smem-states = <&ipa_smp2p_out 0>,
 2150                                            <&ipa_smp2p_out 1>;
 2151                         qcom,smem-state-names = "ipa-clock-enabled-valid",
 2152                                                 "ipa-clock-enabled";
 2153 
 2154                         status = "disabled";
 2155                 };
 2156 
 2157                 tcsr_mutex: hwlock@1f40000 {
 2158                         compatible = "qcom,tcsr-mutex", "syscon";
 2159                         reg = <0 0x01f40000 0 0x40000>;
 2160                         #hwlock-cells = <1>;
 2161                 };
 2162 
 2163                 tcsr: syscon@1fc0000 {
 2164                         compatible = "qcom,sc7280-tcsr", "syscon";
 2165                         reg = <0 0x01fc0000 0 0x30000>;
 2166                 };
 2167 
 2168                 lpasscc: lpasscc@3000000 {
 2169                         compatible = "qcom,sc7280-lpasscc";
 2170                         reg = <0 0x03000000 0 0x40>,
 2171                               <0 0x03c04000 0 0x4>,
 2172                               <0 0x03389000 0 0x24>;
 2173                         reg-names = "qdsp6ss", "top_cc", "cc";
 2174                         clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
 2175                         clock-names = "iface";
 2176                         #clock-cells = <1>;
 2177                 };
 2178 
 2179                 lpass_audiocc: clock-controller@3300000 {
 2180                         compatible = "qcom,sc7280-lpassaudiocc";
 2181                         reg = <0 0x03300000 0 0x30000>;
 2182                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 2183                                <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
 2184                         clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
 2185                         power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
 2186                         #clock-cells = <1>;
 2187                         #power-domain-cells = <1>;
 2188                 };
 2189 
 2190                 lpass_aon: clock-controller@3380000 {
 2191                         compatible = "qcom,sc7280-lpassaoncc";
 2192                         reg = <0 0x03380000 0 0x30000>;
 2193                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 2194                                <&rpmhcc RPMH_CXO_CLK_A>,
 2195                                <&lpasscore LPASS_CORE_CC_CORE_CLK>;
 2196                         clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
 2197                         #clock-cells = <1>;
 2198                         #power-domain-cells = <1>;
 2199                 };
 2200 
 2201                 lpasscore: clock-controller@3900000 {
 2202                         compatible = "qcom,sc7280-lpasscorecc";
 2203                         reg = <0 0x03900000 0 0x50000>;
 2204                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 2205                         clock-names = "bi_tcxo";
 2206                         power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
 2207                         #clock-cells = <1>;
 2208                         #power-domain-cells = <1>;
 2209                 };
 2210 
 2211                 lpass_hm: clock-controller@3c00000 {
 2212                         compatible = "qcom,sc7280-lpasshm";
 2213                         reg = <0 0x3c00000 0 0x28>;
 2214                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 2215                         clock-names = "bi_tcxo";
 2216                         #clock-cells = <1>;
 2217                         #power-domain-cells = <1>;
 2218                 };
 2219 
 2220                 lpass_ag_noc: interconnect@3c40000 {
 2221                         reg = <0 0x03c40000 0 0xf080>;
 2222                         compatible = "qcom,sc7280-lpass-ag-noc";
 2223                         #interconnect-cells = <2>;
 2224                         qcom,bcm-voters = <&apps_bcm_voter>;
 2225                 };
 2226 
 2227                 lpass_tlmm: pinctrl@33c0000 {
 2228                         compatible = "qcom,sc7280-lpass-lpi-pinctrl";
 2229                         reg = <0 0x033c0000 0x0 0x20000>,
 2230                                 <0 0x03550000 0x0 0x10000>;
 2231                         qcom,adsp-bypass-mode;
 2232                         gpio-controller;
 2233                         #gpio-cells = <2>;
 2234                         gpio-ranges = <&lpass_tlmm 0 0 15>;
 2235 
 2236                         #clock-cells = <1>;
 2237 
 2238                         lpass_dmic01_clk: dmic01-clk {
 2239                                 pins = "gpio6";
 2240                                 function = "dmic1_clk";
 2241                         };
 2242 
 2243                         lpass_dmic01_clk_sleep: dmic01-clk-sleep {
 2244                                 pins = "gpio6";
 2245                                 function = "dmic1_clk";
 2246                         };
 2247 
 2248                         lpass_dmic01_data: dmic01-data {
 2249                                 pins = "gpio7";
 2250                                 function = "dmic1_data";
 2251                         };
 2252 
 2253                         lpass_dmic01_data_sleep: dmic01-data-sleep {
 2254                                 pins = "gpio7";
 2255                                 function = "dmic1_data";
 2256                         };
 2257 
 2258                         lpass_dmic23_clk: dmic23-clk {
 2259                                 pins = "gpio8";
 2260                                 function = "dmic2_clk";
 2261                         };
 2262 
 2263                         lpass_dmic23_clk_sleep: dmic23-clk-sleep {
 2264                                 pins = "gpio8";
 2265                                 function = "dmic2_clk";
 2266                         };
 2267 
 2268                         lpass_dmic23_data: dmic23-data {
 2269                                 pins = "gpio9";
 2270                                 function = "dmic2_data";
 2271                         };
 2272 
 2273                         lpass_dmic23_data_sleep: dmic23-data-sleep {
 2274                                 pins = "gpio9";
 2275                                 function = "dmic2_data";
 2276                         };
 2277 
 2278                         lpass_rx_swr_clk: rx-swr-clk {
 2279                                 pins = "gpio3";
 2280                                 function = "swr_rx_clk";
 2281                         };
 2282 
 2283                         lpass_rx_swr_clk_sleep: rx-swr-clk-sleep {
 2284                                 pins = "gpio3";
 2285                                 function = "swr_rx_clk";
 2286                         };
 2287 
 2288                         lpass_rx_swr_data: rx-swr-data {
 2289                                 pins = "gpio4", "gpio5";
 2290                                 function = "swr_rx_data";
 2291                         };
 2292 
 2293                         lpass_rx_swr_data_sleep: rx-swr-data-sleep {
 2294                                 pins = "gpio4", "gpio5";
 2295                                 function = "swr_rx_data";
 2296                         };
 2297 
 2298                         lpass_tx_swr_clk: tx-swr-clk {
 2299                                 pins = "gpio0";
 2300                                 function = "swr_tx_clk";
 2301                         };
 2302 
 2303                         lpass_tx_swr_clk_sleep: tx-swr-clk-sleep {
 2304                                 pins = "gpio0";
 2305                                 function = "swr_tx_clk";
 2306                         };
 2307 
 2308                         lpass_tx_swr_data: tx-swr-data {
 2309                                 pins = "gpio1", "gpio2", "gpio14";
 2310                                 function = "swr_tx_data";
 2311                         };
 2312 
 2313                         lpass_tx_swr_data_sleep: tx-swr-data-sleep {
 2314                                 pins = "gpio1", "gpio2", "gpio14";
 2315                                 function = "swr_tx_data";
 2316                         };
 2317                 };
 2318 
 2319                 gpu: gpu@3d00000 {
 2320                         compatible = "qcom,adreno-635.0", "qcom,adreno";
 2321                         reg = <0 0x03d00000 0 0x40000>,
 2322                               <0 0x03d9e000 0 0x1000>,
 2323                               <0 0x03d61000 0 0x800>;
 2324                         reg-names = "kgsl_3d0_reg_memory",
 2325                                     "cx_mem",
 2326                                     "cx_dbgc";
 2327                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 2328                         iommus = <&adreno_smmu 0 0x401>;
 2329                         operating-points-v2 = <&gpu_opp_table>;
 2330                         qcom,gmu = <&gmu>;
 2331                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
 2332                         interconnect-names = "gfx-mem";
 2333                         #cooling-cells = <2>;
 2334 
 2335                         nvmem-cells = <&gpu_speed_bin>;
 2336                         nvmem-cell-names = "speed_bin";
 2337 
 2338                         gpu_opp_table: opp-table {
 2339                                 compatible = "operating-points-v2";
 2340 
 2341                                 opp-315000000 {
 2342                                         opp-hz = /bits/ 64 <315000000>;
 2343                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 2344                                         opp-peak-kBps = <1804000>;
 2345                                         opp-supported-hw = <0x03>;
 2346                                 };
 2347 
 2348                                 opp-450000000 {
 2349                                         opp-hz = /bits/ 64 <450000000>;
 2350                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 2351                                         opp-peak-kBps = <4068000>;
 2352                                         opp-supported-hw = <0x03>;
 2353                                 };
 2354 
 2355                                 opp-550000000 {
 2356                                         opp-hz = /bits/ 64 <550000000>;
 2357                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 2358                                         opp-peak-kBps = <6832000>;
 2359                                         opp-supported-hw = <0x03>;
 2360                                 };
 2361 
 2362                                 opp-608000000 {
 2363                                         opp-hz = /bits/ 64 <608000000>;
 2364                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 2365                                         opp-peak-kBps = <8368000>;
 2366                                         opp-supported-hw = <0x02>;
 2367                                 };
 2368 
 2369                                 opp-700000000 {
 2370                                         opp-hz = /bits/ 64 <700000000>;
 2371                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 2372                                         opp-peak-kBps = <8532000>;
 2373                                         opp-supported-hw = <0x02>;
 2374                                 };
 2375 
 2376                                 opp-812000000 {
 2377                                         opp-hz = /bits/ 64 <812000000>;
 2378                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 2379                                         opp-peak-kBps = <8532000>;
 2380                                         opp-supported-hw = <0x02>;
 2381                                 };
 2382 
 2383                                 opp-840000000 {
 2384                                         opp-hz = /bits/ 64 <840000000>;
 2385                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 2386                                         opp-peak-kBps = <8532000>;
 2387                                         opp-supported-hw = <0x02>;
 2388                                 };
 2389 
 2390                                 opp-900000000 {
 2391                                         opp-hz = /bits/ 64 <900000000>;
 2392                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 2393                                         opp-peak-kBps = <8532000>;
 2394                                         opp-supported-hw = <0x02>;
 2395                                 };
 2396                         };
 2397                 };
 2398 
 2399                 gmu: gmu@3d6a000 {
 2400                         compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
 2401                         reg = <0 0x03d6a000 0 0x34000>,
 2402                                 <0 0x3de0000 0 0x10000>,
 2403                                 <0 0x0b290000 0 0x10000>;
 2404                         reg-names = "gmu", "rscc", "gmu_pdc";
 2405                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
 2406                                         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
 2407                         interrupt-names = "hfi", "gmu";
 2408                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
 2409                                  <&gpucc GPU_CC_CXO_CLK>,
 2410                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
 2411                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 2412                                  <&gpucc GPU_CC_AHB_CLK>,
 2413                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
 2414                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
 2415                         clock-names = "gmu",
 2416                                       "cxo",
 2417                                       "axi",
 2418                                       "memnoc",
 2419                                       "ahb",
 2420                                       "hub",
 2421                                       "smmu_vote";
 2422                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
 2423                                         <&gpucc GPU_CC_GX_GDSC>;
 2424                         power-domain-names = "cx",
 2425                                              "gx";
 2426                         iommus = <&adreno_smmu 5 0x400>;
 2427                         operating-points-v2 = <&gmu_opp_table>;
 2428 
 2429                         gmu_opp_table: opp-table {
 2430                                 compatible = "operating-points-v2";
 2431 
 2432                                 opp-200000000 {
 2433                                         opp-hz = /bits/ 64 <200000000>;
 2434                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 2435                                 };
 2436                         };
 2437                 };
 2438 
 2439                 gpucc: clock-controller@3d90000 {
 2440                         compatible = "qcom,sc7280-gpucc";
 2441                         reg = <0 0x03d90000 0 0x9000>;
 2442                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 2443                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
 2444                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
 2445                         clock-names = "bi_tcxo",
 2446                                       "gcc_gpu_gpll0_clk_src",
 2447                                       "gcc_gpu_gpll0_div_clk_src";
 2448                         #clock-cells = <1>;
 2449                         #reset-cells = <1>;
 2450                         #power-domain-cells = <1>;
 2451                 };
 2452 
 2453                 adreno_smmu: iommu@3da0000 {
 2454                         compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
 2455                         reg = <0 0x03da0000 0 0x20000>;
 2456                         #iommu-cells = <2>;
 2457                         #global-interrupts = <2>;
 2458                         interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
 2459                                         <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
 2460                                         <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
 2461                                         <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
 2462                                         <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
 2463                                         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
 2464                                         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
 2465                                         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
 2466                                         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
 2467                                         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
 2468                                         <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
 2469                                         <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
 2470 
 2471                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 2472                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
 2473                                  <&gpucc GPU_CC_AHB_CLK>,
 2474                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
 2475                                  <&gpucc GPU_CC_CX_GMU_CLK>,
 2476                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
 2477                                  <&gpucc GPU_CC_HUB_AON_CLK>;
 2478                         clock-names = "gcc_gpu_memnoc_gfx_clk",
 2479                                         "gcc_gpu_snoc_dvm_gfx_clk",
 2480                                         "gpu_cc_ahb_clk",
 2481                                         "gpu_cc_hlos1_vote_gpu_smmu_clk",
 2482                                         "gpu_cc_cx_gmu_clk",
 2483                                         "gpu_cc_hub_cx_int_clk",
 2484                                         "gpu_cc_hub_aon_clk";
 2485 
 2486                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
 2487                 };
 2488 
 2489                 remoteproc_mpss: remoteproc@4080000 {
 2490                         compatible = "qcom,sc7280-mpss-pas";
 2491                         reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
 2492                         reg-names = "qdsp6", "rmb";
 2493 
 2494                         interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
 2495                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 2496                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 2497                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 2498                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
 2499                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
 2500                         interrupt-names = "wdog", "fatal", "ready", "handover",
 2501                                           "stop-ack", "shutdown-ack";
 2502 
 2503                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 2504                                  <&gcc GCC_MSS_OFFLINE_AXI_CLK>,
 2505                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
 2506                                  <&rpmhcc RPMH_PKA_CLK>,
 2507                                  <&rpmhcc RPMH_CXO_CLK>;
 2508                         clock-names = "iface", "offline", "snoc_axi", "pka", "xo";
 2509 
 2510                         power-domains = <&rpmhpd SC7280_CX>,
 2511                                         <&rpmhpd SC7280_MSS>;
 2512                         power-domain-names = "cx", "mss";
 2513 
 2514                         memory-region = <&mpss_mem>;
 2515 
 2516                         qcom,qmp = <&aoss_qmp>;
 2517 
 2518                         qcom,smem-states = <&modem_smp2p_out 0>;
 2519                         qcom,smem-state-names = "stop";
 2520 
 2521                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
 2522                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
 2523                         reset-names = "mss_restart", "pdc_reset";
 2524 
 2525                         qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
 2526                         qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>;
 2527                         qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>;
 2528 
 2529                         status = "disabled";
 2530 
 2531                         glink-edge {
 2532                                 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 2533                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
 2534                                                              IRQ_TYPE_EDGE_RISING>;
 2535                                 mboxes = <&ipcc IPCC_CLIENT_MPSS
 2536                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
 2537                                 label = "modem";
 2538                                 qcom,remote-pid = <1>;
 2539                         };
 2540                 };
 2541 
 2542                 stm@6002000 {
 2543                         compatible = "arm,coresight-stm", "arm,primecell";
 2544                         reg = <0 0x06002000 0 0x1000>,
 2545                               <0 0x16280000 0 0x180000>;
 2546                         reg-names = "stm-base", "stm-stimulus-base";
 2547 
 2548                         clocks = <&aoss_qmp>;
 2549                         clock-names = "apb_pclk";
 2550 
 2551                         out-ports {
 2552                                 port {
 2553                                         stm_out: endpoint {
 2554                                                 remote-endpoint = <&funnel0_in7>;
 2555                                         };
 2556                                 };
 2557                         };
 2558                 };
 2559 
 2560                 funnel@6041000 {
 2561                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2562                         reg = <0 0x06041000 0 0x1000>;
 2563 
 2564                         clocks = <&aoss_qmp>;
 2565                         clock-names = "apb_pclk";
 2566 
 2567                         out-ports {
 2568                                 port {
 2569                                         funnel0_out: endpoint {
 2570                                                 remote-endpoint = <&merge_funnel_in0>;
 2571                                         };
 2572                                 };
 2573                         };
 2574 
 2575                         in-ports {
 2576                                 #address-cells = <1>;
 2577                                 #size-cells = <0>;
 2578 
 2579                                 port@7 {
 2580                                         reg = <7>;
 2581                                         funnel0_in7: endpoint {
 2582                                                 remote-endpoint = <&stm_out>;
 2583                                         };
 2584                                 };
 2585                         };
 2586                 };
 2587 
 2588                 funnel@6042000 {
 2589                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2590                         reg = <0 0x06042000 0 0x1000>;
 2591 
 2592                         clocks = <&aoss_qmp>;
 2593                         clock-names = "apb_pclk";
 2594 
 2595                         out-ports {
 2596                                 port {
 2597                                         funnel1_out: endpoint {
 2598                                                 remote-endpoint = <&merge_funnel_in1>;
 2599                                         };
 2600                                 };
 2601                         };
 2602 
 2603                         in-ports {
 2604                                 #address-cells = <1>;
 2605                                 #size-cells = <0>;
 2606 
 2607                                 port@4 {
 2608                                         reg = <4>;
 2609                                         funnel1_in4: endpoint {
 2610                                                 remote-endpoint = <&apss_merge_funnel_out>;
 2611                                         };
 2612                                 };
 2613                         };
 2614                 };
 2615 
 2616                 funnel@6045000 {
 2617                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2618                         reg = <0 0x06045000 0 0x1000>;
 2619 
 2620                         clocks = <&aoss_qmp>;
 2621                         clock-names = "apb_pclk";
 2622 
 2623                         out-ports {
 2624                                 port {
 2625                                         merge_funnel_out: endpoint {
 2626                                                 remote-endpoint = <&swao_funnel_in>;
 2627                                         };
 2628                                 };
 2629                         };
 2630 
 2631                         in-ports {
 2632                                 #address-cells = <1>;
 2633                                 #size-cells = <0>;
 2634 
 2635                                 port@0 {
 2636                                         reg = <0>;
 2637                                         merge_funnel_in0: endpoint {
 2638                                                 remote-endpoint = <&funnel0_out>;
 2639                                         };
 2640                                 };
 2641 
 2642                                 port@1 {
 2643                                         reg = <1>;
 2644                                         merge_funnel_in1: endpoint {
 2645                                                 remote-endpoint = <&funnel1_out>;
 2646                                         };
 2647                                 };
 2648                         };
 2649                 };
 2650 
 2651                 replicator@6046000 {
 2652                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 2653                         reg = <0 0x06046000 0 0x1000>;
 2654 
 2655                         clocks = <&aoss_qmp>;
 2656                         clock-names = "apb_pclk";
 2657 
 2658                         out-ports {
 2659                                 port {
 2660                                         replicator_out: endpoint {
 2661                                                 remote-endpoint = <&etr_in>;
 2662                                         };
 2663                                 };
 2664                         };
 2665 
 2666                         in-ports {
 2667                                 port {
 2668                                         replicator_in: endpoint {
 2669                                                 remote-endpoint = <&swao_replicator_out>;
 2670                                         };
 2671                                 };
 2672                         };
 2673                 };
 2674 
 2675                 etr@6048000 {
 2676                         compatible = "arm,coresight-tmc", "arm,primecell";
 2677                         reg = <0 0x06048000 0 0x1000>;
 2678                         iommus = <&apps_smmu 0x04c0 0>;
 2679 
 2680                         clocks = <&aoss_qmp>;
 2681                         clock-names = "apb_pclk";
 2682                         arm,scatter-gather;
 2683 
 2684                         in-ports {
 2685                                 port {
 2686                                         etr_in: endpoint {
 2687                                                 remote-endpoint = <&replicator_out>;
 2688                                         };
 2689                                 };
 2690                         };
 2691                 };
 2692 
 2693                 funnel@6b04000 {
 2694                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2695                         reg = <0 0x06b04000 0 0x1000>;
 2696 
 2697                         clocks = <&aoss_qmp>;
 2698                         clock-names = "apb_pclk";
 2699 
 2700                         out-ports {
 2701                                 port {
 2702                                         swao_funnel_out: endpoint {
 2703                                                 remote-endpoint = <&etf_in>;
 2704                                         };
 2705                                 };
 2706                         };
 2707 
 2708                         in-ports {
 2709                                 #address-cells = <1>;
 2710                                 #size-cells = <0>;
 2711 
 2712                                 port@7 {
 2713                                         reg = <7>;
 2714                                         swao_funnel_in: endpoint {
 2715                                                 remote-endpoint = <&merge_funnel_out>;
 2716                                         };
 2717                                 };
 2718                         };
 2719                 };
 2720 
 2721                 etf@6b05000 {
 2722                         compatible = "arm,coresight-tmc", "arm,primecell";
 2723                         reg = <0 0x06b05000 0 0x1000>;
 2724 
 2725                         clocks = <&aoss_qmp>;
 2726                         clock-names = "apb_pclk";
 2727 
 2728                         out-ports {
 2729                                 port {
 2730                                         etf_out: endpoint {
 2731                                                 remote-endpoint = <&swao_replicator_in>;
 2732                                         };
 2733                                 };
 2734                         };
 2735 
 2736                         in-ports {
 2737                                 port {
 2738                                         etf_in: endpoint {
 2739                                                 remote-endpoint = <&swao_funnel_out>;
 2740                                         };
 2741                                 };
 2742                         };
 2743                 };
 2744 
 2745                 replicator@6b06000 {
 2746                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 2747                         reg = <0 0x06b06000 0 0x1000>;
 2748 
 2749                         clocks = <&aoss_qmp>;
 2750                         clock-names = "apb_pclk";
 2751                         qcom,replicator-loses-context;
 2752 
 2753                         out-ports {
 2754                                 port {
 2755                                         swao_replicator_out: endpoint {
 2756                                                 remote-endpoint = <&replicator_in>;
 2757                                         };
 2758                                 };
 2759                         };
 2760 
 2761                         in-ports {
 2762                                 port {
 2763                                         swao_replicator_in: endpoint {
 2764                                                 remote-endpoint = <&etf_out>;
 2765                                         };
 2766                                 };
 2767                         };
 2768                 };
 2769 
 2770                 etm@7040000 {
 2771                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2772                         reg = <0 0x07040000 0 0x1000>;
 2773 
 2774                         cpu = <&CPU0>;
 2775 
 2776                         clocks = <&aoss_qmp>;
 2777                         clock-names = "apb_pclk";
 2778                         arm,coresight-loses-context-with-cpu;
 2779                         qcom,skip-power-up;
 2780 
 2781                         out-ports {
 2782                                 port {
 2783                                         etm0_out: endpoint {
 2784                                                 remote-endpoint = <&apss_funnel_in0>;
 2785                                         };
 2786                                 };
 2787                         };
 2788                 };
 2789 
 2790                 etm@7140000 {
 2791                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2792                         reg = <0 0x07140000 0 0x1000>;
 2793 
 2794                         cpu = <&CPU1>;
 2795 
 2796                         clocks = <&aoss_qmp>;
 2797                         clock-names = "apb_pclk";
 2798                         arm,coresight-loses-context-with-cpu;
 2799                         qcom,skip-power-up;
 2800 
 2801                         out-ports {
 2802                                 port {
 2803                                         etm1_out: endpoint {
 2804                                                 remote-endpoint = <&apss_funnel_in1>;
 2805                                         };
 2806                                 };
 2807                         };
 2808                 };
 2809 
 2810                 etm@7240000 {
 2811                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2812                         reg = <0 0x07240000 0 0x1000>;
 2813 
 2814                         cpu = <&CPU2>;
 2815 
 2816                         clocks = <&aoss_qmp>;
 2817                         clock-names = "apb_pclk";
 2818                         arm,coresight-loses-context-with-cpu;
 2819                         qcom,skip-power-up;
 2820 
 2821                         out-ports {
 2822                                 port {
 2823                                         etm2_out: endpoint {
 2824                                                 remote-endpoint = <&apss_funnel_in2>;
 2825                                         };
 2826                                 };
 2827                         };
 2828                 };
 2829 
 2830                 etm@7340000 {
 2831                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2832                         reg = <0 0x07340000 0 0x1000>;
 2833 
 2834                         cpu = <&CPU3>;
 2835 
 2836                         clocks = <&aoss_qmp>;
 2837                         clock-names = "apb_pclk";
 2838                         arm,coresight-loses-context-with-cpu;
 2839                         qcom,skip-power-up;
 2840 
 2841                         out-ports {
 2842                                 port {
 2843                                         etm3_out: endpoint {
 2844                                                 remote-endpoint = <&apss_funnel_in3>;
 2845                                         };
 2846                                 };
 2847                         };
 2848                 };
 2849 
 2850                 etm@7440000 {
 2851                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2852                         reg = <0 0x07440000 0 0x1000>;
 2853 
 2854                         cpu = <&CPU4>;
 2855 
 2856                         clocks = <&aoss_qmp>;
 2857                         clock-names = "apb_pclk";
 2858                         arm,coresight-loses-context-with-cpu;
 2859                         qcom,skip-power-up;
 2860 
 2861                         out-ports {
 2862                                 port {
 2863                                         etm4_out: endpoint {
 2864                                                 remote-endpoint = <&apss_funnel_in4>;
 2865                                         };
 2866                                 };
 2867                         };
 2868                 };
 2869 
 2870                 etm@7540000 {
 2871                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2872                         reg = <0 0x07540000 0 0x1000>;
 2873 
 2874                         cpu = <&CPU5>;
 2875 
 2876                         clocks = <&aoss_qmp>;
 2877                         clock-names = "apb_pclk";
 2878                         arm,coresight-loses-context-with-cpu;
 2879                         qcom,skip-power-up;
 2880 
 2881                         out-ports {
 2882                                 port {
 2883                                         etm5_out: endpoint {
 2884                                                 remote-endpoint = <&apss_funnel_in5>;
 2885                                         };
 2886                                 };
 2887                         };
 2888                 };
 2889 
 2890                 etm@7640000 {
 2891                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2892                         reg = <0 0x07640000 0 0x1000>;
 2893 
 2894                         cpu = <&CPU6>;
 2895 
 2896                         clocks = <&aoss_qmp>;
 2897                         clock-names = "apb_pclk";
 2898                         arm,coresight-loses-context-with-cpu;
 2899                         qcom,skip-power-up;
 2900 
 2901                         out-ports {
 2902                                 port {
 2903                                         etm6_out: endpoint {
 2904                                                 remote-endpoint = <&apss_funnel_in6>;
 2905                                         };
 2906                                 };
 2907                         };
 2908                 };
 2909 
 2910                 etm@7740000 {
 2911                         compatible = "arm,coresight-etm4x", "arm,primecell";
 2912                         reg = <0 0x07740000 0 0x1000>;
 2913 
 2914                         cpu = <&CPU7>;
 2915 
 2916                         clocks = <&aoss_qmp>;
 2917                         clock-names = "apb_pclk";
 2918                         arm,coresight-loses-context-with-cpu;
 2919                         qcom,skip-power-up;
 2920 
 2921                         out-ports {
 2922                                 port {
 2923                                         etm7_out: endpoint {
 2924                                                 remote-endpoint = <&apss_funnel_in7>;
 2925                                         };
 2926                                 };
 2927                         };
 2928                 };
 2929 
 2930                 funnel@7800000 { /* APSS Funnel */
 2931                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 2932                         reg = <0 0x07800000 0 0x1000>;
 2933 
 2934                         clocks = <&aoss_qmp>;
 2935                         clock-names = "apb_pclk";
 2936 
 2937                         out-ports {
 2938                                 port {
 2939                                         apss_funnel_out: endpoint {
 2940                                                 remote-endpoint = <&apss_merge_funnel_in>;
 2941                                         };
 2942                                 };
 2943                         };
 2944 
 2945                         in-ports {
 2946                                 #address-cells = <1>;
 2947                                 #size-cells = <0>;
 2948 
 2949                                 port@0 {
 2950                                         reg = <0>;
 2951                                         apss_funnel_in0: endpoint {
 2952                                                 remote-endpoint = <&etm0_out>;
 2953                                         };
 2954                                 };
 2955 
 2956                                 port@1 {
 2957                                         reg = <1>;
 2958                                         apss_funnel_in1: endpoint {
 2959                                                 remote-endpoint = <&etm1_out>;
 2960                                         };
 2961                                 };
 2962 
 2963                                 port@2 {
 2964                                         reg = <2>;
 2965                                         apss_funnel_in2: endpoint {
 2966                                                 remote-endpoint = <&etm2_out>;
 2967                                         };
 2968                                 };
 2969 
 2970                                 port@3 {
 2971                                         reg = <3>;
 2972                                         apss_funnel_in3: endpoint {
 2973                                                 remote-endpoint = <&etm3_out>;
 2974                                         };
 2975                                 };
 2976 
 2977                                 port@4 {
 2978                                         reg = <4>;
 2979                                         apss_funnel_in4: endpoint {
 2980                                                 remote-endpoint = <&etm4_out>;
 2981                                         };
 2982                                 };
 2983 
 2984                                 port@5 {
 2985                                         reg = <5>;
 2986                                         apss_funnel_in5: endpoint {
 2987                                                 remote-endpoint = <&etm5_out>;
 2988                                         };
 2989                                 };
 2990 
 2991                                 port@6 {
 2992                                         reg = <6>;
 2993                                         apss_funnel_in6: endpoint {
 2994                                                 remote-endpoint = <&etm6_out>;
 2995                                         };
 2996                                 };
 2997 
 2998                                 port@7 {
 2999                                         reg = <7>;
 3000                                         apss_funnel_in7: endpoint {
 3001                                                 remote-endpoint = <&etm7_out>;
 3002                                         };
 3003                                 };
 3004                         };
 3005                 };
 3006 
 3007                 funnel@7810000 {
 3008                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 3009                         reg = <0 0x07810000 0 0x1000>;
 3010 
 3011                         clocks = <&aoss_qmp>;
 3012                         clock-names = "apb_pclk";
 3013 
 3014                         out-ports {
 3015                                 port {
 3016                                         apss_merge_funnel_out: endpoint {
 3017                                                 remote-endpoint = <&funnel1_in4>;
 3018                                         };
 3019                                 };
 3020                         };
 3021 
 3022                         in-ports {
 3023                                 port {
 3024                                         apss_merge_funnel_in: endpoint {
 3025                                                 remote-endpoint = <&apss_funnel_out>;
 3026                                         };
 3027                                 };
 3028                         };
 3029                 };
 3030 
 3031                 sdhc_2: mmc@8804000 {
 3032                         compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
 3033                         pinctrl-names = "default", "sleep";
 3034                         pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
 3035                         pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
 3036                         status = "disabled";
 3037 
 3038                         reg = <0 0x08804000 0 0x1000>;
 3039 
 3040                         iommus = <&apps_smmu 0x100 0x0>;
 3041                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 3042                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 3043                         interrupt-names = "hc_irq", "pwr_irq";
 3044 
 3045                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 3046                                  <&gcc GCC_SDCC2_APPS_CLK>,
 3047                                  <&rpmhcc RPMH_CXO_CLK>;
 3048                         clock-names = "iface", "core", "xo";
 3049                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
 3050                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
 3051                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 3052                         power-domains = <&rpmhpd SC7280_CX>;
 3053                         operating-points-v2 = <&sdhc2_opp_table>;
 3054 
 3055                         bus-width = <4>;
 3056 
 3057                         qcom,dll-config = <0x0007642c>;
 3058 
 3059                         resets = <&gcc GCC_SDCC2_BCR>;
 3060 
 3061                         sdhc2_opp_table: opp-table {
 3062                                 compatible = "operating-points-v2";
 3063 
 3064                                 opp-100000000 {
 3065                                         opp-hz = /bits/ 64 <100000000>;
 3066                                         required-opps = <&rpmhpd_opp_low_svs>;
 3067                                         opp-peak-kBps = <1800000 400000>;
 3068                                         opp-avg-kBps = <100000 0>;
 3069                                 };
 3070 
 3071                                 opp-202000000 {
 3072                                         opp-hz = /bits/ 64 <202000000>;
 3073                                         required-opps = <&rpmhpd_opp_nom>;
 3074                                         opp-peak-kBps = <5400000 1600000>;
 3075                                         opp-avg-kBps = <200000 0>;
 3076                                 };
 3077                         };
 3078 
 3079                 };
 3080 
 3081                 usb_1_hsphy: phy@88e3000 {
 3082                         compatible = "qcom,sc7280-usb-hs-phy",
 3083                                      "qcom,usb-snps-hs-7nm-phy";
 3084                         reg = <0 0x088e3000 0 0x400>;
 3085                         status = "disabled";
 3086                         #phy-cells = <0>;
 3087 
 3088                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 3089                         clock-names = "ref";
 3090 
 3091                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 3092                 };
 3093 
 3094                 usb_2_hsphy: phy@88e4000 {
 3095                         compatible = "qcom,sc7280-usb-hs-phy",
 3096                                      "qcom,usb-snps-hs-7nm-phy";
 3097                         reg = <0 0x088e4000 0 0x400>;
 3098                         status = "disabled";
 3099                         #phy-cells = <0>;
 3100 
 3101                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 3102                         clock-names = "ref";
 3103 
 3104                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 3105                 };
 3106 
 3107                 usb_1_qmpphy: phy-wrapper@88e9000 {
 3108                         compatible = "qcom,sc7280-qmp-usb3-dp-phy",
 3109                                      "qcom,sm8250-qmp-usb3-dp-phy";
 3110                         reg = <0 0x088e9000 0 0x200>,
 3111                               <0 0x088e8000 0 0x40>,
 3112                               <0 0x088ea000 0 0x200>;
 3113                         status = "disabled";
 3114                         #address-cells = <2>;
 3115                         #size-cells = <2>;
 3116                         ranges;
 3117 
 3118                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 3119                                  <&rpmhcc RPMH_CXO_CLK>,
 3120                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 3121                         clock-names = "aux", "ref_clk_src", "com_aux";
 3122 
 3123                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
 3124                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
 3125                         reset-names = "phy", "common";
 3126 
 3127                         usb_1_ssphy: usb3-phy@88e9200 {
 3128                                 reg = <0 0x088e9200 0 0x200>,
 3129                                       <0 0x088e9400 0 0x200>,
 3130                                       <0 0x088e9c00 0 0x400>,
 3131                                       <0 0x088e9600 0 0x200>,
 3132                                       <0 0x088e9800 0 0x200>,
 3133                                       <0 0x088e9a00 0 0x100>;
 3134                                 #clock-cells = <0>;
 3135                                 #phy-cells = <0>;
 3136                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 3137                                 clock-names = "pipe0";
 3138                                 clock-output-names = "usb3_phy_pipe_clk_src";
 3139                         };
 3140 
 3141                         dp_phy: dp-phy@88ea200 {
 3142                                 reg = <0 0x088ea200 0 0x200>,
 3143                                       <0 0x088ea400 0 0x200>,
 3144                                       <0 0x088eaa00 0 0x200>,
 3145                                       <0 0x088ea600 0 0x200>,
 3146                                       <0 0x088ea800 0 0x200>;
 3147                                 #phy-cells = <0>;
 3148                                 #clock-cells = <1>;
 3149                         };
 3150                 };
 3151 
 3152                 usb_2: usb@8cf8800 {
 3153                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
 3154                         reg = <0 0x08cf8800 0 0x400>;
 3155                         status = "disabled";
 3156                         #address-cells = <2>;
 3157                         #size-cells = <2>;
 3158                         ranges;
 3159                         dma-ranges;
 3160 
 3161                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
 3162                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
 3163                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
 3164                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
 3165                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
 3166                         clock-names = "cfg_noc",
 3167                                       "core",
 3168                                       "iface",
 3169                                       "sleep",
 3170                                       "mock_utmi";
 3171 
 3172                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
 3173                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
 3174                         assigned-clock-rates = <19200000>, <200000000>;
 3175 
 3176                         interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
 3177                                               <&pdc 12 IRQ_TYPE_EDGE_RISING>,
 3178                                               <&pdc 13 IRQ_TYPE_EDGE_RISING>;
 3179                         interrupt-names = "hs_phy_irq",
 3180                                           "dp_hs_phy_irq",
 3181                                           "dm_hs_phy_irq";
 3182 
 3183                         power-domains = <&gcc GCC_USB30_SEC_GDSC>;
 3184 
 3185                         resets = <&gcc GCC_USB30_SEC_BCR>;
 3186 
 3187                         interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
 3188                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
 3189                         interconnect-names = "usb-ddr", "apps-usb";
 3190 
 3191                         usb_2_dwc3: usb@8c00000 {
 3192                                 compatible = "snps,dwc3";
 3193                                 reg = <0 0x08c00000 0 0xe000>;
 3194                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 3195                                 iommus = <&apps_smmu 0xa0 0x0>;
 3196                                 snps,dis_u2_susphy_quirk;
 3197                                 snps,dis_enblslpm_quirk;
 3198                                 phys = <&usb_2_hsphy>;
 3199                                 phy-names = "usb2-phy";
 3200                                 maximum-speed = "high-speed";
 3201                                 usb-role-switch;
 3202                                 port {
 3203                                         usb2_role_switch: endpoint {
 3204                                                 remote-endpoint = <&eud_ep>;
 3205                                         };
 3206                                 };
 3207                         };
 3208                 };
 3209 
 3210                 qspi: spi@88dc000 {
 3211                         compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
 3212                         reg = <0 0x088dc000 0 0x1000>;
 3213                         #address-cells = <1>;
 3214                         #size-cells = <0>;
 3215                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 3216                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
 3217                                  <&gcc GCC_QSPI_CORE_CLK>;
 3218                         clock-names = "iface", "core";
 3219                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
 3220                                         &cnoc2 SLAVE_QSPI_0 0>;
 3221                         interconnect-names = "qspi-config";
 3222                         power-domains = <&rpmhpd SC7280_CX>;
 3223                         operating-points-v2 = <&qspi_opp_table>;
 3224                         status = "disabled";
 3225                 };
 3226 
 3227                 remoteproc_wpss: remoteproc@8a00000 {
 3228                         compatible = "qcom,sc7280-wpss-pil";
 3229                         reg = <0 0x08a00000 0 0x10000>;
 3230 
 3231                         interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
 3232                                               <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 3233                                               <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 3234                                               <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 3235                                               <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
 3236                                               <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
 3237                         interrupt-names = "wdog", "fatal", "ready", "handover",
 3238                                           "stop-ack", "shutdown-ack";
 3239 
 3240                         clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
 3241                                  <&gcc GCC_WPSS_AHB_CLK>,
 3242                                  <&gcc GCC_WPSS_RSCP_CLK>,
 3243                                  <&rpmhcc RPMH_CXO_CLK>;
 3244                         clock-names = "ahb_bdg", "ahb",
 3245                                       "rscp", "xo";
 3246 
 3247                         power-domains = <&rpmhpd SC7280_CX>,
 3248                                         <&rpmhpd SC7280_MX>;
 3249                         power-domain-names = "cx", "mx";
 3250 
 3251                         memory-region = <&wpss_mem>;
 3252 
 3253                         qcom,qmp = <&aoss_qmp>;
 3254 
 3255                         qcom,smem-states = <&wpss_smp2p_out 0>;
 3256                         qcom,smem-state-names = "stop";
 3257 
 3258                         resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
 3259                                  <&pdc_reset PDC_WPSS_SYNC_RESET>;
 3260                         reset-names = "restart", "pdc_sync";
 3261 
 3262                         qcom,halt-regs = <&tcsr_mutex 0x37000>;
 3263 
 3264                         status = "disabled";
 3265 
 3266                         glink-edge {
 3267                                 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
 3268                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
 3269                                                              IRQ_TYPE_EDGE_RISING>;
 3270                                 mboxes = <&ipcc IPCC_CLIENT_WPSS
 3271                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
 3272 
 3273                                 label = "wpss";
 3274                                 qcom,remote-pid = <13>;
 3275                         };
 3276                 };
 3277 
 3278                 dc_noc: interconnect@90e0000 {
 3279                         reg = <0 0x090e0000 0 0x5080>;
 3280                         compatible = "qcom,sc7280-dc-noc";
 3281                         #interconnect-cells = <2>;
 3282                         qcom,bcm-voters = <&apps_bcm_voter>;
 3283                 };
 3284 
 3285                 gem_noc: interconnect@9100000 {
 3286                         reg = <0 0x9100000 0 0xe2200>;
 3287                         compatible = "qcom,sc7280-gem-noc";
 3288                         #interconnect-cells = <2>;
 3289                         qcom,bcm-voters = <&apps_bcm_voter>;
 3290                 };
 3291 
 3292                 system-cache-controller@9200000 {
 3293                         compatible = "qcom,sc7280-llcc";
 3294                         reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
 3295                         reg-names = "llcc_base", "llcc_broadcast_base";
 3296                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 3297                 };
 3298 
 3299                 eud: eud@88e0000 {
 3300                         compatible = "qcom,sc7280-eud","qcom,eud";
 3301                         reg = <0 0x88e0000 0 0x2000>,
 3302                               <0 0x88e2000 0 0x1000>;
 3303                         interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
 3304                         ports {
 3305                                 port@0 {
 3306                                         eud_ep: endpoint {
 3307                                                 remote-endpoint = <&usb2_role_switch>;
 3308                                         };
 3309                                 };
 3310                                 port@1 {
 3311                                         eud_con: endpoint {
 3312                                                 remote-endpoint = <&con_eud>;
 3313                                         };
 3314                                 };
 3315                         };
 3316                 };
 3317 
 3318                 eud_typec: connector {
 3319                         compatible = "usb-c-connector";
 3320                         ports {
 3321                                 port@0 {
 3322                                         con_eud: endpoint {
 3323                                                 remote-endpoint = <&eud_con>;
 3324                                         };
 3325                                 };
 3326                         };
 3327                 };
 3328 
 3329                 nsp_noc: interconnect@a0c0000 {
 3330                         reg = <0 0x0a0c0000 0 0x10000>;
 3331                         compatible = "qcom,sc7280-nsp-noc";
 3332                         #interconnect-cells = <2>;
 3333                         qcom,bcm-voters = <&apps_bcm_voter>;
 3334                 };
 3335 
 3336                 usb_1: usb@a6f8800 {
 3337                         compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
 3338                         reg = <0 0x0a6f8800 0 0x400>;
 3339                         status = "disabled";
 3340                         #address-cells = <2>;
 3341                         #size-cells = <2>;
 3342                         ranges;
 3343                         dma-ranges;
 3344 
 3345                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
 3346                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 3347                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
 3348                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
 3349                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
 3350                         clock-names = "cfg_noc",
 3351                                       "core",
 3352                                       "iface",
 3353                                       "sleep",
 3354                                       "mock_utmi";
 3355 
 3356                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 3357                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 3358                         assigned-clock-rates = <19200000>, <200000000>;
 3359 
 3360                         interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 3361                                               <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
 3362                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
 3363                                               <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
 3364                         interrupt-names = "hs_phy_irq",
 3365                                           "dp_hs_phy_irq",
 3366                                           "dm_hs_phy_irq",
 3367                                           "ss_phy_irq";
 3368 
 3369                         power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
 3370 
 3371                         resets = <&gcc GCC_USB30_PRIM_BCR>;
 3372 
 3373                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
 3374                                         <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
 3375                         interconnect-names = "usb-ddr", "apps-usb";
 3376 
 3377                         wakeup-source;
 3378 
 3379                         usb_1_dwc3: usb@a600000 {
 3380                                 compatible = "snps,dwc3";
 3381                                 reg = <0 0x0a600000 0 0xe000>;
 3382                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 3383                                 iommus = <&apps_smmu 0xe0 0x0>;
 3384                                 snps,dis_u2_susphy_quirk;
 3385                                 snps,dis_enblslpm_quirk;
 3386                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
 3387                                 phy-names = "usb2-phy", "usb3-phy";
 3388                                 maximum-speed = "super-speed";
 3389                         };
 3390                 };
 3391 
 3392                 venus: video-codec@aa00000 {
 3393                         compatible = "qcom,sc7280-venus";
 3394                         reg = <0 0x0aa00000 0 0xd0600>;
 3395                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 3396 
 3397                         clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
 3398                                  <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
 3399                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
 3400                                  <&videocc VIDEO_CC_MVS0_CORE_CLK>,
 3401                                  <&videocc VIDEO_CC_MVS0_AXI_CLK>;
 3402                         clock-names = "core", "bus", "iface",
 3403                                       "vcodec_core", "vcodec_bus";
 3404 
 3405                         power-domains = <&videocc MVSC_GDSC>,
 3406                                         <&videocc MVS0_GDSC>,
 3407                                         <&rpmhpd SC7280_CX>;
 3408                         power-domain-names = "venus", "vcodec0", "cx";
 3409                         operating-points-v2 = <&venus_opp_table>;
 3410 
 3411                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
 3412                                         <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
 3413                         interconnect-names = "cpu-cfg", "video-mem";
 3414 
 3415                         iommus = <&apps_smmu 0x2180 0x20>,
 3416                                  <&apps_smmu 0x2184 0x20>;
 3417                         memory-region = <&video_mem>;
 3418 
 3419                         video-decoder {
 3420                                 compatible = "venus-decoder";
 3421                         };
 3422 
 3423                         video-encoder {
 3424                                 compatible = "venus-encoder";
 3425                         };
 3426 
 3427                         video-firmware {
 3428                                 iommus = <&apps_smmu 0x21a2 0x0>;
 3429                         };
 3430 
 3431                         venus_opp_table: opp-table {
 3432                                 compatible = "operating-points-v2";
 3433 
 3434                                 opp-133330000 {
 3435                                         opp-hz = /bits/ 64 <133330000>;
 3436                                         required-opps = <&rpmhpd_opp_low_svs>;
 3437                                 };
 3438 
 3439                                 opp-240000000 {
 3440                                         opp-hz = /bits/ 64 <240000000>;
 3441                                         required-opps = <&rpmhpd_opp_svs>;
 3442                                 };
 3443 
 3444                                 opp-335000000 {
 3445                                         opp-hz = /bits/ 64 <335000000>;
 3446                                         required-opps = <&rpmhpd_opp_svs_l1>;
 3447                                 };
 3448 
 3449                                 opp-424000000 {
 3450                                         opp-hz = /bits/ 64 <424000000>;
 3451                                         required-opps = <&rpmhpd_opp_nom>;
 3452                                 };
 3453 
 3454                                 opp-460000048 {
 3455                                         opp-hz = /bits/ 64 <460000048>;
 3456                                         required-opps = <&rpmhpd_opp_turbo>;
 3457                                 };
 3458                         };
 3459 
 3460                 };
 3461 
 3462                 videocc: clock-controller@aaf0000 {
 3463                         compatible = "qcom,sc7280-videocc";
 3464                         reg = <0 0xaaf0000 0 0x10000>;
 3465                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 3466                                 <&rpmhcc RPMH_CXO_CLK_A>;
 3467                         clock-names = "bi_tcxo", "bi_tcxo_ao";
 3468                         #clock-cells = <1>;
 3469                         #reset-cells = <1>;
 3470                         #power-domain-cells = <1>;
 3471                 };
 3472 
 3473                 camcc: clock-controller@ad00000 {
 3474                         compatible = "qcom,sc7280-camcc";
 3475                         reg = <0 0x0ad00000 0 0x10000>;
 3476                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 3477                                 <&rpmhcc RPMH_CXO_CLK_A>,
 3478                                 <&sleep_clk>;
 3479                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 3480                         #clock-cells = <1>;
 3481                         #reset-cells = <1>;
 3482                         #power-domain-cells = <1>;
 3483                 };
 3484 
 3485                 dispcc: clock-controller@af00000 {
 3486                         compatible = "qcom,sc7280-dispcc";
 3487                         reg = <0 0xaf00000 0 0x20000>;
 3488                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 3489                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
 3490                                  <&mdss_dsi_phy 0>,
 3491                                  <&mdss_dsi_phy 1>,
 3492                                  <&dp_phy 0>,
 3493                                  <&dp_phy 1>,
 3494                                  <&mdss_edp_phy 0>,
 3495                                  <&mdss_edp_phy 1>;
 3496                         clock-names = "bi_tcxo",
 3497                                       "gcc_disp_gpll0_clk",
 3498                                       "dsi0_phy_pll_out_byteclk",
 3499                                       "dsi0_phy_pll_out_dsiclk",
 3500                                       "dp_phy_pll_link_clk",
 3501                                       "dp_phy_pll_vco_div_clk",
 3502                                       "edp_phy_pll_link_clk",
 3503                                       "edp_phy_pll_vco_div_clk";
 3504                         #clock-cells = <1>;
 3505                         #reset-cells = <1>;
 3506                         #power-domain-cells = <1>;
 3507                 };
 3508 
 3509                 mdss: display-subsystem@ae00000 {
 3510                         compatible = "qcom,sc7280-mdss";
 3511                         reg = <0 0x0ae00000 0 0x1000>;
 3512                         reg-names = "mdss";
 3513 
 3514                         power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
 3515 
 3516                         clocks = <&gcc GCC_DISP_AHB_CLK>,
 3517                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
 3518                                 <&dispcc DISP_CC_MDSS_MDP_CLK>;
 3519                         clock-names = "iface",
 3520                                       "ahb",
 3521                                       "core";
 3522 
 3523                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 3524                         interrupt-controller;
 3525                         #interrupt-cells = <1>;
 3526 
 3527                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
 3528                         interconnect-names = "mdp0-mem";
 3529 
 3530                         iommus = <&apps_smmu 0x900 0x402>;
 3531 
 3532                         #address-cells = <2>;
 3533                         #size-cells = <2>;
 3534                         ranges;
 3535 
 3536                         status = "disabled";
 3537 
 3538                         mdss_mdp: display-controller@ae01000 {
 3539                                 compatible = "qcom,sc7280-dpu";
 3540                                 reg = <0 0x0ae01000 0 0x8f030>,
 3541                                         <0 0x0aeb0000 0 0x2008>;
 3542                                 reg-names = "mdp", "vbif";
 3543 
 3544                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
 3545                                         <&gcc GCC_DISP_SF_AXI_CLK>,
 3546                                         <&dispcc DISP_CC_MDSS_AHB_CLK>,
 3547                                         <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
 3548                                         <&dispcc DISP_CC_MDSS_MDP_CLK>,
 3549                                         <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 3550                                 clock-names = "bus",
 3551                                               "nrt_bus",
 3552                                               "iface",
 3553                                               "lut",
 3554                                               "core",
 3555                                               "vsync";
 3556                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
 3557                                                 <&dispcc DISP_CC_MDSS_AHB_CLK>;
 3558                                 assigned-clock-rates = <19200000>,
 3559                                                         <19200000>;
 3560                                 operating-points-v2 = <&mdp_opp_table>;
 3561                                 power-domains = <&rpmhpd SC7280_CX>;
 3562 
 3563                                 interrupt-parent = <&mdss>;
 3564                                 interrupts = <0>;
 3565 
 3566                                 status = "disabled";
 3567 
 3568                                 ports {
 3569                                         #address-cells = <1>;
 3570                                         #size-cells = <0>;
 3571 
 3572                                         port@0 {
 3573                                                 reg = <0>;
 3574                                                 dpu_intf1_out: endpoint {
 3575                                                         remote-endpoint = <&dsi0_in>;
 3576                                                 };
 3577                                         };
 3578 
 3579                                         port@1 {
 3580                                                 reg = <1>;
 3581                                                 dpu_intf5_out: endpoint {
 3582                                                         remote-endpoint = <&edp_in>;
 3583                                                 };
 3584                                         };
 3585 
 3586                                         port@2 {
 3587                                                 reg = <2>;
 3588                                                 dpu_intf0_out: endpoint {
 3589                                                         remote-endpoint = <&dp_in>;
 3590                                                 };
 3591                                         };
 3592                                 };
 3593 
 3594                                 mdp_opp_table: opp-table {
 3595                                         compatible = "operating-points-v2";
 3596 
 3597                                         opp-200000000 {
 3598                                                 opp-hz = /bits/ 64 <200000000>;
 3599                                                 required-opps = <&rpmhpd_opp_low_svs>;
 3600                                         };
 3601 
 3602                                         opp-300000000 {
 3603                                                 opp-hz = /bits/ 64 <300000000>;
 3604                                                 required-opps = <&rpmhpd_opp_svs>;
 3605                                         };
 3606 
 3607                                         opp-380000000 {
 3608                                                 opp-hz = /bits/ 64 <380000000>;
 3609                                                 required-opps = <&rpmhpd_opp_svs_l1>;
 3610                                         };
 3611 
 3612                                         opp-506666667 {
 3613                                                 opp-hz = /bits/ 64 <506666667>;
 3614                                                 required-opps = <&rpmhpd_opp_nom>;
 3615                                         };
 3616                                 };
 3617                         };
 3618 
 3619                         mdss_dsi: dsi@ae94000 {
 3620                                 compatible = "qcom,mdss-dsi-ctrl";
 3621                                 reg = <0 0x0ae94000 0 0x400>;
 3622                                 reg-names = "dsi_ctrl";
 3623 
 3624                                 interrupt-parent = <&mdss>;
 3625                                 interrupts = <4>;
 3626 
 3627                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 3628                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 3629                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 3630                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 3631                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
 3632                                          <&gcc GCC_DISP_HF_AXI_CLK>;
 3633                                 clock-names = "byte",
 3634                                               "byte_intf",
 3635                                               "pixel",
 3636                                               "core",
 3637                                               "iface",
 3638                                               "bus";
 3639 
 3640                                 operating-points-v2 = <&dsi_opp_table>;
 3641                                 power-domains = <&rpmhpd SC7280_CX>;
 3642 
 3643                                 phys = <&mdss_dsi_phy>;
 3644                                 phy-names = "dsi";
 3645 
 3646                                 #address-cells = <1>;
 3647                                 #size-cells = <0>;
 3648 
 3649                                 status = "disabled";
 3650 
 3651                                 ports {
 3652                                         #address-cells = <1>;
 3653                                         #size-cells = <0>;
 3654 
 3655                                         port@0 {
 3656                                                 reg = <0>;
 3657                                                 dsi0_in: endpoint {
 3658                                                         remote-endpoint = <&dpu_intf1_out>;
 3659                                                 };
 3660                                         };
 3661 
 3662                                         port@1 {
 3663                                                 reg = <1>;
 3664                                                 dsi0_out: endpoint {
 3665                                                 };
 3666                                         };
 3667                                 };
 3668 
 3669                                 dsi_opp_table: opp-table {
 3670                                         compatible = "operating-points-v2";
 3671 
 3672                                         opp-187500000 {
 3673                                                 opp-hz = /bits/ 64 <187500000>;
 3674                                                 required-opps = <&rpmhpd_opp_low_svs>;
 3675                                         };
 3676 
 3677                                         opp-300000000 {
 3678                                                 opp-hz = /bits/ 64 <300000000>;
 3679                                                 required-opps = <&rpmhpd_opp_svs>;
 3680                                         };
 3681 
 3682                                         opp-358000000 {
 3683                                                 opp-hz = /bits/ 64 <358000000>;
 3684                                                 required-opps = <&rpmhpd_opp_svs_l1>;
 3685                                         };
 3686                                 };
 3687                         };
 3688 
 3689                         mdss_dsi_phy: phy@ae94400 {
 3690                                 compatible = "qcom,sc7280-dsi-phy-7nm";
 3691                                 reg = <0 0x0ae94400 0 0x200>,
 3692                                       <0 0x0ae94600 0 0x280>,
 3693                                       <0 0x0ae94900 0 0x280>;
 3694                                 reg-names = "dsi_phy",
 3695                                             "dsi_phy_lane",
 3696                                             "dsi_pll";
 3697 
 3698                                 #clock-cells = <1>;
 3699                                 #phy-cells = <0>;
 3700 
 3701                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 3702                                          <&rpmhcc RPMH_CXO_CLK>;
 3703                                 clock-names = "iface", "ref";
 3704 
 3705                                 status = "disabled";
 3706                         };
 3707 
 3708                         mdss_edp: edp@aea0000 {
 3709                                 compatible = "qcom,sc7280-edp";
 3710                                 pinctrl-names = "default";
 3711                                 pinctrl-0 = <&edp_hot_plug_det>;
 3712 
 3713                                 reg = <0 0xaea0000 0 0x200>,
 3714                                       <0 0xaea0200 0 0x200>,
 3715                                       <0 0xaea0400 0 0xc00>,
 3716                                       <0 0xaea1000 0 0x400>;
 3717 
 3718                                 interrupt-parent = <&mdss>;
 3719                                 interrupts = <14>;
 3720 
 3721                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 3722                                          <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
 3723                                          <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
 3724                                          <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
 3725                                          <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
 3726                                 clock-names = "core_iface",
 3727                                               "core_aux",
 3728                                               "ctrl_link",
 3729                                               "ctrl_link_iface",
 3730                                               "stream_pixel";
 3731                                 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
 3732                                                   <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
 3733                                 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
 3734 
 3735                                 phys = <&mdss_edp_phy>;
 3736                                 phy-names = "dp";
 3737 
 3738                                 operating-points-v2 = <&edp_opp_table>;
 3739                                 power-domains = <&rpmhpd SC7280_CX>;
 3740 
 3741                                 status = "disabled";
 3742 
 3743                                 ports {
 3744                                         #address-cells = <1>;
 3745                                         #size-cells = <0>;
 3746 
 3747                                         port@0 {
 3748                                                 reg = <0>;
 3749                                                 edp_in: endpoint {
 3750                                                         remote-endpoint = <&dpu_intf5_out>;
 3751                                                 };
 3752                                         };
 3753 
 3754                                         port@1 {
 3755                                                 reg = <1>;
 3756                                                 mdss_edp_out: endpoint { };
 3757                                         };
 3758                                 };
 3759 
 3760                                 edp_opp_table: opp-table {
 3761                                         compatible = "operating-points-v2";
 3762 
 3763                                         opp-160000000 {
 3764                                                 opp-hz = /bits/ 64 <160000000>;
 3765                                                 required-opps = <&rpmhpd_opp_low_svs>;
 3766                                         };
 3767 
 3768                                         opp-270000000 {
 3769                                                 opp-hz = /bits/ 64 <270000000>;
 3770                                                 required-opps = <&rpmhpd_opp_svs>;
 3771                                         };
 3772 
 3773                                         opp-540000000 {
 3774                                                 opp-hz = /bits/ 64 <540000000>;
 3775                                                 required-opps = <&rpmhpd_opp_nom>;
 3776                                         };
 3777 
 3778                                         opp-810000000 {
 3779                                                 opp-hz = /bits/ 64 <810000000>;
 3780                                                 required-opps = <&rpmhpd_opp_nom>;
 3781                                         };
 3782                                 };
 3783                         };
 3784 
 3785                         mdss_edp_phy: phy@aec2a00 {
 3786                                 compatible = "qcom,sc7280-edp-phy";
 3787 
 3788                                 reg = <0 0xaec2a00 0 0x19c>,
 3789                                       <0 0xaec2200 0 0xa0>,
 3790                                       <0 0xaec2600 0 0xa0>,
 3791                                       <0 0xaec2000 0 0x1c0>;
 3792 
 3793                                 clocks = <&rpmhcc RPMH_CXO_CLK>,
 3794                                          <&gcc GCC_EDP_CLKREF_EN>;
 3795                                 clock-names = "aux",
 3796                                               "cfg_ahb";
 3797 
 3798                                 #clock-cells = <1>;
 3799                                 #phy-cells = <0>;
 3800 
 3801                                 status = "disabled";
 3802                         };
 3803 
 3804                         mdss_dp: displayport-controller@ae90000 {
 3805                                 compatible = "qcom,sc7280-dp";
 3806 
 3807                                 reg = <0 0xae90000 0 0x200>,
 3808                                       <0 0xae90200 0 0x200>,
 3809                                       <0 0xae90400 0 0xc00>,
 3810                                       <0 0xae91000 0 0x400>,
 3811                                       <0 0xae91400 0 0x400>;
 3812 
 3813                                 interrupt-parent = <&mdss>;
 3814                                 interrupts = <12>;
 3815 
 3816                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 3817                                          <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
 3818                                          <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
 3819                                          <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
 3820                                          <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
 3821                                 clock-names = "core_iface",
 3822                                                 "core_aux",
 3823                                                 "ctrl_link",
 3824                                                 "ctrl_link_iface",
 3825                                                 "stream_pixel";
 3826                                 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
 3827                                                   <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
 3828                                 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
 3829                                 phys = <&dp_phy>;
 3830                                 phy-names = "dp";
 3831 
 3832                                 operating-points-v2 = <&dp_opp_table>;
 3833                                 power-domains = <&rpmhpd SC7280_CX>;
 3834 
 3835                                 #sound-dai-cells = <0>;
 3836 
 3837                                 status = "disabled";
 3838 
 3839                                 ports {
 3840                                         #address-cells = <1>;
 3841                                         #size-cells = <0>;
 3842 
 3843                                         port@0 {
 3844                                                 reg = <0>;
 3845                                                 dp_in: endpoint {
 3846                                                         remote-endpoint = <&dpu_intf0_out>;
 3847                                                 };
 3848                                         };
 3849 
 3850                                         port@1 {
 3851                                                 reg = <1>;
 3852                                                 dp_out: endpoint { };
 3853                                         };
 3854                                 };
 3855 
 3856                                 dp_opp_table: opp-table {
 3857                                         compatible = "operating-points-v2";
 3858 
 3859                                         opp-160000000 {
 3860                                                 opp-hz = /bits/ 64 <160000000>;
 3861                                                 required-opps = <&rpmhpd_opp_low_svs>;
 3862                                         };
 3863 
 3864                                         opp-270000000 {
 3865                                                 opp-hz = /bits/ 64 <270000000>;
 3866                                                 required-opps = <&rpmhpd_opp_svs>;
 3867                                         };
 3868 
 3869                                         opp-540000000 {
 3870                                                 opp-hz = /bits/ 64 <540000000>;
 3871                                                 required-opps = <&rpmhpd_opp_svs_l1>;
 3872                                         };
 3873 
 3874                                         opp-810000000 {
 3875                                                 opp-hz = /bits/ 64 <810000000>;
 3876                                                 required-opps = <&rpmhpd_opp_nom>;
 3877                                         };
 3878                                 };
 3879                         };
 3880                 };
 3881 
 3882                 pdc: interrupt-controller@b220000 {
 3883                         compatible = "qcom,sc7280-pdc", "qcom,pdc";
 3884                         reg = <0 0x0b220000 0 0x30000>;
 3885                         qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
 3886                                           <55 306 4>, <59 312 3>, <62 374 2>,
 3887                                           <64 434 2>, <66 438 3>, <69 86 1>,
 3888                                           <70 520 54>, <124 609 31>, <155 63 1>,
 3889                                           <156 716 12>;
 3890                         #interrupt-cells = <2>;
 3891                         interrupt-parent = <&intc>;
 3892                         interrupt-controller;
 3893                 };
 3894 
 3895                 pdc_reset: reset-controller@b5e0000 {
 3896                         compatible = "qcom,sc7280-pdc-global";
 3897                         reg = <0 0x0b5e0000 0 0x20000>;
 3898                         #reset-cells = <1>;
 3899                 };
 3900 
 3901                 tsens0: thermal-sensor@c263000 {
 3902                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
 3903                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
 3904                                 <0 0x0c222000 0 0x1ff>; /* SROT */
 3905                         #qcom,sensors = <15>;
 3906                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
 3907                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
 3908                         interrupt-names = "uplow","critical";
 3909                         #thermal-sensor-cells = <1>;
 3910                 };
 3911 
 3912                 tsens1: thermal-sensor@c265000 {
 3913                         compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
 3914                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
 3915                                 <0 0x0c223000 0 0x1ff>; /* SROT */
 3916                         #qcom,sensors = <12>;
 3917                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
 3918                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
 3919                         interrupt-names = "uplow","critical";
 3920                         #thermal-sensor-cells = <1>;
 3921                 };
 3922 
 3923                 aoss_reset: reset-controller@c2a0000 {
 3924                         compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
 3925                         reg = <0 0x0c2a0000 0 0x31000>;
 3926                         #reset-cells = <1>;
 3927                 };
 3928 
 3929                 aoss_qmp: power-controller@c300000 {
 3930                         compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
 3931                         reg = <0 0x0c300000 0 0x400>;
 3932                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP
 3933                                                      IPCC_MPROC_SIGNAL_GLINK_QMP
 3934                                                      IRQ_TYPE_EDGE_RISING>;
 3935                         mboxes = <&ipcc IPCC_CLIENT_AOP
 3936                                         IPCC_MPROC_SIGNAL_GLINK_QMP>;
 3937 
 3938                         #clock-cells = <0>;
 3939                 };
 3940 
 3941                 sram@c3f0000 {
 3942                         compatible = "qcom,rpmh-stats";
 3943                         reg = <0 0x0c3f0000 0 0x400>;
 3944                 };
 3945 
 3946                 spmi_bus: spmi@c440000 {
 3947                         compatible = "qcom,spmi-pmic-arb";
 3948                         reg = <0 0x0c440000 0 0x1100>,
 3949                               <0 0x0c600000 0 0x2000000>,
 3950                               <0 0x0e600000 0 0x100000>,
 3951                               <0 0x0e700000 0 0xa0000>,
 3952                               <0 0x0c40a000 0 0x26000>;
 3953                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 3954                         interrupt-names = "periph_irq";
 3955                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
 3956                         qcom,ee = <0>;
 3957                         qcom,channel = <0>;
 3958                         #address-cells = <1>;
 3959                         #size-cells = <1>;
 3960                         interrupt-controller;
 3961                         #interrupt-cells = <4>;
 3962                 };
 3963 
 3964                 tlmm: pinctrl@f100000 {
 3965                         compatible = "qcom,sc7280-pinctrl";
 3966                         reg = <0 0x0f100000 0 0x300000>;
 3967                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 3968                         gpio-controller;
 3969                         #gpio-cells = <2>;
 3970                         interrupt-controller;
 3971                         #interrupt-cells = <2>;
 3972                         gpio-ranges = <&tlmm 0 0 175>;
 3973                         wakeup-parent = <&pdc>;
 3974 
 3975                         dp_hot_plug_det: dp-hot-plug-det {
 3976                                 pins = "gpio47";
 3977                                 function = "dp_hot";
 3978                         };
 3979 
 3980                         edp_hot_plug_det: edp-hot-plug-det {
 3981                                 pins = "gpio60";
 3982                                 function = "edp_hot";
 3983                         };
 3984 
 3985                         mi2s0_data0: mi2s0-data0 {
 3986                                 pins = "gpio98";
 3987                                 function = "mi2s0_data0";
 3988                         };
 3989 
 3990                         mi2s0_data1: mi2s0-data1 {
 3991                                 pins = "gpio99";
 3992                                 function = "mi2s0_data1";
 3993                         };
 3994 
 3995                         mi2s0_mclk: mi2s0-mclk {
 3996                                 pins = "gpio96";
 3997                                 function = "pri_mi2s";
 3998                         };
 3999 
 4000                         mi2s0_sclk: mi2s0-sclk {
 4001                                 pins = "gpio97";
 4002                                 function = "mi2s0_sck";
 4003                         };
 4004 
 4005                         mi2s0_ws: mi2s0-ws {
 4006                                 pins = "gpio100";
 4007                                 function = "mi2s0_ws";
 4008                         };
 4009 
 4010                         mi2s1_data0: mi2s1-data0 {
 4011                                 pins = "gpio107";
 4012                                 function = "mi2s1_data0";
 4013                         };
 4014 
 4015                         mi2s1_sclk: mi2s1-sclk {
 4016                                 pins = "gpio106";
 4017                                 function = "mi2s1_sck";
 4018                         };
 4019 
 4020                         mi2s1_ws: mi2s1-ws {
 4021                                 pins = "gpio108";
 4022                                 function = "mi2s1_ws";
 4023                         };
 4024 
 4025                         pcie1_clkreq_n: pcie1-clkreq-n {
 4026                                 pins = "gpio79";
 4027                                 function = "pcie1_clkreqn";
 4028                         };
 4029 
 4030                         qspi_clk: qspi-clk {
 4031                                 pins = "gpio14";
 4032                                 function = "qspi_clk";
 4033                         };
 4034 
 4035                         qspi_cs0: qspi-cs0 {
 4036                                 pins = "gpio15";
 4037                                 function = "qspi_cs";
 4038                         };
 4039 
 4040                         qspi_cs1: qspi-cs1 {
 4041                                 pins = "gpio19";
 4042                                 function = "qspi_cs";
 4043                         };
 4044 
 4045                         qspi_data01: qspi-data01 {
 4046                                 pins = "gpio12", "gpio13";
 4047                                 function = "qspi_data";
 4048                         };
 4049 
 4050                         qspi_data12: qspi-data12 {
 4051                                 pins = "gpio16", "gpio17";
 4052                                 function = "qspi_data";
 4053                         };
 4054 
 4055                         qup_i2c0_data_clk: qup-i2c0-data-clk {
 4056                                 pins = "gpio0", "gpio1";
 4057                                 function = "qup00";
 4058                         };
 4059 
 4060                         qup_i2c1_data_clk: qup-i2c1-data-clk {
 4061                                 pins = "gpio4", "gpio5";
 4062                                 function = "qup01";
 4063                         };
 4064 
 4065                         qup_i2c2_data_clk: qup-i2c2-data-clk {
 4066                                 pins = "gpio8", "gpio9";
 4067                                 function = "qup02";
 4068                         };
 4069 
 4070                         qup_i2c3_data_clk: qup-i2c3-data-clk {
 4071                                 pins = "gpio12", "gpio13";
 4072                                 function = "qup03";
 4073                         };
 4074 
 4075                         qup_i2c4_data_clk: qup-i2c4-data-clk {
 4076                                 pins = "gpio16", "gpio17";
 4077                                 function = "qup04";
 4078                         };
 4079 
 4080                         qup_i2c5_data_clk: qup-i2c5-data-clk {
 4081                                 pins = "gpio20", "gpio21";
 4082                                 function = "qup05";
 4083                         };
 4084 
 4085                         qup_i2c6_data_clk: qup-i2c6-data-clk {
 4086                                 pins = "gpio24", "gpio25";
 4087                                 function = "qup06";
 4088                         };
 4089 
 4090                         qup_i2c7_data_clk: qup-i2c7-data-clk {
 4091                                 pins = "gpio28", "gpio29";
 4092                                 function = "qup07";
 4093                         };
 4094 
 4095                         qup_i2c8_data_clk: qup-i2c8-data-clk {
 4096                                 pins = "gpio32", "gpio33";
 4097                                 function = "qup10";
 4098                         };
 4099 
 4100                         qup_i2c9_data_clk: qup-i2c9-data-clk {
 4101                                 pins = "gpio36", "gpio37";
 4102                                 function = "qup11";
 4103                         };
 4104 
 4105                         qup_i2c10_data_clk: qup-i2c10-data-clk {
 4106                                 pins = "gpio40", "gpio41";
 4107                                 function = "qup12";
 4108                         };
 4109 
 4110                         qup_i2c11_data_clk: qup-i2c11-data-clk {
 4111                                 pins = "gpio44", "gpio45";
 4112                                 function = "qup13";
 4113                         };
 4114 
 4115                         qup_i2c12_data_clk: qup-i2c12-data-clk {
 4116                                 pins = "gpio48", "gpio49";
 4117                                 function = "qup14";
 4118                         };
 4119 
 4120                         qup_i2c13_data_clk: qup-i2c13-data-clk {
 4121                                 pins = "gpio52", "gpio53";
 4122                                 function = "qup15";
 4123                         };
 4124 
 4125                         qup_i2c14_data_clk: qup-i2c14-data-clk {
 4126                                 pins = "gpio56", "gpio57";
 4127                                 function = "qup16";
 4128                         };
 4129 
 4130                         qup_i2c15_data_clk: qup-i2c15-data-clk {
 4131                                 pins = "gpio60", "gpio61";
 4132                                 function = "qup17";
 4133                         };
 4134 
 4135                         qup_spi0_data_clk: qup-spi0-data-clk {
 4136                                 pins = "gpio0", "gpio1", "gpio2";
 4137                                 function = "qup00";
 4138                         };
 4139 
 4140                         qup_spi0_cs: qup-spi0-cs {
 4141                                 pins = "gpio3";
 4142                                 function = "qup00";
 4143                         };
 4144 
 4145                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
 4146                                 pins = "gpio3";
 4147                                 function = "gpio";
 4148                         };
 4149 
 4150                         qup_spi1_data_clk: qup-spi1-data-clk {
 4151                                 pins = "gpio4", "gpio5", "gpio6";
 4152                                 function = "qup01";
 4153                         };
 4154 
 4155                         qup_spi1_cs: qup-spi1-cs {
 4156                                 pins = "gpio7";
 4157                                 function = "qup01";
 4158                         };
 4159 
 4160                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
 4161                                 pins = "gpio7";
 4162                                 function = "gpio";
 4163                         };
 4164 
 4165                         qup_spi2_data_clk: qup-spi2-data-clk {
 4166                                 pins = "gpio8", "gpio9", "gpio10";
 4167                                 function = "qup02";
 4168                         };
 4169 
 4170                         qup_spi2_cs: qup-spi2-cs {
 4171                                 pins = "gpio11";
 4172                                 function = "qup02";
 4173                         };
 4174 
 4175                         qup_spi2_cs_gpio: qup-spi2-cs-gpio {
 4176                                 pins = "gpio11";
 4177                                 function = "gpio";
 4178                         };
 4179 
 4180                         qup_spi3_data_clk: qup-spi3-data-clk {
 4181                                 pins = "gpio12", "gpio13", "gpio14";
 4182                                 function = "qup03";
 4183                         };
 4184 
 4185                         qup_spi3_cs: qup-spi3-cs {
 4186                                 pins = "gpio15";
 4187                                 function = "qup03";
 4188                         };
 4189 
 4190                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
 4191                                 pins = "gpio15";
 4192                                 function = "gpio";
 4193                         };
 4194 
 4195                         qup_spi4_data_clk: qup-spi4-data-clk {
 4196                                 pins = "gpio16", "gpio17", "gpio18";
 4197                                 function = "qup04";
 4198                         };
 4199 
 4200                         qup_spi4_cs: qup-spi4-cs {
 4201                                 pins = "gpio19";
 4202                                 function = "qup04";
 4203                         };
 4204 
 4205                         qup_spi4_cs_gpio: qup-spi4-cs-gpio {
 4206                                 pins = "gpio19";
 4207                                 function = "gpio";
 4208                         };
 4209 
 4210                         qup_spi5_data_clk: qup-spi5-data-clk {
 4211                                 pins = "gpio20", "gpio21", "gpio22";
 4212                                 function = "qup05";
 4213                         };
 4214 
 4215                         qup_spi5_cs: qup-spi5-cs {
 4216                                 pins = "gpio23";
 4217                                 function = "qup05";
 4218                         };
 4219 
 4220                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
 4221                                 pins = "gpio23";
 4222                                 function = "gpio";
 4223                         };
 4224 
 4225                         qup_spi6_data_clk: qup-spi6-data-clk {
 4226                                 pins = "gpio24", "gpio25", "gpio26";
 4227                                 function = "qup06";
 4228                         };
 4229 
 4230                         qup_spi6_cs: qup-spi6-cs {
 4231                                 pins = "gpio27";
 4232                                 function = "qup06";
 4233                         };
 4234 
 4235                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
 4236                                 pins = "gpio27";
 4237                                 function = "gpio";
 4238                         };
 4239 
 4240                         qup_spi7_data_clk: qup-spi7-data-clk {
 4241                                 pins = "gpio28", "gpio29", "gpio30";
 4242                                 function = "qup07";
 4243                         };
 4244 
 4245                         qup_spi7_cs: qup-spi7-cs {
 4246                                 pins = "gpio31";
 4247                                 function = "qup07";
 4248                         };
 4249 
 4250                         qup_spi7_cs_gpio: qup-spi7-cs-gpio {
 4251                                 pins = "gpio31";
 4252                                 function = "gpio";
 4253                         };
 4254 
 4255                         qup_spi8_data_clk: qup-spi8-data-clk {
 4256                                 pins = "gpio32", "gpio33", "gpio34";
 4257                                 function = "qup10";
 4258                         };
 4259 
 4260                         qup_spi8_cs: qup-spi8-cs {
 4261                                 pins = "gpio35";
 4262                                 function = "qup10";
 4263                         };
 4264 
 4265                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
 4266                                 pins = "gpio35";
 4267                                 function = "gpio";
 4268                         };
 4269 
 4270                         qup_spi9_data_clk: qup-spi9-data-clk {
 4271                                 pins = "gpio36", "gpio37", "gpio38";
 4272                                 function = "qup11";
 4273                         };
 4274 
 4275                         qup_spi9_cs: qup-spi9-cs {
 4276                                 pins = "gpio39";
 4277                                 function = "qup11";
 4278                         };
 4279 
 4280                         qup_spi9_cs_gpio: qup-spi9-cs-gpio {
 4281                                 pins = "gpio39";
 4282                                 function = "gpio";
 4283                         };
 4284 
 4285                         qup_spi10_data_clk: qup-spi10-data-clk {
 4286                                 pins = "gpio40", "gpio41", "gpio42";
 4287                                 function = "qup12";
 4288                         };
 4289 
 4290                         qup_spi10_cs: qup-spi10-cs {
 4291                                 pins = "gpio43";
 4292                                 function = "qup12";
 4293                         };
 4294 
 4295                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
 4296                                 pins = "gpio43";
 4297                                 function = "gpio";
 4298                         };
 4299 
 4300                         qup_spi11_data_clk: qup-spi11-data-clk {
 4301                                 pins = "gpio44", "gpio45", "gpio46";
 4302                                 function = "qup13";
 4303                         };
 4304 
 4305                         qup_spi11_cs: qup-spi11-cs {
 4306                                 pins = "gpio47";
 4307                                 function = "qup13";
 4308                         };
 4309 
 4310                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
 4311                                 pins = "gpio47";
 4312                                 function = "gpio";
 4313                         };
 4314 
 4315                         qup_spi12_data_clk: qup-spi12-data-clk {
 4316                                 pins = "gpio48", "gpio49", "gpio50";
 4317                                 function = "qup14";
 4318                         };
 4319 
 4320                         qup_spi12_cs: qup-spi12-cs {
 4321                                 pins = "gpio51";
 4322                                 function = "qup14";
 4323                         };
 4324 
 4325                         qup_spi12_cs_gpio: qup-spi12-cs-gpio {
 4326                                 pins = "gpio51";
 4327                                 function = "gpio";
 4328                         };
 4329 
 4330                         qup_spi13_data_clk: qup-spi13-data-clk {
 4331                                 pins = "gpio52", "gpio53", "gpio54";
 4332                                 function = "qup15";
 4333                         };
 4334 
 4335                         qup_spi13_cs: qup-spi13-cs {
 4336                                 pins = "gpio55";
 4337                                 function = "qup15";
 4338                         };
 4339 
 4340                         qup_spi13_cs_gpio: qup-spi13-cs-gpio {
 4341                                 pins = "gpio55";
 4342                                 function = "gpio";
 4343                         };
 4344 
 4345                         qup_spi14_data_clk: qup-spi14-data-clk {
 4346                                 pins = "gpio56", "gpio57", "gpio58";
 4347                                 function = "qup16";
 4348                         };
 4349 
 4350                         qup_spi14_cs: qup-spi14-cs {
 4351                                 pins = "gpio59";
 4352                                 function = "qup16";
 4353                         };
 4354 
 4355                         qup_spi14_cs_gpio: qup-spi14-cs-gpio {
 4356                                 pins = "gpio59";
 4357                                 function = "gpio";
 4358                         };
 4359 
 4360                         qup_spi15_data_clk: qup-spi15-data-clk {
 4361                                 pins = "gpio60", "gpio61", "gpio62";
 4362                                 function = "qup17";
 4363                         };
 4364 
 4365                         qup_spi15_cs: qup-spi15-cs {
 4366                                 pins = "gpio63";
 4367                                 function = "qup17";
 4368                         };
 4369 
 4370                         qup_spi15_cs_gpio: qup-spi15-cs-gpio {
 4371                                 pins = "gpio63";
 4372                                 function = "gpio";
 4373                         };
 4374 
 4375                         qup_uart0_cts: qup-uart0-cts {
 4376                                 pins = "gpio0";
 4377                                 function = "qup00";
 4378                         };
 4379 
 4380                         qup_uart0_rts: qup-uart0-rts {
 4381                                 pins = "gpio1";
 4382                                 function = "qup00";
 4383                         };
 4384 
 4385                         qup_uart0_tx: qup-uart0-tx {
 4386                                 pins = "gpio2";
 4387                                 function = "qup00";
 4388                         };
 4389 
 4390                         qup_uart0_rx: qup-uart0-rx {
 4391                                 pins = "gpio3";
 4392                                 function = "qup00";
 4393                         };
 4394 
 4395                         qup_uart1_cts: qup-uart1-cts {
 4396                                 pins = "gpio4";
 4397                                 function = "qup01";
 4398                         };
 4399 
 4400                         qup_uart1_rts: qup-uart1-rts {
 4401                                 pins = "gpio5";
 4402                                 function = "qup01";
 4403                         };
 4404 
 4405                         qup_uart1_tx: qup-uart1-tx {
 4406                                 pins = "gpio6";
 4407                                 function = "qup01";
 4408                         };
 4409 
 4410                         qup_uart1_rx: qup-uart1-rx {
 4411                                 pins = "gpio7";
 4412                                 function = "qup01";
 4413                         };
 4414 
 4415                         qup_uart2_cts: qup-uart2-cts {
 4416                                 pins = "gpio8";
 4417                                 function = "qup02";
 4418                         };
 4419 
 4420                         qup_uart2_rts: qup-uart2-rts {
 4421                                 pins = "gpio9";
 4422                                 function = "qup02";
 4423                         };
 4424 
 4425                         qup_uart2_tx: qup-uart2-tx {
 4426                                 pins = "gpio10";
 4427                                 function = "qup02";
 4428                         };
 4429 
 4430                         qup_uart2_rx: qup-uart2-rx {
 4431                                 pins = "gpio11";
 4432                                 function = "qup02";
 4433                         };
 4434 
 4435                         qup_uart3_cts: qup-uart3-cts {
 4436                                 pins = "gpio12";
 4437                                 function = "qup03";
 4438                         };
 4439 
 4440                         qup_uart3_rts: qup-uart3-rts {
 4441                                 pins = "gpio13";
 4442                                 function = "qup03";
 4443                         };
 4444 
 4445                         qup_uart3_tx: qup-uart3-tx {
 4446                                 pins = "gpio14";
 4447                                 function = "qup03";
 4448                         };
 4449 
 4450                         qup_uart3_rx: qup-uart3-rx {
 4451                                 pins = "gpio15";
 4452                                 function = "qup03";
 4453                         };
 4454 
 4455                         qup_uart4_cts: qup-uart4-cts {
 4456                                 pins = "gpio16";
 4457                                 function = "qup04";
 4458                         };
 4459 
 4460                         qup_uart4_rts: qup-uart4-rts {
 4461                                 pins = "gpio17";
 4462                                 function = "qup04";
 4463                         };
 4464 
 4465                         qup_uart4_tx: qup-uart4-tx {
 4466                                 pins = "gpio18";
 4467                                 function = "qup04";
 4468                         };
 4469 
 4470                         qup_uart4_rx: qup-uart4-rx {
 4471                                 pins = "gpio19";
 4472                                 function = "qup04";
 4473                         };
 4474 
 4475                         qup_uart5_cts: qup-uart5-cts {
 4476                                 pins = "gpio20";
 4477                                 function = "qup05";
 4478                         };
 4479 
 4480                         qup_uart5_rts: qup-uart5-rts {
 4481                                 pins = "gpio21";
 4482                                 function = "qup05";
 4483                         };
 4484 
 4485                         qup_uart5_tx: qup-uart5-tx {
 4486                                 pins = "gpio22";
 4487                                 function = "qup05";
 4488                         };
 4489 
 4490                         qup_uart5_rx: qup-uart5-rx {
 4491                                 pins = "gpio23";
 4492                                 function = "qup05";
 4493                         };
 4494 
 4495                         qup_uart6_cts: qup-uart6-cts {
 4496                                 pins = "gpio24";
 4497                                 function = "qup06";
 4498                         };
 4499 
 4500                         qup_uart6_rts: qup-uart6-rts {
 4501                                 pins = "gpio25";
 4502                                 function = "qup06";
 4503                         };
 4504 
 4505                         qup_uart6_tx: qup-uart6-tx {
 4506                                 pins = "gpio26";
 4507                                 function = "qup06";
 4508                         };
 4509 
 4510                         qup_uart6_rx: qup-uart6-rx {
 4511                                 pins = "gpio27";
 4512                                 function = "qup06";
 4513                         };
 4514 
 4515                         qup_uart7_cts: qup-uart7-cts {
 4516                                 pins = "gpio28";
 4517                                 function = "qup07";
 4518                         };
 4519 
 4520                         qup_uart7_rts: qup-uart7-rts {
 4521                                 pins = "gpio29";
 4522                                 function = "qup07";
 4523                         };
 4524 
 4525                         qup_uart7_tx: qup-uart7-tx {
 4526                                 pins = "gpio30";
 4527                                 function = "qup07";
 4528                         };
 4529 
 4530                         qup_uart7_rx: qup-uart7-rx {
 4531                                 pins = "gpio31";
 4532                                 function = "qup07";
 4533                         };
 4534 
 4535                         qup_uart8_cts: qup-uart8-cts {
 4536                                 pins = "gpio32";
 4537                                 function = "qup10";
 4538                         };
 4539 
 4540                         qup_uart8_rts: qup-uart8-rts {
 4541                                 pins = "gpio33";
 4542                                 function = "qup10";
 4543                         };
 4544 
 4545                         qup_uart8_tx: qup-uart8-tx {
 4546                                 pins = "gpio34";
 4547                                 function = "qup10";
 4548                         };
 4549 
 4550                         qup_uart8_rx: qup-uart8-rx {
 4551                                 pins = "gpio35";
 4552                                 function = "qup10";
 4553                         };
 4554 
 4555                         qup_uart9_cts: qup-uart9-cts {
 4556                                 pins = "gpio36";
 4557                                 function = "qup11";
 4558                         };
 4559 
 4560                         qup_uart9_rts: qup-uart9-rts {
 4561                                 pins = "gpio37";
 4562                                 function = "qup11";
 4563                         };
 4564 
 4565                         qup_uart9_tx: qup-uart9-tx {
 4566                                 pins = "gpio38";
 4567                                 function = "qup11";
 4568                         };
 4569 
 4570                         qup_uart9_rx: qup-uart9-rx {
 4571                                 pins = "gpio39";
 4572                                 function = "qup11";
 4573                         };
 4574 
 4575                         qup_uart10_cts: qup-uart10-cts {
 4576                                 pins = "gpio40";
 4577                                 function = "qup12";
 4578                         };
 4579 
 4580                         qup_uart10_rts: qup-uart10-rts {
 4581                                 pins = "gpio41";
 4582                                 function = "qup12";
 4583                         };
 4584 
 4585                         qup_uart10_tx: qup-uart10-tx {
 4586                                 pins = "gpio42";
 4587                                 function = "qup12";
 4588                         };
 4589 
 4590                         qup_uart10_rx: qup-uart10-rx {
 4591                                 pins = "gpio43";
 4592                                 function = "qup12";
 4593                         };
 4594 
 4595                         qup_uart11_cts: qup-uart11-cts {
 4596                                 pins = "gpio44";
 4597                                 function = "qup13";
 4598                         };
 4599 
 4600                         qup_uart11_rts: qup-uart11-rts {
 4601                                 pins = "gpio45";
 4602                                 function = "qup13";
 4603                         };
 4604 
 4605                         qup_uart11_tx: qup-uart11-tx {
 4606                                 pins = "gpio46";
 4607                                 function = "qup13";
 4608                         };
 4609 
 4610                         qup_uart11_rx: qup-uart11-rx {
 4611                                 pins = "gpio47";
 4612                                 function = "qup13";
 4613                         };
 4614 
 4615                         qup_uart12_cts: qup-uart12-cts {
 4616                                 pins = "gpio48";
 4617                                 function = "qup14";
 4618                         };
 4619 
 4620                         qup_uart12_rts: qup-uart12-rts {
 4621                                 pins = "gpio49";
 4622                                 function = "qup14";
 4623                         };
 4624 
 4625                         qup_uart12_tx: qup-uart12-tx {
 4626                                 pins = "gpio50";
 4627                                 function = "qup14";
 4628                         };
 4629 
 4630                         qup_uart12_rx: qup-uart12-rx {
 4631                                 pins = "gpio51";
 4632                                 function = "qup14";
 4633                         };
 4634 
 4635                         qup_uart13_cts: qup-uart13-cts {
 4636                                 pins = "gpio52";
 4637                                 function = "qup15";
 4638                         };
 4639 
 4640                         qup_uart13_rts: qup-uart13-rts {
 4641                                 pins = "gpio53";
 4642                                 function = "qup15";
 4643                         };
 4644 
 4645                         qup_uart13_tx: qup-uart13-tx {
 4646                                 pins = "gpio54";
 4647                                 function = "qup15";
 4648                         };
 4649 
 4650                         qup_uart13_rx: qup-uart13-rx {
 4651                                 pins = "gpio55";
 4652                                 function = "qup15";
 4653                         };
 4654 
 4655                         qup_uart14_cts: qup-uart14-cts {
 4656                                 pins = "gpio56";
 4657                                 function = "qup16";
 4658                         };
 4659 
 4660                         qup_uart14_rts: qup-uart14-rts {
 4661                                 pins = "gpio57";
 4662                                 function = "qup16";
 4663                         };
 4664 
 4665                         qup_uart14_tx: qup-uart14-tx {
 4666                                 pins = "gpio58";
 4667                                 function = "qup16";
 4668                         };
 4669 
 4670                         qup_uart14_rx: qup-uart14-rx {
 4671                                 pins = "gpio59";
 4672                                 function = "qup16";
 4673                         };
 4674 
 4675                         qup_uart15_cts: qup-uart15-cts {
 4676                                 pins = "gpio60";
 4677                                 function = "qup17";
 4678                         };
 4679 
 4680                         qup_uart15_rts: qup-uart15-rts {
 4681                                 pins = "gpio61";
 4682                                 function = "qup17";
 4683                         };
 4684 
 4685                         qup_uart15_tx: qup-uart15-tx {
 4686                                 pins = "gpio62";
 4687                                 function = "qup17";
 4688                         };
 4689 
 4690                         qup_uart15_rx: qup-uart15-rx {
 4691                                 pins = "gpio63";
 4692                                 function = "qup17";
 4693                         };
 4694 
 4695                         sdc1_clk: sdc1-clk {
 4696                                 pins = "sdc1_clk";
 4697                         };
 4698 
 4699                         sdc1_cmd: sdc1-cmd {
 4700                                 pins = "sdc1_cmd";
 4701                         };
 4702 
 4703                         sdc1_data: sdc1-data {
 4704                                 pins = "sdc1_data";
 4705                         };
 4706 
 4707                         sdc1_rclk: sdc1-rclk {
 4708                                 pins = "sdc1_rclk";
 4709                         };
 4710 
 4711                         sdc1_clk_sleep: sdc1-clk-sleep {
 4712                                 pins = "sdc1_clk";
 4713                                 drive-strength = <2>;
 4714                                 bias-bus-hold;
 4715                         };
 4716 
 4717                         sdc1_cmd_sleep: sdc1-cmd-sleep {
 4718                                 pins = "sdc1_cmd";
 4719                                 drive-strength = <2>;
 4720                                 bias-bus-hold;
 4721                         };
 4722 
 4723                         sdc1_data_sleep: sdc1-data-sleep {
 4724                                 pins = "sdc1_data";
 4725                                 drive-strength = <2>;
 4726                                 bias-bus-hold;
 4727                         };
 4728 
 4729                         sdc1_rclk_sleep: sdc1-rclk-sleep {
 4730                                 pins = "sdc1_rclk";
 4731                                 drive-strength = <2>;
 4732                                 bias-bus-hold;
 4733                         };
 4734 
 4735                         sdc2_clk: sdc2-clk {
 4736                                 pins = "sdc2_clk";
 4737                         };
 4738 
 4739                         sdc2_cmd: sdc2-cmd {
 4740                                 pins = "sdc2_cmd";
 4741                         };
 4742 
 4743                         sdc2_data: sdc2-data {
 4744                                 pins = "sdc2_data";
 4745                         };
 4746 
 4747                         sdc2_clk_sleep: sdc2-clk-sleep {
 4748                                 pins = "sdc2_clk";
 4749                                 drive-strength = <2>;
 4750                                 bias-bus-hold;
 4751                         };
 4752 
 4753                         sdc2_cmd_sleep: sdc2-cmd-sleep {
 4754                                 pins = "sdc2_cmd";
 4755                                 drive-strength = <2>;
 4756                                 bias-bus-hold;
 4757                         };
 4758 
 4759                         sdc2_data_sleep: sdc2-data-sleep {
 4760                                 pins = "sdc2_data";
 4761                                 drive-strength = <2>;
 4762                                 bias-bus-hold;
 4763                         };
 4764                 };
 4765 
 4766                 sram@146a5000 {
 4767                         compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
 4768                         reg = <0 0x146a5000 0 0x6000>;
 4769 
 4770                         #address-cells = <1>;
 4771                         #size-cells = <1>;
 4772 
 4773                         ranges = <0 0 0x146a5000 0x6000>;
 4774 
 4775                         pil-reloc@594c {
 4776                                 compatible = "qcom,pil-reloc-info";
 4777                                 reg = <0x594c 0xc8>;
 4778                         };
 4779                 };
 4780 
 4781                 apps_smmu: iommu@15000000 {
 4782                         compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
 4783                         reg = <0 0x15000000 0 0x100000>;
 4784                         #iommu-cells = <2>;
 4785                         #global-interrupts = <1>;
 4786                         dma-coherent;
 4787                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 4788                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 4789                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 4790                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 4791                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 4792                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 4793                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 4794                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 4795                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 4796                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 4797                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 4798                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 4799                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 4800                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 4801                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 4802                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 4803                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 4804                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 4805                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 4806                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 4807                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 4808                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 4809                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 4810                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 4811                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 4812                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 4813                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 4814                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 4815                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 4816                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 4817                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 4818                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 4819                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 4820                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 4821                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 4822                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 4823                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 4824                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 4825                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 4826                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 4827                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 4828                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 4829                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 4830                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 4831                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 4832                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 4833                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
 4834                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 4835                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 4836                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 4837                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 4838                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 4839                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 4840                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 4841                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 4842                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 4843                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 4844                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 4845                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 4846                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 4847                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 4848                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 4849                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 4850                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 4851                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 4852                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
 4853                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 4854                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
 4855                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
 4856                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
 4857                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
 4858                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
 4859                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
 4860                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
 4861                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
 4862                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
 4863                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
 4864                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
 4865                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
 4866                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
 4867                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
 4868                 };
 4869 
 4870                 intc: interrupt-controller@17a00000 {
 4871                         compatible = "arm,gic-v3";
 4872                         #address-cells = <2>;
 4873                         #size-cells = <2>;
 4874                         ranges;
 4875                         #interrupt-cells = <3>;
 4876                         interrupt-controller;
 4877                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
 4878                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
 4879                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 4880 
 4881                         gic-its@17a40000 {
 4882                                 compatible = "arm,gic-v3-its";
 4883                                 msi-controller;
 4884                                 #msi-cells = <1>;
 4885                                 reg = <0 0x17a40000 0 0x20000>;
 4886                                 status = "disabled";
 4887                         };
 4888                 };
 4889 
 4890                 watchdog@17c10000 {
 4891                         compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
 4892                         reg = <0 0x17c10000 0 0x1000>;
 4893                         clocks = <&sleep_clk>;
 4894                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 4895                 };
 4896 
 4897                 timer@17c20000 {
 4898                         #address-cells = <1>;
 4899                         #size-cells = <1>;
 4900                         ranges = <0 0 0 0x20000000>;
 4901                         compatible = "arm,armv7-timer-mem";
 4902                         reg = <0 0x17c20000 0 0x1000>;
 4903 
 4904                         frame@17c21000 {
 4905                                 frame-number = <0>;
 4906                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 4907                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 4908                                 reg = <0x17c21000 0x1000>,
 4909                                       <0x17c22000 0x1000>;
 4910                         };
 4911 
 4912                         frame@17c23000 {
 4913                                 frame-number = <1>;
 4914                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 4915                                 reg = <0x17c23000 0x1000>;
 4916                                 status = "disabled";
 4917                         };
 4918 
 4919                         frame@17c25000 {
 4920                                 frame-number = <2>;
 4921                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 4922                                 reg = <0x17c25000 0x1000>;
 4923                                 status = "disabled";
 4924                         };
 4925 
 4926                         frame@17c27000 {
 4927                                 frame-number = <3>;
 4928                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 4929                                 reg = <0x17c27000 0x1000>;
 4930                                 status = "disabled";
 4931                         };
 4932 
 4933                         frame@17c29000 {
 4934                                 frame-number = <4>;
 4935                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 4936                                 reg = <0x17c29000 0x1000>;
 4937                                 status = "disabled";
 4938                         };
 4939 
 4940                         frame@17c2b000 {
 4941                                 frame-number = <5>;
 4942                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 4943                                 reg = <0x17c2b000 0x1000>;
 4944                                 status = "disabled";
 4945                         };
 4946 
 4947                         frame@17c2d000 {
 4948                                 frame-number = <6>;
 4949                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 4950                                 reg = <0x17c2d000 0x1000>;
 4951                                 status = "disabled";
 4952                         };
 4953                 };
 4954 
 4955                 apps_rsc: rsc@18200000 {
 4956                         compatible = "qcom,rpmh-rsc";
 4957                         reg = <0 0x18200000 0 0x10000>,
 4958                               <0 0x18210000 0 0x10000>,
 4959                               <0 0x18220000 0 0x10000>;
 4960                         reg-names = "drv-0", "drv-1", "drv-2";
 4961                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 4962                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 4963                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 4964                         qcom,tcs-offset = <0xd00>;
 4965                         qcom,drv-id = <2>;
 4966                         qcom,tcs-config = <ACTIVE_TCS  2>,
 4967                                           <SLEEP_TCS   3>,
 4968                                           <WAKE_TCS    3>,
 4969                                           <CONTROL_TCS 1>;
 4970 
 4971                         apps_bcm_voter: bcm-voter {
 4972                                 compatible = "qcom,bcm-voter";
 4973                         };
 4974 
 4975                         rpmhpd: power-controller {
 4976                                 compatible = "qcom,sc7280-rpmhpd";
 4977                                 #power-domain-cells = <1>;
 4978                                 operating-points-v2 = <&rpmhpd_opp_table>;
 4979 
 4980                                 rpmhpd_opp_table: opp-table {
 4981                                         compatible = "operating-points-v2";
 4982 
 4983                                         rpmhpd_opp_ret: opp1 {
 4984                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 4985                                         };
 4986 
 4987                                         rpmhpd_opp_low_svs: opp2 {
 4988                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 4989                                         };
 4990 
 4991                                         rpmhpd_opp_svs: opp3 {
 4992                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 4993                                         };
 4994 
 4995                                         rpmhpd_opp_svs_l1: opp4 {
 4996                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 4997                                         };
 4998 
 4999                                         rpmhpd_opp_svs_l2: opp5 {
 5000                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 5001                                         };
 5002 
 5003                                         rpmhpd_opp_nom: opp6 {
 5004                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 5005                                         };
 5006 
 5007                                         rpmhpd_opp_nom_l1: opp7 {
 5008                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 5009                                         };
 5010 
 5011                                         rpmhpd_opp_turbo: opp8 {
 5012                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 5013                                         };
 5014 
 5015                                         rpmhpd_opp_turbo_l1: opp9 {
 5016                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 5017                                         };
 5018                                 };
 5019                         };
 5020 
 5021                         rpmhcc: clock-controller {
 5022                                 compatible = "qcom,sc7280-rpmh-clk";
 5023                                 clocks = <&xo_board>;
 5024                                 clock-names = "xo";
 5025                                 #clock-cells = <1>;
 5026                         };
 5027                 };
 5028 
 5029                 epss_l3: interconnect@18590000 {
 5030                         compatible = "qcom,sc7280-epss-l3";
 5031                         reg = <0 0x18590000 0 0x1000>;
 5032                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
 5033                         clock-names = "xo", "alternate";
 5034                         #interconnect-cells = <1>;
 5035                 };
 5036 
 5037                 cpufreq_hw: cpufreq@18591000 {
 5038                         compatible = "qcom,cpufreq-epss";
 5039                         reg = <0 0x18591000 0 0x1000>,
 5040                               <0 0x18592000 0 0x1000>,
 5041                               <0 0x18593000 0 0x1000>;
 5042                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
 5043                         clock-names = "xo", "alternate";
 5044                         #freq-domain-cells = <1>;
 5045                 };
 5046         };
 5047 
 5048         thermal_zones: thermal-zones {
 5049                 cpu0-thermal {
 5050                         polling-delay-passive = <250>;
 5051                         polling-delay = <0>;
 5052 
 5053                         thermal-sensors = <&tsens0 1>;
 5054 
 5055                         trips {
 5056                                 cpu0_alert0: trip-point0 {
 5057                                         temperature = <90000>;
 5058                                         hysteresis = <2000>;
 5059                                         type = "passive";
 5060                                 };
 5061 
 5062                                 cpu0_alert1: trip-point1 {
 5063                                         temperature = <95000>;
 5064                                         hysteresis = <2000>;
 5065                                         type = "passive";
 5066                                 };
 5067 
 5068                                 cpu0_crit: cpu-crit {
 5069                                         temperature = <110000>;
 5070                                         hysteresis = <0>;
 5071                                         type = "critical";
 5072                                 };
 5073                         };
 5074 
 5075                         cooling-maps {
 5076                                 map0 {
 5077                                         trip = <&cpu0_alert0>;
 5078                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5079                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5080                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5081                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5082                                 };
 5083                                 map1 {
 5084                                         trip = <&cpu0_alert1>;
 5085                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5086                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5087                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5088                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5089                                 };
 5090                         };
 5091                 };
 5092 
 5093                 cpu1-thermal {
 5094                         polling-delay-passive = <250>;
 5095                         polling-delay = <0>;
 5096 
 5097                         thermal-sensors = <&tsens0 2>;
 5098 
 5099                         trips {
 5100                                 cpu1_alert0: trip-point0 {
 5101                                         temperature = <90000>;
 5102                                         hysteresis = <2000>;
 5103                                         type = "passive";
 5104                                 };
 5105 
 5106                                 cpu1_alert1: trip-point1 {
 5107                                         temperature = <95000>;
 5108                                         hysteresis = <2000>;
 5109                                         type = "passive";
 5110                                 };
 5111 
 5112                                 cpu1_crit: cpu-crit {
 5113                                         temperature = <110000>;
 5114                                         hysteresis = <0>;
 5115                                         type = "critical";
 5116                                 };
 5117                         };
 5118 
 5119                         cooling-maps {
 5120                                 map0 {
 5121                                         trip = <&cpu1_alert0>;
 5122                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5123                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5124                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5125                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5126                                 };
 5127                                 map1 {
 5128                                         trip = <&cpu1_alert1>;
 5129                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5130                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5131                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5132                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5133                                 };
 5134                         };
 5135                 };
 5136 
 5137                 cpu2-thermal {
 5138                         polling-delay-passive = <250>;
 5139                         polling-delay = <0>;
 5140 
 5141                         thermal-sensors = <&tsens0 3>;
 5142 
 5143                         trips {
 5144                                 cpu2_alert0: trip-point0 {
 5145                                         temperature = <90000>;
 5146                                         hysteresis = <2000>;
 5147                                         type = "passive";
 5148                                 };
 5149 
 5150                                 cpu2_alert1: trip-point1 {
 5151                                         temperature = <95000>;
 5152                                         hysteresis = <2000>;
 5153                                         type = "passive";
 5154                                 };
 5155 
 5156                                 cpu2_crit: cpu-crit {
 5157                                         temperature = <110000>;
 5158                                         hysteresis = <0>;
 5159                                         type = "critical";
 5160                                 };
 5161                         };
 5162 
 5163                         cooling-maps {
 5164                                 map0 {
 5165                                         trip = <&cpu2_alert0>;
 5166                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5167                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5168                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5169                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5170                                 };
 5171                                 map1 {
 5172                                         trip = <&cpu2_alert1>;
 5173                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5174                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5175                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5176                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5177                                 };
 5178                         };
 5179                 };
 5180 
 5181                 cpu3-thermal {
 5182                         polling-delay-passive = <250>;
 5183                         polling-delay = <0>;
 5184 
 5185                         thermal-sensors = <&tsens0 4>;
 5186 
 5187                         trips {
 5188                                 cpu3_alert0: trip-point0 {
 5189                                         temperature = <90000>;
 5190                                         hysteresis = <2000>;
 5191                                         type = "passive";
 5192                                 };
 5193 
 5194                                 cpu3_alert1: trip-point1 {
 5195                                         temperature = <95000>;
 5196                                         hysteresis = <2000>;
 5197                                         type = "passive";
 5198                                 };
 5199 
 5200                                 cpu3_crit: cpu-crit {
 5201                                         temperature = <110000>;
 5202                                         hysteresis = <0>;
 5203                                         type = "critical";
 5204                                 };
 5205                         };
 5206 
 5207                         cooling-maps {
 5208                                 map0 {
 5209                                         trip = <&cpu3_alert0>;
 5210                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5211                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5212                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5213                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5214                                 };
 5215                                 map1 {
 5216                                         trip = <&cpu3_alert1>;
 5217                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5218                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5219                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5220                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5221                                 };
 5222                         };
 5223                 };
 5224 
 5225                 cpu4-thermal {
 5226                         polling-delay-passive = <250>;
 5227                         polling-delay = <0>;
 5228 
 5229                         thermal-sensors = <&tsens0 7>;
 5230 
 5231                         trips {
 5232                                 cpu4_alert0: trip-point0 {
 5233                                         temperature = <90000>;
 5234                                         hysteresis = <2000>;
 5235                                         type = "passive";
 5236                                 };
 5237 
 5238                                 cpu4_alert1: trip-point1 {
 5239                                         temperature = <95000>;
 5240                                         hysteresis = <2000>;
 5241                                         type = "passive";
 5242                                 };
 5243 
 5244                                 cpu4_crit: cpu-crit {
 5245                                         temperature = <110000>;
 5246                                         hysteresis = <0>;
 5247                                         type = "critical";
 5248                                 };
 5249                         };
 5250 
 5251                         cooling-maps {
 5252                                 map0 {
 5253                                         trip = <&cpu4_alert0>;
 5254                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5255                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5256                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5257                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5258                                 };
 5259                                 map1 {
 5260                                         trip = <&cpu4_alert1>;
 5261                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5262                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5263                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5264                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5265                                 };
 5266                         };
 5267                 };
 5268 
 5269                 cpu5-thermal {
 5270                         polling-delay-passive = <250>;
 5271                         polling-delay = <0>;
 5272 
 5273                         thermal-sensors = <&tsens0 8>;
 5274 
 5275                         trips {
 5276                                 cpu5_alert0: trip-point0 {
 5277                                         temperature = <90000>;
 5278                                         hysteresis = <2000>;
 5279                                         type = "passive";
 5280                                 };
 5281 
 5282                                 cpu5_alert1: trip-point1 {
 5283                                         temperature = <95000>;
 5284                                         hysteresis = <2000>;
 5285                                         type = "passive";
 5286                                 };
 5287 
 5288                                 cpu5_crit: cpu-crit {
 5289                                         temperature = <110000>;
 5290                                         hysteresis = <0>;
 5291                                         type = "critical";
 5292                                 };
 5293                         };
 5294 
 5295                         cooling-maps {
 5296                                 map0 {
 5297                                         trip = <&cpu5_alert0>;
 5298                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5299                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5300                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5301                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5302                                 };
 5303                                 map1 {
 5304                                         trip = <&cpu5_alert1>;
 5305                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5306                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5307                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5308                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5309                                 };
 5310                         };
 5311                 };
 5312 
 5313                 cpu6-thermal {
 5314                         polling-delay-passive = <250>;
 5315                         polling-delay = <0>;
 5316 
 5317                         thermal-sensors = <&tsens0 9>;
 5318 
 5319                         trips {
 5320                                 cpu6_alert0: trip-point0 {
 5321                                         temperature = <90000>;
 5322                                         hysteresis = <2000>;
 5323                                         type = "passive";
 5324                                 };
 5325 
 5326                                 cpu6_alert1: trip-point1 {
 5327                                         temperature = <95000>;
 5328                                         hysteresis = <2000>;
 5329                                         type = "passive";
 5330                                 };
 5331 
 5332                                 cpu6_crit: cpu-crit {
 5333                                         temperature = <110000>;
 5334                                         hysteresis = <0>;
 5335                                         type = "critical";
 5336                                 };
 5337                         };
 5338 
 5339                         cooling-maps {
 5340                                 map0 {
 5341                                         trip = <&cpu6_alert0>;
 5342                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5343                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5344                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5345                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5346                                 };
 5347                                 map1 {
 5348                                         trip = <&cpu6_alert1>;
 5349                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5350                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5351                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5352                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5353                                 };
 5354                         };
 5355                 };
 5356 
 5357                 cpu7-thermal {
 5358                         polling-delay-passive = <250>;
 5359                         polling-delay = <0>;
 5360 
 5361                         thermal-sensors = <&tsens0 10>;
 5362 
 5363                         trips {
 5364                                 cpu7_alert0: trip-point0 {
 5365                                         temperature = <90000>;
 5366                                         hysteresis = <2000>;
 5367                                         type = "passive";
 5368                                 };
 5369 
 5370                                 cpu7_alert1: trip-point1 {
 5371                                         temperature = <95000>;
 5372                                         hysteresis = <2000>;
 5373                                         type = "passive";
 5374                                 };
 5375 
 5376                                 cpu7_crit: cpu-crit {
 5377                                         temperature = <110000>;
 5378                                         hysteresis = <0>;
 5379                                         type = "critical";
 5380                                 };
 5381                         };
 5382 
 5383                         cooling-maps {
 5384                                 map0 {
 5385                                         trip = <&cpu7_alert0>;
 5386                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5387                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5388                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5389                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5390                                 };
 5391                                 map1 {
 5392                                         trip = <&cpu7_alert1>;
 5393                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5394                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5395                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5396                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5397                                 };
 5398                         };
 5399                 };
 5400 
 5401                 cpu8-thermal {
 5402                         polling-delay-passive = <250>;
 5403                         polling-delay = <0>;
 5404 
 5405                         thermal-sensors = <&tsens0 11>;
 5406 
 5407                         trips {
 5408                                 cpu8_alert0: trip-point0 {
 5409                                         temperature = <90000>;
 5410                                         hysteresis = <2000>;
 5411                                         type = "passive";
 5412                                 };
 5413 
 5414                                 cpu8_alert1: trip-point1 {
 5415                                         temperature = <95000>;
 5416                                         hysteresis = <2000>;
 5417                                         type = "passive";
 5418                                 };
 5419 
 5420                                 cpu8_crit: cpu-crit {
 5421                                         temperature = <110000>;
 5422                                         hysteresis = <0>;
 5423                                         type = "critical";
 5424                                 };
 5425                         };
 5426 
 5427                         cooling-maps {
 5428                                 map0 {
 5429                                         trip = <&cpu8_alert0>;
 5430                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5431                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5432                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5433                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5434                                 };
 5435                                 map1 {
 5436                                         trip = <&cpu8_alert1>;
 5437                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5438                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5439                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5440                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5441                                 };
 5442                         };
 5443                 };
 5444 
 5445                 cpu9-thermal {
 5446                         polling-delay-passive = <250>;
 5447                         polling-delay = <0>;
 5448 
 5449                         thermal-sensors = <&tsens0 12>;
 5450 
 5451                         trips {
 5452                                 cpu9_alert0: trip-point0 {
 5453                                         temperature = <90000>;
 5454                                         hysteresis = <2000>;
 5455                                         type = "passive";
 5456                                 };
 5457 
 5458                                 cpu9_alert1: trip-point1 {
 5459                                         temperature = <95000>;
 5460                                         hysteresis = <2000>;
 5461                                         type = "passive";
 5462                                 };
 5463 
 5464                                 cpu9_crit: cpu-crit {
 5465                                         temperature = <110000>;
 5466                                         hysteresis = <0>;
 5467                                         type = "critical";
 5468                                 };
 5469                         };
 5470 
 5471                         cooling-maps {
 5472                                 map0 {
 5473                                         trip = <&cpu9_alert0>;
 5474                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5475                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5476                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5477                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5478                                 };
 5479                                 map1 {
 5480                                         trip = <&cpu9_alert1>;
 5481                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5482                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5483                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5484                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5485                                 };
 5486                         };
 5487                 };
 5488 
 5489                 cpu10-thermal {
 5490                         polling-delay-passive = <250>;
 5491                         polling-delay = <0>;
 5492 
 5493                         thermal-sensors = <&tsens0 13>;
 5494 
 5495                         trips {
 5496                                 cpu10_alert0: trip-point0 {
 5497                                         temperature = <90000>;
 5498                                         hysteresis = <2000>;
 5499                                         type = "passive";
 5500                                 };
 5501 
 5502                                 cpu10_alert1: trip-point1 {
 5503                                         temperature = <95000>;
 5504                                         hysteresis = <2000>;
 5505                                         type = "passive";
 5506                                 };
 5507 
 5508                                 cpu10_crit: cpu-crit {
 5509                                         temperature = <110000>;
 5510                                         hysteresis = <0>;
 5511                                         type = "critical";
 5512                                 };
 5513                         };
 5514 
 5515                         cooling-maps {
 5516                                 map0 {
 5517                                         trip = <&cpu10_alert0>;
 5518                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5519                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5520                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5521                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5522                                 };
 5523                                 map1 {
 5524                                         trip = <&cpu10_alert1>;
 5525                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5526                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5527                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5528                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5529                                 };
 5530                         };
 5531                 };
 5532 
 5533                 cpu11-thermal {
 5534                         polling-delay-passive = <250>;
 5535                         polling-delay = <0>;
 5536 
 5537                         thermal-sensors = <&tsens0 14>;
 5538 
 5539                         trips {
 5540                                 cpu11_alert0: trip-point0 {
 5541                                         temperature = <90000>;
 5542                                         hysteresis = <2000>;
 5543                                         type = "passive";
 5544                                 };
 5545 
 5546                                 cpu11_alert1: trip-point1 {
 5547                                         temperature = <95000>;
 5548                                         hysteresis = <2000>;
 5549                                         type = "passive";
 5550                                 };
 5551 
 5552                                 cpu11_crit: cpu-crit {
 5553                                         temperature = <110000>;
 5554                                         hysteresis = <0>;
 5555                                         type = "critical";
 5556                                 };
 5557                         };
 5558 
 5559                         cooling-maps {
 5560                                 map0 {
 5561                                         trip = <&cpu11_alert0>;
 5562                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5563                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5564                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5565                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5566                                 };
 5567                                 map1 {
 5568                                         trip = <&cpu11_alert1>;
 5569                                         cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5570                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5571                                                          <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 5572                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5573                                 };
 5574                         };
 5575                 };
 5576 
 5577                 aoss0-thermal {
 5578                         polling-delay-passive = <0>;
 5579                         polling-delay = <0>;
 5580 
 5581                         thermal-sensors = <&tsens0 0>;
 5582 
 5583                         trips {
 5584                                 aoss0_alert0: trip-point0 {
 5585                                         temperature = <90000>;
 5586                                         hysteresis = <2000>;
 5587                                         type = "hot";
 5588                                 };
 5589 
 5590                                 aoss0_crit: aoss0-crit {
 5591                                         temperature = <110000>;
 5592                                         hysteresis = <0>;
 5593                                         type = "critical";
 5594                                 };
 5595                         };
 5596                 };
 5597 
 5598                 aoss1-thermal {
 5599                         polling-delay-passive = <0>;
 5600                         polling-delay = <0>;
 5601 
 5602                         thermal-sensors = <&tsens1 0>;
 5603 
 5604                         trips {
 5605                                 aoss1_alert0: trip-point0 {
 5606                                         temperature = <90000>;
 5607                                         hysteresis = <2000>;
 5608                                         type = "hot";
 5609                                 };
 5610 
 5611                                 aoss1_crit: aoss1-crit {
 5612                                         temperature = <110000>;
 5613                                         hysteresis = <0>;
 5614                                         type = "critical";
 5615                                 };
 5616                         };
 5617                 };
 5618 
 5619                 cpuss0-thermal {
 5620                         polling-delay-passive = <0>;
 5621                         polling-delay = <0>;
 5622 
 5623                         thermal-sensors = <&tsens0 5>;
 5624 
 5625                         trips {
 5626                                 cpuss0_alert0: trip-point0 {
 5627                                         temperature = <90000>;
 5628                                         hysteresis = <2000>;
 5629                                         type = "hot";
 5630                                 };
 5631                                 cpuss0_crit: cluster0-crit {
 5632                                         temperature = <110000>;
 5633                                         hysteresis = <0>;
 5634                                         type = "critical";
 5635                                 };
 5636                         };
 5637                 };
 5638 
 5639                 cpuss1-thermal {
 5640                         polling-delay-passive = <0>;
 5641                         polling-delay = <0>;
 5642 
 5643                         thermal-sensors = <&tsens0 6>;
 5644 
 5645                         trips {
 5646                                 cpuss1_alert0: trip-point0 {
 5647                                         temperature = <90000>;
 5648                                         hysteresis = <2000>;
 5649                                         type = "hot";
 5650                                 };
 5651                                 cpuss1_crit: cluster0-crit {
 5652                                         temperature = <110000>;
 5653                                         hysteresis = <0>;
 5654                                         type = "critical";
 5655                                 };
 5656                         };
 5657                 };
 5658 
 5659                 gpuss0-thermal {
 5660                         polling-delay-passive = <100>;
 5661                         polling-delay = <0>;
 5662 
 5663                         thermal-sensors = <&tsens1 1>;
 5664 
 5665                         trips {
 5666                                 gpuss0_alert0: trip-point0 {
 5667                                         temperature = <95000>;
 5668                                         hysteresis = <2000>;
 5669                                         type = "passive";
 5670                                 };
 5671 
 5672                                 gpuss0_crit: gpuss0-crit {
 5673                                         temperature = <110000>;
 5674                                         hysteresis = <0>;
 5675                                         type = "critical";
 5676                                 };
 5677                         };
 5678 
 5679                         cooling-maps {
 5680                                 map0 {
 5681                                         trip = <&gpuss0_alert0>;
 5682                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5683                                 };
 5684                         };
 5685                 };
 5686 
 5687                 gpuss1-thermal {
 5688                         polling-delay-passive = <100>;
 5689                         polling-delay = <0>;
 5690 
 5691                         thermal-sensors = <&tsens1 2>;
 5692 
 5693                         trips {
 5694                                 gpuss1_alert0: trip-point0 {
 5695                                         temperature = <95000>;
 5696                                         hysteresis = <2000>;
 5697                                         type = "passive";
 5698                                 };
 5699 
 5700                                 gpuss1_crit: gpuss1-crit {
 5701                                         temperature = <110000>;
 5702                                         hysteresis = <0>;
 5703                                         type = "critical";
 5704                                 };
 5705                         };
 5706 
 5707                         cooling-maps {
 5708                                 map0 {
 5709                                         trip = <&gpuss1_alert0>;
 5710                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 5711                                 };
 5712                         };
 5713                 };
 5714 
 5715                 nspss0-thermal {
 5716                         polling-delay-passive = <0>;
 5717                         polling-delay = <0>;
 5718 
 5719                         thermal-sensors = <&tsens1 3>;
 5720 
 5721                         trips {
 5722                                 nspss0_alert0: trip-point0 {
 5723                                         temperature = <90000>;
 5724                                         hysteresis = <2000>;
 5725                                         type = "hot";
 5726                                 };
 5727 
 5728                                 nspss0_crit: nspss0-crit {
 5729                                         temperature = <110000>;
 5730                                         hysteresis = <0>;
 5731                                         type = "critical";
 5732                                 };
 5733                         };
 5734                 };
 5735 
 5736                 nspss1-thermal {
 5737                         polling-delay-passive = <0>;
 5738                         polling-delay = <0>;
 5739 
 5740                         thermal-sensors = <&tsens1 4>;
 5741 
 5742                         trips {
 5743                                 nspss1_alert0: trip-point0 {
 5744                                         temperature = <90000>;
 5745                                         hysteresis = <2000>;
 5746                                         type = "hot";
 5747                                 };
 5748 
 5749                                 nspss1_crit: nspss1-crit {
 5750                                         temperature = <110000>;
 5751                                         hysteresis = <0>;
 5752                                         type = "critical";
 5753                                 };
 5754                         };
 5755                 };
 5756 
 5757                 video-thermal {
 5758                         polling-delay-passive = <0>;
 5759                         polling-delay = <0>;
 5760 
 5761                         thermal-sensors = <&tsens1 5>;
 5762 
 5763                         trips {
 5764                                 video_alert0: trip-point0 {
 5765                                         temperature = <90000>;
 5766                                         hysteresis = <2000>;
 5767                                         type = "hot";
 5768                                 };
 5769 
 5770                                 video_crit: video-crit {
 5771                                         temperature = <110000>;
 5772                                         hysteresis = <0>;
 5773                                         type = "critical";
 5774                                 };
 5775                         };
 5776                 };
 5777 
 5778                 ddr-thermal {
 5779                         polling-delay-passive = <0>;
 5780                         polling-delay = <0>;
 5781 
 5782                         thermal-sensors = <&tsens1 6>;
 5783 
 5784                         trips {
 5785                                 ddr_alert0: trip-point0 {
 5786                                         temperature = <90000>;
 5787                                         hysteresis = <2000>;
 5788                                         type = "hot";
 5789                                 };
 5790 
 5791                                 ddr_crit: ddr-crit {
 5792                                         temperature = <110000>;
 5793                                         hysteresis = <0>;
 5794                                         type = "critical";
 5795                                 };
 5796                         };
 5797                 };
 5798 
 5799                 mdmss0-thermal {
 5800                         polling-delay-passive = <0>;
 5801                         polling-delay = <0>;
 5802 
 5803                         thermal-sensors = <&tsens1 7>;
 5804 
 5805                         trips {
 5806                                 mdmss0_alert0: trip-point0 {
 5807                                         temperature = <90000>;
 5808                                         hysteresis = <2000>;
 5809                                         type = "hot";
 5810                                 };
 5811 
 5812                                 mdmss0_crit: mdmss0-crit {
 5813                                         temperature = <110000>;
 5814                                         hysteresis = <0>;
 5815                                         type = "critical";
 5816                                 };
 5817                         };
 5818                 };
 5819 
 5820                 mdmss1-thermal {
 5821                         polling-delay-passive = <0>;
 5822                         polling-delay = <0>;
 5823 
 5824                         thermal-sensors = <&tsens1 8>;
 5825 
 5826                         trips {
 5827                                 mdmss1_alert0: trip-point0 {
 5828                                         temperature = <90000>;
 5829                                         hysteresis = <2000>;
 5830                                         type = "hot";
 5831                                 };
 5832 
 5833                                 mdmss1_crit: mdmss1-crit {
 5834                                         temperature = <110000>;
 5835                                         hysteresis = <0>;
 5836                                         type = "critical";
 5837                                 };
 5838                         };
 5839                 };
 5840 
 5841                 mdmss2-thermal {
 5842                         polling-delay-passive = <0>;
 5843                         polling-delay = <0>;
 5844 
 5845                         thermal-sensors = <&tsens1 9>;
 5846 
 5847                         trips {
 5848                                 mdmss2_alert0: trip-point0 {
 5849                                         temperature = <90000>;
 5850                                         hysteresis = <2000>;
 5851                                         type = "hot";
 5852                                 };
 5853 
 5854                                 mdmss2_crit: mdmss2-crit {
 5855                                         temperature = <110000>;
 5856                                         hysteresis = <0>;
 5857                                         type = "critical";
 5858                                 };
 5859                         };
 5860                 };
 5861 
 5862                 mdmss3-thermal {
 5863                         polling-delay-passive = <0>;
 5864                         polling-delay = <0>;
 5865 
 5866                         thermal-sensors = <&tsens1 10>;
 5867 
 5868                         trips {
 5869                                 mdmss3_alert0: trip-point0 {
 5870                                         temperature = <90000>;
 5871                                         hysteresis = <2000>;
 5872                                         type = "hot";
 5873                                 };
 5874 
 5875                                 mdmss3_crit: mdmss3-crit {
 5876                                         temperature = <110000>;
 5877                                         hysteresis = <0>;
 5878                                         type = "critical";
 5879                                 };
 5880                         };
 5881                 };
 5882 
 5883                 camera0-thermal {
 5884                         polling-delay-passive = <0>;
 5885                         polling-delay = <0>;
 5886 
 5887                         thermal-sensors = <&tsens1 11>;
 5888 
 5889                         trips {
 5890                                 camera0_alert0: trip-point0 {
 5891                                         temperature = <90000>;
 5892                                         hysteresis = <2000>;
 5893                                         type = "hot";
 5894                                 };
 5895 
 5896                                 camera0_crit: camera0-crit {
 5897                                         temperature = <110000>;
 5898                                         hysteresis = <0>;
 5899                                         type = "critical";
 5900                                 };
 5901                         };
 5902                 };
 5903         };
 5904 
 5905         timer {
 5906                 compatible = "arm,armv8-timer";
 5907                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 5908                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 5909                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 5910                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 5911         };
 5912 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/sc7280.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/sc7280.dtsi
