sdm660.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0-only
    2 /*
    3  * Copyright (c) 2018, Craig Tatlor.
    4  * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com>
    5  * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com>
    6  * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com>
    7  * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com>
    8  */
    9 
   10 #include "sdm630.dtsi"
   11 
   12 &adreno_gpu {
   13         compatible = "qcom,adreno-512.0", "qcom,adreno";
   14         operating-points-v2 = <&gpu_sdm660_opp_table>;
   15 
   16         gpu_sdm660_opp_table: opp-table {
   17                 compatible = "operating-points-v2";
   18 
   19                 /*
   20                  * 775MHz is only available on the highest speed bin
   21                  * Though it cannot be used for now due to interconnect
   22                  * framework not supporting multiple frequencies
   23                  * at the same opp-level
   24 
   25                 opp-750000000 {
   26                         opp-hz = /bits/ 64 <750000000>;
   27                         opp-level = <RPM_SMD_LEVEL_TURBO>;
   28                         opp-peak-kBps = <5412000>;
   29                         opp-supported-hw = <0xCHECKME>;
   30                 };
   31 
   32                 * These OPPs are correct, but we are lacking support for the
   33                 * GPU regulator. Hence, disable them for now to prevent the
   34                 * platform from hanging on high graphics loads.
   35 
   36                 opp-700000000 {
   37                         opp-hz = /bits/ 64 <700000000>;
   38                         opp-level = <RPM_SMD_LEVEL_TURBO>;
   39                         opp-peak-kBps = <5184000>;
   40                         opp-supported-hw = <0xFF>;
   41                 };
   42 
   43                 opp-647000000 {
   44                         opp-hz = /bits/ 64 <647000000>;
   45                         opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
   46                         opp-peak-kBps = <4068000>;
   47                         opp-supported-hw = <0xFF>;
   48                 };
   49 
   50                 opp-588000000 {
   51                         opp-hz = /bits/ 64 <588000000>;
   52                         opp-level = <RPM_SMD_LEVEL_NOM>;
   53                         opp-peak-kBps = <3072000>;
   54                         opp-supported-hw = <0xFF>;
   55                 };
   56 
   57                 opp-465000000 {
   58                         opp-hz = /bits/ 64 <465000000>;
   59                         opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
   60                         opp-peak-kBps = <2724000>;
   61                         opp-supported-hw = <0xFF>;
   62                 };
   63 
   64                 opp-370000000 {
   65                         opp-hz = /bits/ 64 <370000000>;
   66                         opp-level = <RPM_SMD_LEVEL_SVS>;
   67                         opp-peak-kBps = <2188000>;
   68                         opp-supported-hw = <0xFF>;
   69                 };
   70                 */
   71 
   72                 opp-266000000 {
   73                         opp-hz = /bits/ 64 <266000000>;
   74                         opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
   75                         opp-peak-kBps = <1648000>;
   76                         opp-supported-hw = <0xFF>;
   77                 };
   78 
   79                 opp-160000000 {
   80                         opp-hz = /bits/ 64 <160000000>;
   81                         opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
   82                         opp-peak-kBps = <1200000>;
   83                         opp-supported-hw = <0xFF>;
   84                 };
   85         };
   86 };
   87 
   88 &CPU0 {
   89         compatible = "qcom,kryo260";
   90         capacity-dmips-mhz = <1024>;
   91         /delete-property/ operating-points-v2;
   92 };
   93 
   94 &CPU1 {
   95         compatible = "qcom,kryo260";
   96         capacity-dmips-mhz = <1024>;
   97         /delete-property/ operating-points-v2;
   98 };
   99 
  100 &CPU2 {
  101         compatible = "qcom,kryo260";
  102         capacity-dmips-mhz = <1024>;
  103         /delete-property/ operating-points-v2;
  104 };
  105 
  106 &CPU3 {
  107         compatible = "qcom,kryo260";
  108         capacity-dmips-mhz = <1024>;
  109         /delete-property/ operating-points-v2;
  110 };
  111 
  112 &CPU4 {
  113         compatible = "qcom,kryo260";
  114         capacity-dmips-mhz = <640>;
  115         /delete-property/ operating-points-v2;
  116 };
  117 
  118 &CPU5 {
  119         compatible = "qcom,kryo260";
  120         capacity-dmips-mhz = <640>;
  121         /delete-property/ operating-points-v2;
  122 };
  123 
  124 &CPU6 {
  125         compatible = "qcom,kryo260";
  126         capacity-dmips-mhz = <640>;
  127         /delete-property/ operating-points-v2;
  128 };
  129 
  130 &CPU7 {
  131         compatible = "qcom,kryo260";
  132         capacity-dmips-mhz = <640>;
  133         /delete-property/ operating-points-v2;
  134 };
  135 
  136 &gcc {
  137         compatible = "qcom,gcc-sdm660";
  138 };
  139 
  140 &gpucc {
  141         compatible = "qcom,gpucc-sdm660";
  142 };
  143 
  144 &mdp {
  145         ports {
  146                 port@1 {
  147                         reg = <1>;
  148                         mdp5_intf2_out: endpoint {
  149                                 remote-endpoint = <&dsi1_in>;
  150                         };
  151                 };
  152         };
  153 };
  154 
  155 &mdss {
  156         dsi1: dsi@c996000 {
  157                 compatible = "qcom,mdss-dsi-ctrl";
  158                 reg = <0x0c996000 0x400>;
  159                 reg-names = "dsi_ctrl";
  160 
  161                 /* DSI1 shares the OPP table with DSI0 */
  162                 operating-points-v2 = <&dsi_opp_table>;
  163                 power-domains = <&rpmpd SDM660_VDDCX>;
  164 
  165                 interrupt-parent = <&mdss>;
  166                 interrupts = <5>;
  167 
  168                 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
  169                                         <&mmcc PCLK1_CLK_SRC>;
  170                 assigned-clock-parents = <&dsi1_phy 0>,
  171                                                 <&dsi1_phy 1>;
  172 
  173                 clocks = <&mmcc MDSS_MDP_CLK>,
  174                                 <&mmcc MDSS_BYTE1_CLK>,
  175                                 <&mmcc MDSS_BYTE1_INTF_CLK>,
  176                                 <&mmcc MNOC_AHB_CLK>,
  177                                 <&mmcc MDSS_AHB_CLK>,
  178                                 <&mmcc MDSS_AXI_CLK>,
  179                                 <&mmcc MISC_AHB_CLK>,
  180                                 <&mmcc MDSS_PCLK1_CLK>,
  181                                 <&mmcc MDSS_ESC1_CLK>;
  182                 clock-names = "mdp_core",
  183                                         "byte",
  184                                         "byte_intf",
  185                                         "mnoc",
  186                                         "iface",
  187                                         "bus",
  188                                         "core_mmss",
  189                                         "pixel",
  190                                         "core";
  191 
  192                 phys = <&dsi1_phy>;
  193                 phy-names = "dsi";
  194 
  195                 status = "disabled";
  196 
  197                 ports {
  198                         #address-cells = <1>;
  199                         #size-cells = <0>;
  200 
  201                         port@0 {
  202                                 reg = <0>;
  203                                 dsi1_in: endpoint {
  204                                         remote-endpoint = <&mdp5_intf2_out>;
  205                                 };
  206                         };
  207 
  208                         port@1 {
  209                                 reg = <1>;
  210                                 dsi1_out: endpoint {
  211                                 };
  212                         };
  213                 };
  214         };
  215 
  216         dsi1_phy: dsi-phy@c996400 {
  217                 compatible = "qcom,dsi-phy-14nm-660";
  218                 reg = <0x0c996400 0x100>,
  219                                 <0x0c996500 0x300>,
  220                                 <0x0c996800 0x188>;
  221                 reg-names = "dsi_phy",
  222                                 "dsi_phy_lane",
  223                                 "dsi_pll";
  224 
  225                 #clock-cells = <1>;
  226                 #phy-cells = <0>;
  227 
  228                 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
  229                 clock-names = "iface", "ref";
  230                 status = "disabled";
  231         };
  232 };
  233 
  234 &mmcc {
  235         compatible = "qcom,mmcc-sdm660";
  236         clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
  237                         <&sleep_clk>,
  238                         <&gcc GCC_MMSS_GPLL0_CLK>,
  239                         <&gcc GCC_MMSS_GPLL0_DIV_CLK>,
  240                         <&dsi0_phy 1>,
  241                         <&dsi0_phy 0>,
  242                         <&dsi1_phy 1>,
  243                         <&dsi1_phy 0>,
  244                         <0>,
  245                         <0>;
  246 };
  247 
  248 &tlmm {
  249         compatible = "qcom,sdm660-pinctrl";
  250 };
  251 
  252 &tsens {
  253         #qcom,sensors = <14>;
  254 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/sdm660.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/sdm660.dtsi