sdm845.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * SDM845 SoC device tree source
    4  *
    5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
    6  */
    7 
    8 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
    9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
   10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
   11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
   12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
   13 #include <dt-bindings/clock/qcom,rpmh.h>
   14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
   15 #include <dt-bindings/dma/qcom-gpi.h>
   16 #include <dt-bindings/gpio/gpio.h>
   17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
   18 #include <dt-bindings/interconnect/qcom,sdm845.h>
   19 #include <dt-bindings/interrupt-controller/arm-gic.h>
   20 #include <dt-bindings/phy/phy-qcom-qusb2.h>
   21 #include <dt-bindings/power/qcom-rpmpd.h>
   22 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
   23 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
   24 #include <dt-bindings/soc/qcom,apr.h>
   25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
   26 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
   27 #include <dt-bindings/thermal/thermal.h>
   28 
   29 / {
   30         interrupt-parent = <&intc>;
   31 
   32         #address-cells = <2>;
   33         #size-cells = <2>;
   34 
   35         aliases {
   36                 i2c0 = &i2c0;
   37                 i2c1 = &i2c1;
   38                 i2c2 = &i2c2;
   39                 i2c3 = &i2c3;
   40                 i2c4 = &i2c4;
   41                 i2c5 = &i2c5;
   42                 i2c6 = &i2c6;
   43                 i2c7 = &i2c7;
   44                 i2c8 = &i2c8;
   45                 i2c9 = &i2c9;
   46                 i2c10 = &i2c10;
   47                 i2c11 = &i2c11;
   48                 i2c12 = &i2c12;
   49                 i2c13 = &i2c13;
   50                 i2c14 = &i2c14;
   51                 i2c15 = &i2c15;
   52                 spi0 = &spi0;
   53                 spi1 = &spi1;
   54                 spi2 = &spi2;
   55                 spi3 = &spi3;
   56                 spi4 = &spi4;
   57                 spi5 = &spi5;
   58                 spi6 = &spi6;
   59                 spi7 = &spi7;
   60                 spi8 = &spi8;
   61                 spi9 = &spi9;
   62                 spi10 = &spi10;
   63                 spi11 = &spi11;
   64                 spi12 = &spi12;
   65                 spi13 = &spi13;
   66                 spi14 = &spi14;
   67                 spi15 = &spi15;
   68         };
   69 
   70         chosen { };
   71 
   72         memory@80000000 {
   73                 device_type = "memory";
   74                 /* We expect the bootloader to fill in the size */
   75                 reg = <0 0x80000000 0 0>;
   76         };
   77 
   78         reserved-memory {
   79                 #address-cells = <2>;
   80                 #size-cells = <2>;
   81                 ranges;
   82 
   83                 hyp_mem: hyp-mem@85700000 {
   84                         reg = <0 0x85700000 0 0x600000>;
   85                         no-map;
   86                 };
   87 
   88                 xbl_mem: xbl-mem@85e00000 {
   89                         reg = <0 0x85e00000 0 0x100000>;
   90                         no-map;
   91                 };
   92 
   93                 aop_mem: aop-mem@85fc0000 {
   94                         reg = <0 0x85fc0000 0 0x20000>;
   95                         no-map;
   96                 };
   97 
   98                 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
   99                         compatible = "qcom,cmd-db";
  100                         reg = <0x0 0x85fe0000 0 0x20000>;
  101                         no-map;
  102                 };
  103 
  104                 smem@86000000 {
  105                         compatible = "qcom,smem";
  106                         reg = <0x0 0x86000000 0 0x200000>;
  107                         no-map;
  108                         hwlocks = <&tcsr_mutex 3>;
  109                 };
  110 
  111                 tz_mem: tz@86200000 {
  112                         reg = <0 0x86200000 0 0x2d00000>;
  113                         no-map;
  114                 };
  115 
  116                 rmtfs_mem: rmtfs@88f00000 {
  117                         compatible = "qcom,rmtfs-mem";
  118                         reg = <0 0x88f00000 0 0x200000>;
  119                         no-map;
  120 
  121                         qcom,client-id = <1>;
  122                         qcom,vmid = <15>;
  123                 };
  124 
  125                 qseecom_mem: qseecom@8ab00000 {
  126                         reg = <0 0x8ab00000 0 0x1400000>;
  127                         no-map;
  128                 };
  129 
  130                 camera_mem: camera-mem@8bf00000 {
  131                         reg = <0 0x8bf00000 0 0x500000>;
  132                         no-map;
  133                 };
  134 
  135                 ipa_fw_mem: ipa-fw@8c400000 {
  136                         reg = <0 0x8c400000 0 0x10000>;
  137                         no-map;
  138                 };
  139 
  140                 ipa_gsi_mem: ipa-gsi@8c410000 {
  141                         reg = <0 0x8c410000 0 0x5000>;
  142                         no-map;
  143                 };
  144 
  145                 gpu_mem: gpu@8c415000 {
  146                         reg = <0 0x8c415000 0 0x2000>;
  147                         no-map;
  148                 };
  149 
  150                 adsp_mem: adsp@8c500000 {
  151                         reg = <0 0x8c500000 0 0x1a00000>;
  152                         no-map;
  153                 };
  154 
  155                 wlan_msa_mem: wlan-msa@8df00000 {
  156                         reg = <0 0x8df00000 0 0x100000>;
  157                         no-map;
  158                 };
  159 
  160                 mpss_region: mpss@8e000000 {
  161                         reg = <0 0x8e000000 0 0x7800000>;
  162                         no-map;
  163                 };
  164 
  165                 venus_mem: venus@95800000 {
  166                         reg = <0 0x95800000 0 0x500000>;
  167                         no-map;
  168                 };
  169 
  170                 cdsp_mem: cdsp@95d00000 {
  171                         reg = <0 0x95d00000 0 0x800000>;
  172                         no-map;
  173                 };
  174 
  175                 mba_region: mba@96500000 {
  176                         reg = <0 0x96500000 0 0x200000>;
  177                         no-map;
  178                 };
  179 
  180                 slpi_mem: slpi@96700000 {
  181                         reg = <0 0x96700000 0 0x1400000>;
  182                         no-map;
  183                 };
  184 
  185                 spss_mem: spss@97b00000 {
  186                         reg = <0 0x97b00000 0 0x100000>;
  187                         no-map;
  188                 };
  189         };
  190 
  191         cpus: cpus {
  192                 #address-cells = <2>;
  193                 #size-cells = <0>;
  194 
  195                 CPU0: cpu@0 {
  196                         device_type = "cpu";
  197                         compatible = "qcom,kryo385";
  198                         reg = <0x0 0x0>;
  199                         enable-method = "psci";
  200                         capacity-dmips-mhz = <611>;
  201                         dynamic-power-coefficient = <290>;
  202                         qcom,freq-domain = <&cpufreq_hw 0>;
  203                         operating-points-v2 = <&cpu0_opp_table>;
  204                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  205                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  206                         power-domains = <&CPU_PD0>;
  207                         power-domain-names = "psci";
  208                         #cooling-cells = <2>;
  209                         next-level-cache = <&L2_0>;
  210                         L2_0: l2-cache {
  211                                 compatible = "cache";
  212                                 next-level-cache = <&L3_0>;
  213                                 L3_0: l3-cache {
  214                                       compatible = "cache";
  215                                 };
  216                         };
  217                 };
  218 
  219                 CPU1: cpu@100 {
  220                         device_type = "cpu";
  221                         compatible = "qcom,kryo385";
  222                         reg = <0x0 0x100>;
  223                         enable-method = "psci";
  224                         capacity-dmips-mhz = <611>;
  225                         dynamic-power-coefficient = <290>;
  226                         qcom,freq-domain = <&cpufreq_hw 0>;
  227                         operating-points-v2 = <&cpu0_opp_table>;
  228                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  229                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  230                         power-domains = <&CPU_PD1>;
  231                         power-domain-names = "psci";
  232                         #cooling-cells = <2>;
  233                         next-level-cache = <&L2_100>;
  234                         L2_100: l2-cache {
  235                                 compatible = "cache";
  236                                 next-level-cache = <&L3_0>;
  237                         };
  238                 };
  239 
  240                 CPU2: cpu@200 {
  241                         device_type = "cpu";
  242                         compatible = "qcom,kryo385";
  243                         reg = <0x0 0x200>;
  244                         enable-method = "psci";
  245                         capacity-dmips-mhz = <611>;
  246                         dynamic-power-coefficient = <290>;
  247                         qcom,freq-domain = <&cpufreq_hw 0>;
  248                         operating-points-v2 = <&cpu0_opp_table>;
  249                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  250                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  251                         power-domains = <&CPU_PD2>;
  252                         power-domain-names = "psci";
  253                         #cooling-cells = <2>;
  254                         next-level-cache = <&L2_200>;
  255                         L2_200: l2-cache {
  256                                 compatible = "cache";
  257                                 next-level-cache = <&L3_0>;
  258                         };
  259                 };
  260 
  261                 CPU3: cpu@300 {
  262                         device_type = "cpu";
  263                         compatible = "qcom,kryo385";
  264                         reg = <0x0 0x300>;
  265                         enable-method = "psci";
  266                         capacity-dmips-mhz = <611>;
  267                         dynamic-power-coefficient = <290>;
  268                         qcom,freq-domain = <&cpufreq_hw 0>;
  269                         operating-points-v2 = <&cpu0_opp_table>;
  270                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  271                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  272                         #cooling-cells = <2>;
  273                         power-domains = <&CPU_PD3>;
  274                         power-domain-names = "psci";
  275                         next-level-cache = <&L2_300>;
  276                         L2_300: l2-cache {
  277                                 compatible = "cache";
  278                                 next-level-cache = <&L3_0>;
  279                         };
  280                 };
  281 
  282                 CPU4: cpu@400 {
  283                         device_type = "cpu";
  284                         compatible = "qcom,kryo385";
  285                         reg = <0x0 0x400>;
  286                         enable-method = "psci";
  287                         capacity-dmips-mhz = <1024>;
  288                         dynamic-power-coefficient = <442>;
  289                         qcom,freq-domain = <&cpufreq_hw 1>;
  290                         operating-points-v2 = <&cpu4_opp_table>;
  291                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  292                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  293                         power-domains = <&CPU_PD4>;
  294                         power-domain-names = "psci";
  295                         #cooling-cells = <2>;
  296                         next-level-cache = <&L2_400>;
  297                         L2_400: l2-cache {
  298                                 compatible = "cache";
  299                                 next-level-cache = <&L3_0>;
  300                         };
  301                 };
  302 
  303                 CPU5: cpu@500 {
  304                         device_type = "cpu";
  305                         compatible = "qcom,kryo385";
  306                         reg = <0x0 0x500>;
  307                         enable-method = "psci";
  308                         capacity-dmips-mhz = <1024>;
  309                         dynamic-power-coefficient = <442>;
  310                         qcom,freq-domain = <&cpufreq_hw 1>;
  311                         operating-points-v2 = <&cpu4_opp_table>;
  312                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  313                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  314                         power-domains = <&CPU_PD5>;
  315                         power-domain-names = "psci";
  316                         #cooling-cells = <2>;
  317                         next-level-cache = <&L2_500>;
  318                         L2_500: l2-cache {
  319                                 compatible = "cache";
  320                                 next-level-cache = <&L3_0>;
  321                         };
  322                 };
  323 
  324                 CPU6: cpu@600 {
  325                         device_type = "cpu";
  326                         compatible = "qcom,kryo385";
  327                         reg = <0x0 0x600>;
  328                         enable-method = "psci";
  329                         capacity-dmips-mhz = <1024>;
  330                         dynamic-power-coefficient = <442>;
  331                         qcom,freq-domain = <&cpufreq_hw 1>;
  332                         operating-points-v2 = <&cpu4_opp_table>;
  333                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  334                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  335                         power-domains = <&CPU_PD6>;
  336                         power-domain-names = "psci";
  337                         #cooling-cells = <2>;
  338                         next-level-cache = <&L2_600>;
  339                         L2_600: l2-cache {
  340                                 compatible = "cache";
  341                                 next-level-cache = <&L3_0>;
  342                         };
  343                 };
  344 
  345                 CPU7: cpu@700 {
  346                         device_type = "cpu";
  347                         compatible = "qcom,kryo385";
  348                         reg = <0x0 0x700>;
  349                         enable-method = "psci";
  350                         capacity-dmips-mhz = <1024>;
  351                         dynamic-power-coefficient = <442>;
  352                         qcom,freq-domain = <&cpufreq_hw 1>;
  353                         operating-points-v2 = <&cpu4_opp_table>;
  354                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>,
  355                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
  356                         power-domains = <&CPU_PD7>;
  357                         power-domain-names = "psci";
  358                         #cooling-cells = <2>;
  359                         next-level-cache = <&L2_700>;
  360                         L2_700: l2-cache {
  361                                 compatible = "cache";
  362                                 next-level-cache = <&L3_0>;
  363                         };
  364                 };
  365 
  366                 cpu-map {
  367                         cluster0 {
  368                                 core0 {
  369                                         cpu = <&CPU0>;
  370                                 };
  371 
  372                                 core1 {
  373                                         cpu = <&CPU1>;
  374                                 };
  375 
  376                                 core2 {
  377                                         cpu = <&CPU2>;
  378                                 };
  379 
  380                                 core3 {
  381                                         cpu = <&CPU3>;
  382                                 };
  383 
  384                                 core4 {
  385                                         cpu = <&CPU4>;
  386                                 };
  387 
  388                                 core5 {
  389                                         cpu = <&CPU5>;
  390                                 };
  391 
  392                                 core6 {
  393                                         cpu = <&CPU6>;
  394                                 };
  395 
  396                                 core7 {
  397                                         cpu = <&CPU7>;
  398                                 };
  399                         };
  400                 };
  401 
  402                 cpu_idle_states: idle-states {
  403                         entry-method = "psci";
  404 
  405                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
  406                                 compatible = "arm,idle-state";
  407                                 idle-state-name = "little-rail-power-collapse";
  408                                 arm,psci-suspend-param = <0x40000004>;
  409                                 entry-latency-us = <350>;
  410                                 exit-latency-us = <461>;
  411                                 min-residency-us = <1890>;
  412                                 local-timer-stop;
  413                         };
  414 
  415                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
  416                                 compatible = "arm,idle-state";
  417                                 idle-state-name = "big-rail-power-collapse";
  418                                 arm,psci-suspend-param = <0x40000004>;
  419                                 entry-latency-us = <264>;
  420                                 exit-latency-us = <621>;
  421                                 min-residency-us = <952>;
  422                                 local-timer-stop;
  423                         };
  424                 };
  425 
  426                 domain-idle-states {
  427                         CLUSTER_SLEEP_0: cluster-sleep-0 {
  428                                 compatible = "domain-idle-state";
  429                                 idle-state-name = "cluster-power-collapse";
  430                                 arm,psci-suspend-param = <0x4100c244>;
  431                                 entry-latency-us = <3263>;
  432                                 exit-latency-us = <6562>;
  433                                 min-residency-us = <9987>;
  434                                 local-timer-stop;
  435                         };
  436                 };
  437         };
  438 
  439         cpu0_opp_table: opp-table-cpu0 {
  440                 compatible = "operating-points-v2";
  441                 opp-shared;
  442 
  443                 cpu0_opp1: opp-300000000 {
  444                         opp-hz = /bits/ 64 <300000000>;
  445                         opp-peak-kBps = <800000 4800000>;
  446                 };
  447 
  448                 cpu0_opp2: opp-403200000 {
  449                         opp-hz = /bits/ 64 <403200000>;
  450                         opp-peak-kBps = <800000 4800000>;
  451                 };
  452 
  453                 cpu0_opp3: opp-480000000 {
  454                         opp-hz = /bits/ 64 <480000000>;
  455                         opp-peak-kBps = <800000 6451200>;
  456                 };
  457 
  458                 cpu0_opp4: opp-576000000 {
  459                         opp-hz = /bits/ 64 <576000000>;
  460                         opp-peak-kBps = <800000 6451200>;
  461                 };
  462 
  463                 cpu0_opp5: opp-652800000 {
  464                         opp-hz = /bits/ 64 <652800000>;
  465                         opp-peak-kBps = <800000 7680000>;
  466                 };
  467 
  468                 cpu0_opp6: opp-748800000 {
  469                         opp-hz = /bits/ 64 <748800000>;
  470                         opp-peak-kBps = <1804000 9216000>;
  471                 };
  472 
  473                 cpu0_opp7: opp-825600000 {
  474                         opp-hz = /bits/ 64 <825600000>;
  475                         opp-peak-kBps = <1804000 9216000>;
  476                 };
  477 
  478                 cpu0_opp8: opp-902400000 {
  479                         opp-hz = /bits/ 64 <902400000>;
  480                         opp-peak-kBps = <1804000 10444800>;
  481                 };
  482 
  483                 cpu0_opp9: opp-979200000 {
  484                         opp-hz = /bits/ 64 <979200000>;
  485                         opp-peak-kBps = <1804000 11980800>;
  486                 };
  487 
  488                 cpu0_opp10: opp-1056000000 {
  489                         opp-hz = /bits/ 64 <1056000000>;
  490                         opp-peak-kBps = <1804000 11980800>;
  491                 };
  492 
  493                 cpu0_opp11: opp-1132800000 {
  494                         opp-hz = /bits/ 64 <1132800000>;
  495                         opp-peak-kBps = <2188000 13516800>;
  496                 };
  497 
  498                 cpu0_opp12: opp-1228800000 {
  499                         opp-hz = /bits/ 64 <1228800000>;
  500                         opp-peak-kBps = <2188000 15052800>;
  501                 };
  502 
  503                 cpu0_opp13: opp-1324800000 {
  504                         opp-hz = /bits/ 64 <1324800000>;
  505                         opp-peak-kBps = <2188000 16588800>;
  506                 };
  507 
  508                 cpu0_opp14: opp-1420800000 {
  509                         opp-hz = /bits/ 64 <1420800000>;
  510                         opp-peak-kBps = <3072000 18124800>;
  511                 };
  512 
  513                 cpu0_opp15: opp-1516800000 {
  514                         opp-hz = /bits/ 64 <1516800000>;
  515                         opp-peak-kBps = <3072000 19353600>;
  516                 };
  517 
  518                 cpu0_opp16: opp-1612800000 {
  519                         opp-hz = /bits/ 64 <1612800000>;
  520                         opp-peak-kBps = <4068000 19353600>;
  521                 };
  522 
  523                 cpu0_opp17: opp-1689600000 {
  524                         opp-hz = /bits/ 64 <1689600000>;
  525                         opp-peak-kBps = <4068000 20889600>;
  526                 };
  527 
  528                 cpu0_opp18: opp-1766400000 {
  529                         opp-hz = /bits/ 64 <1766400000>;
  530                         opp-peak-kBps = <4068000 22425600>;
  531                 };
  532         };
  533 
  534         cpu4_opp_table: opp-table-cpu4 {
  535                 compatible = "operating-points-v2";
  536                 opp-shared;
  537 
  538                 cpu4_opp1: opp-300000000 {
  539                         opp-hz = /bits/ 64 <300000000>;
  540                         opp-peak-kBps = <800000 4800000>;
  541                 };
  542 
  543                 cpu4_opp2: opp-403200000 {
  544                         opp-hz = /bits/ 64 <403200000>;
  545                         opp-peak-kBps = <800000 4800000>;
  546                 };
  547 
  548                 cpu4_opp3: opp-480000000 {
  549                         opp-hz = /bits/ 64 <480000000>;
  550                         opp-peak-kBps = <1804000 4800000>;
  551                 };
  552 
  553                 cpu4_opp4: opp-576000000 {
  554                         opp-hz = /bits/ 64 <576000000>;
  555                         opp-peak-kBps = <1804000 4800000>;
  556                 };
  557 
  558                 cpu4_opp5: opp-652800000 {
  559                         opp-hz = /bits/ 64 <652800000>;
  560                         opp-peak-kBps = <1804000 4800000>;
  561                 };
  562 
  563                 cpu4_opp6: opp-748800000 {
  564                         opp-hz = /bits/ 64 <748800000>;
  565                         opp-peak-kBps = <1804000 4800000>;
  566                 };
  567 
  568                 cpu4_opp7: opp-825600000 {
  569                         opp-hz = /bits/ 64 <825600000>;
  570                         opp-peak-kBps = <2188000 9216000>;
  571                 };
  572 
  573                 cpu4_opp8: opp-902400000 {
  574                         opp-hz = /bits/ 64 <902400000>;
  575                         opp-peak-kBps = <2188000 9216000>;
  576                 };
  577 
  578                 cpu4_opp9: opp-979200000 {
  579                         opp-hz = /bits/ 64 <979200000>;
  580                         opp-peak-kBps = <2188000 9216000>;
  581                 };
  582 
  583                 cpu4_opp10: opp-1056000000 {
  584                         opp-hz = /bits/ 64 <1056000000>;
  585                         opp-peak-kBps = <3072000 9216000>;
  586                 };
  587 
  588                 cpu4_opp11: opp-1132800000 {
  589                         opp-hz = /bits/ 64 <1132800000>;
  590                         opp-peak-kBps = <3072000 11980800>;
  591                 };
  592 
  593                 cpu4_opp12: opp-1209600000 {
  594                         opp-hz = /bits/ 64 <1209600000>;
  595                         opp-peak-kBps = <4068000 11980800>;
  596                 };
  597 
  598                 cpu4_opp13: opp-1286400000 {
  599                         opp-hz = /bits/ 64 <1286400000>;
  600                         opp-peak-kBps = <4068000 11980800>;
  601                 };
  602 
  603                 cpu4_opp14: opp-1363200000 {
  604                         opp-hz = /bits/ 64 <1363200000>;
  605                         opp-peak-kBps = <4068000 15052800>;
  606                 };
  607 
  608                 cpu4_opp15: opp-1459200000 {
  609                         opp-hz = /bits/ 64 <1459200000>;
  610                         opp-peak-kBps = <4068000 15052800>;
  611                 };
  612 
  613                 cpu4_opp16: opp-1536000000 {
  614                         opp-hz = /bits/ 64 <1536000000>;
  615                         opp-peak-kBps = <5412000 15052800>;
  616                 };
  617 
  618                 cpu4_opp17: opp-1612800000 {
  619                         opp-hz = /bits/ 64 <1612800000>;
  620                         opp-peak-kBps = <5412000 15052800>;
  621                 };
  622 
  623                 cpu4_opp18: opp-1689600000 {
  624                         opp-hz = /bits/ 64 <1689600000>;
  625                         opp-peak-kBps = <5412000 19353600>;
  626                 };
  627 
  628                 cpu4_opp19: opp-1766400000 {
  629                         opp-hz = /bits/ 64 <1766400000>;
  630                         opp-peak-kBps = <6220000 19353600>;
  631                 };
  632 
  633                 cpu4_opp20: opp-1843200000 {
  634                         opp-hz = /bits/ 64 <1843200000>;
  635                         opp-peak-kBps = <6220000 19353600>;
  636                 };
  637 
  638                 cpu4_opp21: opp-1920000000 {
  639                         opp-hz = /bits/ 64 <1920000000>;
  640                         opp-peak-kBps = <7216000 19353600>;
  641                 };
  642 
  643                 cpu4_opp22: opp-1996800000 {
  644                         opp-hz = /bits/ 64 <1996800000>;
  645                         opp-peak-kBps = <7216000 20889600>;
  646                 };
  647 
  648                 cpu4_opp23: opp-2092800000 {
  649                         opp-hz = /bits/ 64 <2092800000>;
  650                         opp-peak-kBps = <7216000 20889600>;
  651                 };
  652 
  653                 cpu4_opp24: opp-2169600000 {
  654                         opp-hz = /bits/ 64 <2169600000>;
  655                         opp-peak-kBps = <7216000 20889600>;
  656                 };
  657 
  658                 cpu4_opp25: opp-2246400000 {
  659                         opp-hz = /bits/ 64 <2246400000>;
  660                         opp-peak-kBps = <7216000 20889600>;
  661                 };
  662 
  663                 cpu4_opp26: opp-2323200000 {
  664                         opp-hz = /bits/ 64 <2323200000>;
  665                         opp-peak-kBps = <7216000 20889600>;
  666                 };
  667 
  668                 cpu4_opp27: opp-2400000000 {
  669                         opp-hz = /bits/ 64 <2400000000>;
  670                         opp-peak-kBps = <7216000 22425600>;
  671                 };
  672 
  673                 cpu4_opp28: opp-2476800000 {
  674                         opp-hz = /bits/ 64 <2476800000>;
  675                         opp-peak-kBps = <7216000 22425600>;
  676                 };
  677 
  678                 cpu4_opp29: opp-2553600000 {
  679                         opp-hz = /bits/ 64 <2553600000>;
  680                         opp-peak-kBps = <7216000 22425600>;
  681                 };
  682 
  683                 cpu4_opp30: opp-2649600000 {
  684                         opp-hz = /bits/ 64 <2649600000>;
  685                         opp-peak-kBps = <7216000 22425600>;
  686                 };
  687 
  688                 cpu4_opp31: opp-2745600000 {
  689                         opp-hz = /bits/ 64 <2745600000>;
  690                         opp-peak-kBps = <7216000 25497600>;
  691                 };
  692 
  693                 cpu4_opp32: opp-2803200000 {
  694                         opp-hz = /bits/ 64 <2803200000>;
  695                         opp-peak-kBps = <7216000 25497600>;
  696                 };
  697         };
  698 
  699         pmu {
  700                 compatible = "arm,armv8-pmuv3";
  701                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
  702         };
  703 
  704         timer {
  705                 compatible = "arm,armv8-timer";
  706                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
  707                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
  708                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
  709                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
  710         };
  711 
  712         clocks {
  713                 xo_board: xo-board {
  714                         compatible = "fixed-clock";
  715                         #clock-cells = <0>;
  716                         clock-frequency = <38400000>;
  717                         clock-output-names = "xo_board";
  718                 };
  719 
  720                 sleep_clk: sleep-clk {
  721                         compatible = "fixed-clock";
  722                         #clock-cells = <0>;
  723                         clock-frequency = <32764>;
  724                 };
  725         };
  726 
  727         firmware {
  728                 scm {
  729                         compatible = "qcom,scm-sdm845", "qcom,scm";
  730                 };
  731         };
  732 
  733         adsp_pas: remoteproc-adsp {
  734                 compatible = "qcom,sdm845-adsp-pas";
  735 
  736                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
  737                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  738                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  739                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  740                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  741                 interrupt-names = "wdog", "fatal", "ready",
  742                                   "handover", "stop-ack";
  743 
  744                 clocks = <&rpmhcc RPMH_CXO_CLK>;
  745                 clock-names = "xo";
  746 
  747                 memory-region = <&adsp_mem>;
  748 
  749                 qcom,qmp = <&aoss_qmp>;
  750 
  751                 qcom,smem-states = <&adsp_smp2p_out 0>;
  752                 qcom,smem-state-names = "stop";
  753 
  754                 status = "disabled";
  755 
  756                 glink-edge {
  757                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
  758                         label = "lpass";
  759                         qcom,remote-pid = <2>;
  760                         mboxes = <&apss_shared 8>;
  761 
  762                         apr {
  763                                 compatible = "qcom,apr-v2";
  764                                 qcom,glink-channels = "apr_audio_svc";
  765                                 qcom,domain = <APR_DOMAIN_ADSP>;
  766                                 #address-cells = <1>;
  767                                 #size-cells = <0>;
  768                                 qcom,intents = <512 20>;
  769 
  770                                 apr-service@3 {
  771                                         reg = <APR_SVC_ADSP_CORE>;
  772                                         compatible = "qcom,q6core";
  773                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
  774                                 };
  775 
  776                                 q6afe: apr-service@4 {
  777                                         compatible = "qcom,q6afe";
  778                                         reg = <APR_SVC_AFE>;
  779                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
  780                                         q6afedai: dais {
  781                                                 compatible = "qcom,q6afe-dais";
  782                                                 #address-cells = <1>;
  783                                                 #size-cells = <0>;
  784                                                 #sound-dai-cells = <1>;
  785                                         };
  786                                 };
  787 
  788                                 q6asm: apr-service@7 {
  789                                         compatible = "qcom,q6asm";
  790                                         reg = <APR_SVC_ASM>;
  791                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
  792                                         q6asmdai: dais {
  793                                                 compatible = "qcom,q6asm-dais";
  794                                                 #address-cells = <1>;
  795                                                 #size-cells = <0>;
  796                                                 #sound-dai-cells = <1>;
  797                                                 iommus = <&apps_smmu 0x1821 0x0>;
  798                                         };
  799                                 };
  800 
  801                                 q6adm: apr-service@8 {
  802                                         compatible = "qcom,q6adm";
  803                                         reg = <APR_SVC_ADM>;
  804                                         qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd";
  805                                         q6routing: routing {
  806                                                 compatible = "qcom,q6adm-routing";
  807                                                 #sound-dai-cells = <0>;
  808                                         };
  809                                 };
  810                         };
  811 
  812                         fastrpc {
  813                                 compatible = "qcom,fastrpc";
  814                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
  815                                 label = "adsp";
  816                                 qcom,non-secure-domain;
  817                                 #address-cells = <1>;
  818                                 #size-cells = <0>;
  819 
  820                                 compute-cb@3 {
  821                                         compatible = "qcom,fastrpc-compute-cb";
  822                                         reg = <3>;
  823                                         iommus = <&apps_smmu 0x1823 0x0>;
  824                                 };
  825 
  826                                 compute-cb@4 {
  827                                         compatible = "qcom,fastrpc-compute-cb";
  828                                         reg = <4>;
  829                                         iommus = <&apps_smmu 0x1824 0x0>;
  830                                 };
  831                         };
  832                 };
  833         };
  834 
  835         cdsp_pas: remoteproc-cdsp {
  836                 compatible = "qcom,sdm845-cdsp-pas";
  837 
  838                 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
  839                                       <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  840                                       <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  841                                       <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  842                                       <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  843                 interrupt-names = "wdog", "fatal", "ready",
  844                                   "handover", "stop-ack";
  845 
  846                 clocks = <&rpmhcc RPMH_CXO_CLK>;
  847                 clock-names = "xo";
  848 
  849                 memory-region = <&cdsp_mem>;
  850 
  851                 qcom,qmp = <&aoss_qmp>;
  852 
  853                 qcom,smem-states = <&cdsp_smp2p_out 0>;
  854                 qcom,smem-state-names = "stop";
  855 
  856                 status = "disabled";
  857 
  858                 glink-edge {
  859                         interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
  860                         label = "turing";
  861                         qcom,remote-pid = <5>;
  862                         mboxes = <&apss_shared 4>;
  863                         fastrpc {
  864                                 compatible = "qcom,fastrpc";
  865                                 qcom,glink-channels = "fastrpcglink-apps-dsp";
  866                                 label = "cdsp";
  867                                 qcom,non-secure-domain;
  868                                 #address-cells = <1>;
  869                                 #size-cells = <0>;
  870 
  871                                 compute-cb@1 {
  872                                         compatible = "qcom,fastrpc-compute-cb";
  873                                         reg = <1>;
  874                                         iommus = <&apps_smmu 0x1401 0x30>;
  875                                 };
  876 
  877                                 compute-cb@2 {
  878                                         compatible = "qcom,fastrpc-compute-cb";
  879                                         reg = <2>;
  880                                         iommus = <&apps_smmu 0x1402 0x30>;
  881                                 };
  882 
  883                                 compute-cb@3 {
  884                                         compatible = "qcom,fastrpc-compute-cb";
  885                                         reg = <3>;
  886                                         iommus = <&apps_smmu 0x1403 0x30>;
  887                                 };
  888 
  889                                 compute-cb@4 {
  890                                         compatible = "qcom,fastrpc-compute-cb";
  891                                         reg = <4>;
  892                                         iommus = <&apps_smmu 0x1404 0x30>;
  893                                 };
  894 
  895                                 compute-cb@5 {
  896                                         compatible = "qcom,fastrpc-compute-cb";
  897                                         reg = <5>;
  898                                         iommus = <&apps_smmu 0x1405 0x30>;
  899                                 };
  900 
  901                                 compute-cb@6 {
  902                                         compatible = "qcom,fastrpc-compute-cb";
  903                                         reg = <6>;
  904                                         iommus = <&apps_smmu 0x1406 0x30>;
  905                                 };
  906 
  907                                 compute-cb@7 {
  908                                         compatible = "qcom,fastrpc-compute-cb";
  909                                         reg = <7>;
  910                                         iommus = <&apps_smmu 0x1407 0x30>;
  911                                 };
  912 
  913                                 compute-cb@8 {
  914                                         compatible = "qcom,fastrpc-compute-cb";
  915                                         reg = <8>;
  916                                         iommus = <&apps_smmu 0x1408 0x30>;
  917                                 };
  918                         };
  919                 };
  920         };
  921 
  922         tcsr_mutex: hwlock {
  923                 compatible = "qcom,tcsr-mutex";
  924                 syscon = <&tcsr_mutex_regs 0 0x1000>;
  925                 #hwlock-cells = <1>;
  926         };
  927 
  928         smp2p-cdsp {
  929                 compatible = "qcom,smp2p";
  930                 qcom,smem = <94>, <432>;
  931 
  932                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
  933 
  934                 mboxes = <&apss_shared 6>;
  935 
  936                 qcom,local-pid = <0>;
  937                 qcom,remote-pid = <5>;
  938 
  939                 cdsp_smp2p_out: master-kernel {
  940                         qcom,entry-name = "master-kernel";
  941                         #qcom,smem-state-cells = <1>;
  942                 };
  943 
  944                 cdsp_smp2p_in: slave-kernel {
  945                         qcom,entry-name = "slave-kernel";
  946 
  947                         interrupt-controller;
  948                         #interrupt-cells = <2>;
  949                 };
  950         };
  951 
  952         smp2p-lpass {
  953                 compatible = "qcom,smp2p";
  954                 qcom,smem = <443>, <429>;
  955 
  956                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
  957 
  958                 mboxes = <&apss_shared 10>;
  959 
  960                 qcom,local-pid = <0>;
  961                 qcom,remote-pid = <2>;
  962 
  963                 adsp_smp2p_out: master-kernel {
  964                         qcom,entry-name = "master-kernel";
  965                         #qcom,smem-state-cells = <1>;
  966                 };
  967 
  968                 adsp_smp2p_in: slave-kernel {
  969                         qcom,entry-name = "slave-kernel";
  970 
  971                         interrupt-controller;
  972                         #interrupt-cells = <2>;
  973                 };
  974         };
  975 
  976         smp2p-mpss {
  977                 compatible = "qcom,smp2p";
  978                 qcom,smem = <435>, <428>;
  979                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
  980                 mboxes = <&apss_shared 14>;
  981                 qcom,local-pid = <0>;
  982                 qcom,remote-pid = <1>;
  983 
  984                 modem_smp2p_out: master-kernel {
  985                         qcom,entry-name = "master-kernel";
  986                         #qcom,smem-state-cells = <1>;
  987                 };
  988 
  989                 modem_smp2p_in: slave-kernel {
  990                         qcom,entry-name = "slave-kernel";
  991                         interrupt-controller;
  992                         #interrupt-cells = <2>;
  993                 };
  994 
  995                 ipa_smp2p_out: ipa-ap-to-modem {
  996                         qcom,entry-name = "ipa";
  997                         #qcom,smem-state-cells = <1>;
  998                 };
  999 
 1000                 ipa_smp2p_in: ipa-modem-to-ap {
 1001                         qcom,entry-name = "ipa";
 1002                         interrupt-controller;
 1003                         #interrupt-cells = <2>;
 1004                 };
 1005         };
 1006 
 1007         smp2p-slpi {
 1008                 compatible = "qcom,smp2p";
 1009                 qcom,smem = <481>, <430>;
 1010                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 1011                 mboxes = <&apss_shared 26>;
 1012                 qcom,local-pid = <0>;
 1013                 qcom,remote-pid = <3>;
 1014 
 1015                 slpi_smp2p_out: master-kernel {
 1016                         qcom,entry-name = "master-kernel";
 1017                         #qcom,smem-state-cells = <1>;
 1018                 };
 1019 
 1020                 slpi_smp2p_in: slave-kernel {
 1021                         qcom,entry-name = "slave-kernel";
 1022                         interrupt-controller;
 1023                         #interrupt-cells = <2>;
 1024                 };
 1025         };
 1026 
 1027         psci: psci {
 1028                 compatible = "arm,psci-1.0";
 1029                 method = "smc";
 1030 
 1031                 CPU_PD0: power-domain-cpu0 {
 1032                         #power-domain-cells = <0>;
 1033                         power-domains = <&CLUSTER_PD>;
 1034                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 1035                 };
 1036 
 1037                 CPU_PD1: power-domain-cpu1 {
 1038                         #power-domain-cells = <0>;
 1039                         power-domains = <&CLUSTER_PD>;
 1040                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 1041                 };
 1042 
 1043                 CPU_PD2: power-domain-cpu2 {
 1044                         #power-domain-cells = <0>;
 1045                         power-domains = <&CLUSTER_PD>;
 1046                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 1047                 };
 1048 
 1049                 CPU_PD3: power-domain-cpu3 {
 1050                         #power-domain-cells = <0>;
 1051                         power-domains = <&CLUSTER_PD>;
 1052                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 1053                 };
 1054 
 1055                 CPU_PD4: power-domain-cpu4 {
 1056                         #power-domain-cells = <0>;
 1057                         power-domains = <&CLUSTER_PD>;
 1058                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 1059                 };
 1060 
 1061                 CPU_PD5: power-domain-cpu5 {
 1062                         #power-domain-cells = <0>;
 1063                         power-domains = <&CLUSTER_PD>;
 1064                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 1065                 };
 1066 
 1067                 CPU_PD6: power-domain-cpu6 {
 1068                         #power-domain-cells = <0>;
 1069                         power-domains = <&CLUSTER_PD>;
 1070                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 1071                 };
 1072 
 1073                 CPU_PD7: power-domain-cpu7 {
 1074                         #power-domain-cells = <0>;
 1075                         power-domains = <&CLUSTER_PD>;
 1076                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 1077                 };
 1078 
 1079                 CLUSTER_PD: power-domain-cluster {
 1080                         #power-domain-cells = <0>;
 1081                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 1082                 };
 1083         };
 1084 
 1085         soc: soc@0 {
 1086                 #address-cells = <2>;
 1087                 #size-cells = <2>;
 1088                 ranges = <0 0 0 0 0x10 0>;
 1089                 dma-ranges = <0 0 0 0 0x10 0>;
 1090                 compatible = "simple-bus";
 1091 
 1092                 gcc: clock-controller@100000 {
 1093                         compatible = "qcom,gcc-sdm845";
 1094                         reg = <0 0x00100000 0 0x1f0000>;
 1095                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 1096                                  <&rpmhcc RPMH_CXO_CLK_A>,
 1097                                  <&sleep_clk>,
 1098                                  <&pcie0_lane>,
 1099                                  <&pcie1_lane>;
 1100                         clock-names = "bi_tcxo",
 1101                                       "bi_tcxo_ao",
 1102                                       "sleep_clk",
 1103                                       "pcie_0_pipe_clk",
 1104                                       "pcie_1_pipe_clk";
 1105                         #clock-cells = <1>;
 1106                         #reset-cells = <1>;
 1107                         #power-domain-cells = <1>;
 1108                 };
 1109 
 1110                 qfprom@784000 {
 1111                         compatible = "qcom,sdm845-qfprom", "qcom,qfprom";
 1112                         reg = <0 0x00784000 0 0x8ff>;
 1113                         #address-cells = <1>;
 1114                         #size-cells = <1>;
 1115 
 1116                         qusb2p_hstx_trim: hstx-trim-primary@1eb {
 1117                                 reg = <0x1eb 0x1>;
 1118                                 bits = <1 4>;
 1119                         };
 1120 
 1121                         qusb2s_hstx_trim: hstx-trim-secondary@1eb {
 1122                                 reg = <0x1eb 0x2>;
 1123                                 bits = <6 4>;
 1124                         };
 1125                 };
 1126 
 1127                 rng: rng@793000 {
 1128                         compatible = "qcom,prng-ee";
 1129                         reg = <0 0x00793000 0 0x1000>;
 1130                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 1131                         clock-names = "core";
 1132                 };
 1133 
 1134                 qup_opp_table: opp-table-qup {
 1135                         compatible = "operating-points-v2";
 1136 
 1137                         opp-50000000 {
 1138                                 opp-hz = /bits/ 64 <50000000>;
 1139                                 required-opps = <&rpmhpd_opp_min_svs>;
 1140                         };
 1141 
 1142                         opp-75000000 {
 1143                                 opp-hz = /bits/ 64 <75000000>;
 1144                                 required-opps = <&rpmhpd_opp_low_svs>;
 1145                         };
 1146 
 1147                         opp-100000000 {
 1148                                 opp-hz = /bits/ 64 <100000000>;
 1149                                 required-opps = <&rpmhpd_opp_svs>;
 1150                         };
 1151 
 1152                         opp-128000000 {
 1153                                 opp-hz = /bits/ 64 <128000000>;
 1154                                 required-opps = <&rpmhpd_opp_nom>;
 1155                         };
 1156                 };
 1157 
 1158                 gpi_dma0: dma-controller@800000 {
 1159                         #dma-cells = <3>;
 1160                         compatible = "qcom,sdm845-gpi-dma";
 1161                         reg = <0 0x00800000 0 0x60000>;
 1162                         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
 1163                                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 1164                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 1165                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 1166                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
 1167                                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 1168                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 1169                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 1170                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 1171                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 1172                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 1173                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 1174                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 1175                         dma-channels = <13>;
 1176                         dma-channel-mask = <0xfa>;
 1177                         iommus = <&apps_smmu 0x0016 0x0>;
 1178                         status = "disabled";
 1179                 };
 1180 
 1181                 qupv3_id_0: geniqup@8c0000 {
 1182                         compatible = "qcom,geni-se-qup";
 1183                         reg = <0 0x008c0000 0 0x6000>;
 1184                         clock-names = "m-ahb", "s-ahb";
 1185                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 1186                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 1187                         iommus = <&apps_smmu 0x3 0x0>;
 1188                         #address-cells = <2>;
 1189                         #size-cells = <2>;
 1190                         ranges;
 1191                         interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>;
 1192                         interconnect-names = "qup-core";
 1193                         status = "disabled";
 1194 
 1195                         i2c0: i2c@880000 {
 1196                                 compatible = "qcom,geni-i2c";
 1197                                 reg = <0 0x00880000 0 0x4000>;
 1198                                 clock-names = "se";
 1199                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 1200                                 pinctrl-names = "default";
 1201                                 pinctrl-0 = <&qup_i2c0_default>;
 1202                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 1203                                 #address-cells = <1>;
 1204                                 #size-cells = <0>;
 1205                                 power-domains = <&rpmhpd SDM845_CX>;
 1206                                 operating-points-v2 = <&qup_opp_table>;
 1207                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1208                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1209                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1210                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1211                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
 1212                                        <&gpi_dma0 1 0 QCOM_GPI_I2C>;
 1213                                 dma-names = "tx", "rx";
 1214                                 status = "disabled";
 1215                         };
 1216 
 1217                         spi0: spi@880000 {
 1218                                 compatible = "qcom,geni-spi";
 1219                                 reg = <0 0x00880000 0 0x4000>;
 1220                                 clock-names = "se";
 1221                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 1222                                 pinctrl-names = "default";
 1223                                 pinctrl-0 = <&qup_spi0_default>;
 1224                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 1225                                 #address-cells = <1>;
 1226                                 #size-cells = <0>;
 1227                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1228                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1229                                 interconnect-names = "qup-core", "qup-config";
 1230                                 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
 1231                                        <&gpi_dma0 1 0 QCOM_GPI_SPI>;
 1232                                 dma-names = "tx", "rx";
 1233                                 status = "disabled";
 1234                         };
 1235 
 1236                         uart0: serial@880000 {
 1237                                 compatible = "qcom,geni-uart";
 1238                                 reg = <0 0x00880000 0 0x4000>;
 1239                                 clock-names = "se";
 1240                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 1241                                 pinctrl-names = "default";
 1242                                 pinctrl-0 = <&qup_uart0_default>;
 1243                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 1244                                 power-domains = <&rpmhpd SDM845_CX>;
 1245                                 operating-points-v2 = <&qup_opp_table>;
 1246                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1247                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1248                                 interconnect-names = "qup-core", "qup-config";
 1249                                 status = "disabled";
 1250                         };
 1251 
 1252                         i2c1: i2c@884000 {
 1253                                 compatible = "qcom,geni-i2c";
 1254                                 reg = <0 0x00884000 0 0x4000>;
 1255                                 clock-names = "se";
 1256                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 1257                                 pinctrl-names = "default";
 1258                                 pinctrl-0 = <&qup_i2c1_default>;
 1259                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 1260                                 #address-cells = <1>;
 1261                                 #size-cells = <0>;
 1262                                 power-domains = <&rpmhpd SDM845_CX>;
 1263                                 operating-points-v2 = <&qup_opp_table>;
 1264                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1265                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1266                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1267                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1268                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
 1269                                        <&gpi_dma0 1 1 QCOM_GPI_I2C>;
 1270                                 dma-names = "tx", "rx";
 1271                                 status = "disabled";
 1272                         };
 1273 
 1274                         spi1: spi@884000 {
 1275                                 compatible = "qcom,geni-spi";
 1276                                 reg = <0 0x00884000 0 0x4000>;
 1277                                 clock-names = "se";
 1278                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 1279                                 pinctrl-names = "default";
 1280                                 pinctrl-0 = <&qup_spi1_default>;
 1281                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 1282                                 #address-cells = <1>;
 1283                                 #size-cells = <0>;
 1284                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1285                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1286                                 interconnect-names = "qup-core", "qup-config";
 1287                                 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
 1288                                        <&gpi_dma0 1 1 QCOM_GPI_SPI>;
 1289                                 dma-names = "tx", "rx";
 1290                                 status = "disabled";
 1291                         };
 1292 
 1293                         uart1: serial@884000 {
 1294                                 compatible = "qcom,geni-uart";
 1295                                 reg = <0 0x00884000 0 0x4000>;
 1296                                 clock-names = "se";
 1297                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 1298                                 pinctrl-names = "default";
 1299                                 pinctrl-0 = <&qup_uart1_default>;
 1300                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 1301                                 power-domains = <&rpmhpd SDM845_CX>;
 1302                                 operating-points-v2 = <&qup_opp_table>;
 1303                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1304                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1305                                 interconnect-names = "qup-core", "qup-config";
 1306                                 status = "disabled";
 1307                         };
 1308 
 1309                         i2c2: i2c@888000 {
 1310                                 compatible = "qcom,geni-i2c";
 1311                                 reg = <0 0x00888000 0 0x4000>;
 1312                                 clock-names = "se";
 1313                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 1314                                 pinctrl-names = "default";
 1315                                 pinctrl-0 = <&qup_i2c2_default>;
 1316                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 1317                                 #address-cells = <1>;
 1318                                 #size-cells = <0>;
 1319                                 power-domains = <&rpmhpd SDM845_CX>;
 1320                                 operating-points-v2 = <&qup_opp_table>;
 1321                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1322                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1323                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1324                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1325                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
 1326                                        <&gpi_dma0 1 2 QCOM_GPI_I2C>;
 1327                                 dma-names = "tx", "rx";
 1328                                 status = "disabled";
 1329                         };
 1330 
 1331                         spi2: spi@888000 {
 1332                                 compatible = "qcom,geni-spi";
 1333                                 reg = <0 0x00888000 0 0x4000>;
 1334                                 clock-names = "se";
 1335                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 1336                                 pinctrl-names = "default";
 1337                                 pinctrl-0 = <&qup_spi2_default>;
 1338                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 1339                                 #address-cells = <1>;
 1340                                 #size-cells = <0>;
 1341                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1342                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1343                                 interconnect-names = "qup-core", "qup-config";
 1344                                 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
 1345                                        <&gpi_dma0 1 2 QCOM_GPI_SPI>;
 1346                                 dma-names = "tx", "rx";
 1347                                 status = "disabled";
 1348                         };
 1349 
 1350                         uart2: serial@888000 {
 1351                                 compatible = "qcom,geni-uart";
 1352                                 reg = <0 0x00888000 0 0x4000>;
 1353                                 clock-names = "se";
 1354                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 1355                                 pinctrl-names = "default";
 1356                                 pinctrl-0 = <&qup_uart2_default>;
 1357                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 1358                                 power-domains = <&rpmhpd SDM845_CX>;
 1359                                 operating-points-v2 = <&qup_opp_table>;
 1360                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1361                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1362                                 interconnect-names = "qup-core", "qup-config";
 1363                                 status = "disabled";
 1364                         };
 1365 
 1366                         i2c3: i2c@88c000 {
 1367                                 compatible = "qcom,geni-i2c";
 1368                                 reg = <0 0x0088c000 0 0x4000>;
 1369                                 clock-names = "se";
 1370                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 1371                                 pinctrl-names = "default";
 1372                                 pinctrl-0 = <&qup_i2c3_default>;
 1373                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 1374                                 #address-cells = <1>;
 1375                                 #size-cells = <0>;
 1376                                 power-domains = <&rpmhpd SDM845_CX>;
 1377                                 operating-points-v2 = <&qup_opp_table>;
 1378                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1379                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1380                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1381                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1382                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
 1383                                        <&gpi_dma0 1 3 QCOM_GPI_I2C>;
 1384                                 dma-names = "tx", "rx";
 1385                                 status = "disabled";
 1386                         };
 1387 
 1388                         spi3: spi@88c000 {
 1389                                 compatible = "qcom,geni-spi";
 1390                                 reg = <0 0x0088c000 0 0x4000>;
 1391                                 clock-names = "se";
 1392                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 1393                                 pinctrl-names = "default";
 1394                                 pinctrl-0 = <&qup_spi3_default>;
 1395                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 1396                                 #address-cells = <1>;
 1397                                 #size-cells = <0>;
 1398                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1399                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1400                                 interconnect-names = "qup-core", "qup-config";
 1401                                 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
 1402                                        <&gpi_dma0 1 3 QCOM_GPI_SPI>;
 1403                                 dma-names = "tx", "rx";
 1404                                 status = "disabled";
 1405                         };
 1406 
 1407                         uart3: serial@88c000 {
 1408                                 compatible = "qcom,geni-uart";
 1409                                 reg = <0 0x0088c000 0 0x4000>;
 1410                                 clock-names = "se";
 1411                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 1412                                 pinctrl-names = "default";
 1413                                 pinctrl-0 = <&qup_uart3_default>;
 1414                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 1415                                 power-domains = <&rpmhpd SDM845_CX>;
 1416                                 operating-points-v2 = <&qup_opp_table>;
 1417                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1418                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1419                                 interconnect-names = "qup-core", "qup-config";
 1420                                 status = "disabled";
 1421                         };
 1422 
 1423                         i2c4: i2c@890000 {
 1424                                 compatible = "qcom,geni-i2c";
 1425                                 reg = <0 0x00890000 0 0x4000>;
 1426                                 clock-names = "se";
 1427                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 1428                                 pinctrl-names = "default";
 1429                                 pinctrl-0 = <&qup_i2c4_default>;
 1430                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 1431                                 #address-cells = <1>;
 1432                                 #size-cells = <0>;
 1433                                 power-domains = <&rpmhpd SDM845_CX>;
 1434                                 operating-points-v2 = <&qup_opp_table>;
 1435                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1436                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1437                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1438                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1439                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
 1440                                        <&gpi_dma0 1 4 QCOM_GPI_I2C>;
 1441                                 dma-names = "tx", "rx";
 1442                                 status = "disabled";
 1443                         };
 1444 
 1445                         spi4: spi@890000 {
 1446                                 compatible = "qcom,geni-spi";
 1447                                 reg = <0 0x00890000 0 0x4000>;
 1448                                 clock-names = "se";
 1449                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 1450                                 pinctrl-names = "default";
 1451                                 pinctrl-0 = <&qup_spi4_default>;
 1452                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 1453                                 #address-cells = <1>;
 1454                                 #size-cells = <0>;
 1455                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1456                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1457                                 interconnect-names = "qup-core", "qup-config";
 1458                                 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
 1459                                        <&gpi_dma0 1 4 QCOM_GPI_SPI>;
 1460                                 dma-names = "tx", "rx";
 1461                                 status = "disabled";
 1462                         };
 1463 
 1464                         uart4: serial@890000 {
 1465                                 compatible = "qcom,geni-uart";
 1466                                 reg = <0 0x00890000 0 0x4000>;
 1467                                 clock-names = "se";
 1468                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 1469                                 pinctrl-names = "default";
 1470                                 pinctrl-0 = <&qup_uart4_default>;
 1471                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 1472                                 power-domains = <&rpmhpd SDM845_CX>;
 1473                                 operating-points-v2 = <&qup_opp_table>;
 1474                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1475                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1476                                 interconnect-names = "qup-core", "qup-config";
 1477                                 status = "disabled";
 1478                         };
 1479 
 1480                         i2c5: i2c@894000 {
 1481                                 compatible = "qcom,geni-i2c";
 1482                                 reg = <0 0x00894000 0 0x4000>;
 1483                                 clock-names = "se";
 1484                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 1485                                 pinctrl-names = "default";
 1486                                 pinctrl-0 = <&qup_i2c5_default>;
 1487                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 1488                                 #address-cells = <1>;
 1489                                 #size-cells = <0>;
 1490                                 power-domains = <&rpmhpd SDM845_CX>;
 1491                                 operating-points-v2 = <&qup_opp_table>;
 1492                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1493                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1494                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1495                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1496                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
 1497                                        <&gpi_dma0 1 5 QCOM_GPI_I2C>;
 1498                                 dma-names = "tx", "rx";
 1499                                 status = "disabled";
 1500                         };
 1501 
 1502                         spi5: spi@894000 {
 1503                                 compatible = "qcom,geni-spi";
 1504                                 reg = <0 0x00894000 0 0x4000>;
 1505                                 clock-names = "se";
 1506                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 1507                                 pinctrl-names = "default";
 1508                                 pinctrl-0 = <&qup_spi5_default>;
 1509                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 1510                                 #address-cells = <1>;
 1511                                 #size-cells = <0>;
 1512                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1513                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1514                                 interconnect-names = "qup-core", "qup-config";
 1515                                 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
 1516                                        <&gpi_dma0 1 5 QCOM_GPI_SPI>;
 1517                                 dma-names = "tx", "rx";
 1518                                 status = "disabled";
 1519                         };
 1520 
 1521                         uart5: serial@894000 {
 1522                                 compatible = "qcom,geni-uart";
 1523                                 reg = <0 0x00894000 0 0x4000>;
 1524                                 clock-names = "se";
 1525                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 1526                                 pinctrl-names = "default";
 1527                                 pinctrl-0 = <&qup_uart5_default>;
 1528                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
 1529                                 power-domains = <&rpmhpd SDM845_CX>;
 1530                                 operating-points-v2 = <&qup_opp_table>;
 1531                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1532                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1533                                 interconnect-names = "qup-core", "qup-config";
 1534                                 status = "disabled";
 1535                         };
 1536 
 1537                         i2c6: i2c@898000 {
 1538                                 compatible = "qcom,geni-i2c";
 1539                                 reg = <0 0x00898000 0 0x4000>;
 1540                                 clock-names = "se";
 1541                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 1542                                 pinctrl-names = "default";
 1543                                 pinctrl-0 = <&qup_i2c6_default>;
 1544                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 1545                                 #address-cells = <1>;
 1546                                 #size-cells = <0>;
 1547                                 power-domains = <&rpmhpd SDM845_CX>;
 1548                                 operating-points-v2 = <&qup_opp_table>;
 1549                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1550                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>,
 1551                                                 <&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>;
 1552                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1553                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
 1554                                        <&gpi_dma0 1 6 QCOM_GPI_I2C>;
 1555                                 dma-names = "tx", "rx";
 1556                                 status = "disabled";
 1557                         };
 1558 
 1559                         spi6: spi@898000 {
 1560                                 compatible = "qcom,geni-spi";
 1561                                 reg = <0 0x00898000 0 0x4000>;
 1562                                 clock-names = "se";
 1563                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 1564                                 pinctrl-names = "default";
 1565                                 pinctrl-0 = <&qup_spi6_default>;
 1566                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 1567                                 #address-cells = <1>;
 1568                                 #size-cells = <0>;
 1569                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1570                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1571                                 interconnect-names = "qup-core", "qup-config";
 1572                                 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
 1573                                        <&gpi_dma0 1 6 QCOM_GPI_SPI>;
 1574                                 dma-names = "tx", "rx";
 1575                                 status = "disabled";
 1576                         };
 1577 
 1578                         uart6: serial@898000 {
 1579                                 compatible = "qcom,geni-uart";
 1580                                 reg = <0 0x00898000 0 0x4000>;
 1581                                 clock-names = "se";
 1582                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 1583                                 pinctrl-names = "default";
 1584                                 pinctrl-0 = <&qup_uart6_default>;
 1585                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
 1586                                 power-domains = <&rpmhpd SDM845_CX>;
 1587                                 operating-points-v2 = <&qup_opp_table>;
 1588                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1589                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1590                                 interconnect-names = "qup-core", "qup-config";
 1591                                 status = "disabled";
 1592                         };
 1593 
 1594                         i2c7: i2c@89c000 {
 1595                                 compatible = "qcom,geni-i2c";
 1596                                 reg = <0 0x0089c000 0 0x4000>;
 1597                                 clock-names = "se";
 1598                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 1599                                 pinctrl-names = "default";
 1600                                 pinctrl-0 = <&qup_i2c7_default>;
 1601                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 1602                                 #address-cells = <1>;
 1603                                 #size-cells = <0>;
 1604                                 power-domains = <&rpmhpd SDM845_CX>;
 1605                                 operating-points-v2 = <&qup_opp_table>;
 1606                                 status = "disabled";
 1607                         };
 1608 
 1609                         spi7: spi@89c000 {
 1610                                 compatible = "qcom,geni-spi";
 1611                                 reg = <0 0x0089c000 0 0x4000>;
 1612                                 clock-names = "se";
 1613                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 1614                                 pinctrl-names = "default";
 1615                                 pinctrl-0 = <&qup_spi7_default>;
 1616                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 1617                                 #address-cells = <1>;
 1618                                 #size-cells = <0>;
 1619                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1620                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1621                                 interconnect-names = "qup-core", "qup-config";
 1622                                 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
 1623                                        <&gpi_dma0 1 7 QCOM_GPI_SPI>;
 1624                                 dma-names = "tx", "rx";
 1625                                 status = "disabled";
 1626                         };
 1627 
 1628                         uart7: serial@89c000 {
 1629                                 compatible = "qcom,geni-uart";
 1630                                 reg = <0 0x0089c000 0 0x4000>;
 1631                                 clock-names = "se";
 1632                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 1633                                 pinctrl-names = "default";
 1634                                 pinctrl-0 = <&qup_uart7_default>;
 1635                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
 1636                                 power-domains = <&rpmhpd SDM845_CX>;
 1637                                 operating-points-v2 = <&qup_opp_table>;
 1638                                 interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
 1639                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
 1640                                 interconnect-names = "qup-core", "qup-config";
 1641                                 status = "disabled";
 1642                         };
 1643                 };
 1644 
 1645                 gpi_dma1: dma-controller@0xa00000 {
 1646                         #dma-cells = <3>;
 1647                         compatible = "qcom,sdm845-gpi-dma";
 1648                         reg = <0 0x00a00000 0 0x60000>;
 1649                         interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 1650                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 1651                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 1652                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 1653                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 1654                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 1655                                      <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
 1656                                      <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
 1657                                      <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
 1658                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
 1659                                      <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
 1660                                      <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
 1661                                      <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 1662                         dma-channels = <13>;
 1663                         dma-channel-mask = <0xfa>;
 1664                         iommus = <&apps_smmu 0x06d6 0x0>;
 1665                         status = "disabled";
 1666                 };
 1667 
 1668                 qupv3_id_1: geniqup@ac0000 {
 1669                         compatible = "qcom,geni-se-qup";
 1670                         reg = <0 0x00ac0000 0 0x6000>;
 1671                         clock-names = "m-ahb", "s-ahb";
 1672                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 1673                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 1674                         iommus = <&apps_smmu 0x6c3 0x0>;
 1675                         #address-cells = <2>;
 1676                         #size-cells = <2>;
 1677                         ranges;
 1678                         interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>;
 1679                         interconnect-names = "qup-core";
 1680                         status = "disabled";
 1681 
 1682                         i2c8: i2c@a80000 {
 1683                                 compatible = "qcom,geni-i2c";
 1684                                 reg = <0 0x00a80000 0 0x4000>;
 1685                                 clock-names = "se";
 1686                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 1687                                 pinctrl-names = "default";
 1688                                 pinctrl-0 = <&qup_i2c8_default>;
 1689                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 1690                                 #address-cells = <1>;
 1691                                 #size-cells = <0>;
 1692                                 power-domains = <&rpmhpd SDM845_CX>;
 1693                                 operating-points-v2 = <&qup_opp_table>;
 1694                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1695                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 1696                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 1697                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1698                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
 1699                                        <&gpi_dma1 1 0 QCOM_GPI_I2C>;
 1700                                 dma-names = "tx", "rx";
 1701                                 status = "disabled";
 1702                         };
 1703 
 1704                         spi8: spi@a80000 {
 1705                                 compatible = "qcom,geni-spi";
 1706                                 reg = <0 0x00a80000 0 0x4000>;
 1707                                 clock-names = "se";
 1708                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 1709                                 pinctrl-names = "default";
 1710                                 pinctrl-0 = <&qup_spi8_default>;
 1711                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 1712                                 #address-cells = <1>;
 1713                                 #size-cells = <0>;
 1714                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1715                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1716                                 interconnect-names = "qup-core", "qup-config";
 1717                                 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
 1718                                        <&gpi_dma1 1 0 QCOM_GPI_SPI>;
 1719                                 dma-names = "tx", "rx";
 1720                                 status = "disabled";
 1721                         };
 1722 
 1723                         uart8: serial@a80000 {
 1724                                 compatible = "qcom,geni-uart";
 1725                                 reg = <0 0x00a80000 0 0x4000>;
 1726                                 clock-names = "se";
 1727                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
 1728                                 pinctrl-names = "default";
 1729                                 pinctrl-0 = <&qup_uart8_default>;
 1730                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
 1731                                 power-domains = <&rpmhpd SDM845_CX>;
 1732                                 operating-points-v2 = <&qup_opp_table>;
 1733                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1734                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1735                                 interconnect-names = "qup-core", "qup-config";
 1736                                 status = "disabled";
 1737                         };
 1738 
 1739                         i2c9: i2c@a84000 {
 1740                                 compatible = "qcom,geni-i2c";
 1741                                 reg = <0 0x00a84000 0 0x4000>;
 1742                                 clock-names = "se";
 1743                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 1744                                 pinctrl-names = "default";
 1745                                 pinctrl-0 = <&qup_i2c9_default>;
 1746                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 1747                                 #address-cells = <1>;
 1748                                 #size-cells = <0>;
 1749                                 power-domains = <&rpmhpd SDM845_CX>;
 1750                                 operating-points-v2 = <&qup_opp_table>;
 1751                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1752                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 1753                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 1754                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1755                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
 1756                                        <&gpi_dma1 1 1 QCOM_GPI_I2C>;
 1757                                 dma-names = "tx", "rx";
 1758                                 status = "disabled";
 1759                         };
 1760 
 1761                         spi9: spi@a84000 {
 1762                                 compatible = "qcom,geni-spi";
 1763                                 reg = <0 0x00a84000 0 0x4000>;
 1764                                 clock-names = "se";
 1765                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 1766                                 pinctrl-names = "default";
 1767                                 pinctrl-0 = <&qup_spi9_default>;
 1768                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 1769                                 #address-cells = <1>;
 1770                                 #size-cells = <0>;
 1771                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1772                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1773                                 interconnect-names = "qup-core", "qup-config";
 1774                                 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
 1775                                        <&gpi_dma1 1 1 QCOM_GPI_SPI>;
 1776                                 dma-names = "tx", "rx";
 1777                                 status = "disabled";
 1778                         };
 1779 
 1780                         uart9: serial@a84000 {
 1781                                 compatible = "qcom,geni-debug-uart";
 1782                                 reg = <0 0x00a84000 0 0x4000>;
 1783                                 clock-names = "se";
 1784                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 1785                                 pinctrl-names = "default";
 1786                                 pinctrl-0 = <&qup_uart9_default>;
 1787                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
 1788                                 power-domains = <&rpmhpd SDM845_CX>;
 1789                                 operating-points-v2 = <&qup_opp_table>;
 1790                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1791                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1792                                 interconnect-names = "qup-core", "qup-config";
 1793                                 status = "disabled";
 1794                         };
 1795 
 1796                         i2c10: i2c@a88000 {
 1797                                 compatible = "qcom,geni-i2c";
 1798                                 reg = <0 0x00a88000 0 0x4000>;
 1799                                 clock-names = "se";
 1800                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 1801                                 pinctrl-names = "default";
 1802                                 pinctrl-0 = <&qup_i2c10_default>;
 1803                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 1804                                 #address-cells = <1>;
 1805                                 #size-cells = <0>;
 1806                                 power-domains = <&rpmhpd SDM845_CX>;
 1807                                 operating-points-v2 = <&qup_opp_table>;
 1808                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1809                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 1810                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 1811                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1812                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
 1813                                        <&gpi_dma1 1 2 QCOM_GPI_I2C>;
 1814                                 dma-names = "tx", "rx";
 1815                                 status = "disabled";
 1816                         };
 1817 
 1818                         spi10: spi@a88000 {
 1819                                 compatible = "qcom,geni-spi";
 1820                                 reg = <0 0x00a88000 0 0x4000>;
 1821                                 clock-names = "se";
 1822                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 1823                                 pinctrl-names = "default";
 1824                                 pinctrl-0 = <&qup_spi10_default>;
 1825                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 1826                                 #address-cells = <1>;
 1827                                 #size-cells = <0>;
 1828                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1829                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1830                                 interconnect-names = "qup-core", "qup-config";
 1831                                 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
 1832                                        <&gpi_dma1 1 2 QCOM_GPI_SPI>;
 1833                                 dma-names = "tx", "rx";
 1834                                 status = "disabled";
 1835                         };
 1836 
 1837                         uart10: serial@a88000 {
 1838                                 compatible = "qcom,geni-uart";
 1839                                 reg = <0 0x00a88000 0 0x4000>;
 1840                                 clock-names = "se";
 1841                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
 1842                                 pinctrl-names = "default";
 1843                                 pinctrl-0 = <&qup_uart10_default>;
 1844                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 1845                                 power-domains = <&rpmhpd SDM845_CX>;
 1846                                 operating-points-v2 = <&qup_opp_table>;
 1847                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1848                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1849                                 interconnect-names = "qup-core", "qup-config";
 1850                                 status = "disabled";
 1851                         };
 1852 
 1853                         i2c11: i2c@a8c000 {
 1854                                 compatible = "qcom,geni-i2c";
 1855                                 reg = <0 0x00a8c000 0 0x4000>;
 1856                                 clock-names = "se";
 1857                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 1858                                 pinctrl-names = "default";
 1859                                 pinctrl-0 = <&qup_i2c11_default>;
 1860                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 1861                                 #address-cells = <1>;
 1862                                 #size-cells = <0>;
 1863                                 power-domains = <&rpmhpd SDM845_CX>;
 1864                                 operating-points-v2 = <&qup_opp_table>;
 1865                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1866                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 1867                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 1868                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1869                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
 1870                                        <&gpi_dma1 1 3 QCOM_GPI_I2C>;
 1871                                 dma-names = "tx", "rx";
 1872                                 status = "disabled";
 1873                         };
 1874 
 1875                         spi11: spi@a8c000 {
 1876                                 compatible = "qcom,geni-spi";
 1877                                 reg = <0 0x00a8c000 0 0x4000>;
 1878                                 clock-names = "se";
 1879                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 1880                                 pinctrl-names = "default";
 1881                                 pinctrl-0 = <&qup_spi11_default>;
 1882                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 1883                                 #address-cells = <1>;
 1884                                 #size-cells = <0>;
 1885                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1886                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1887                                 interconnect-names = "qup-core", "qup-config";
 1888                                 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
 1889                                        <&gpi_dma1 1 3 QCOM_GPI_SPI>;
 1890                                 dma-names = "tx", "rx";
 1891                                 status = "disabled";
 1892                         };
 1893 
 1894                         uart11: serial@a8c000 {
 1895                                 compatible = "qcom,geni-uart";
 1896                                 reg = <0 0x00a8c000 0 0x4000>;
 1897                                 clock-names = "se";
 1898                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
 1899                                 pinctrl-names = "default";
 1900                                 pinctrl-0 = <&qup_uart11_default>;
 1901                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 1902                                 power-domains = <&rpmhpd SDM845_CX>;
 1903                                 operating-points-v2 = <&qup_opp_table>;
 1904                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1905                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1906                                 interconnect-names = "qup-core", "qup-config";
 1907                                 status = "disabled";
 1908                         };
 1909 
 1910                         i2c12: i2c@a90000 {
 1911                                 compatible = "qcom,geni-i2c";
 1912                                 reg = <0 0x00a90000 0 0x4000>;
 1913                                 clock-names = "se";
 1914                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 1915                                 pinctrl-names = "default";
 1916                                 pinctrl-0 = <&qup_i2c12_default>;
 1917                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 1918                                 #address-cells = <1>;
 1919                                 #size-cells = <0>;
 1920                                 power-domains = <&rpmhpd SDM845_CX>;
 1921                                 operating-points-v2 = <&qup_opp_table>;
 1922                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1923                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 1924                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 1925                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1926                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
 1927                                        <&gpi_dma1 1 4 QCOM_GPI_I2C>;
 1928                                 dma-names = "tx", "rx";
 1929                                 status = "disabled";
 1930                         };
 1931 
 1932                         spi12: spi@a90000 {
 1933                                 compatible = "qcom,geni-spi";
 1934                                 reg = <0 0x00a90000 0 0x4000>;
 1935                                 clock-names = "se";
 1936                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 1937                                 pinctrl-names = "default";
 1938                                 pinctrl-0 = <&qup_spi12_default>;
 1939                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 1940                                 #address-cells = <1>;
 1941                                 #size-cells = <0>;
 1942                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1943                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1944                                 interconnect-names = "qup-core", "qup-config";
 1945                                 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
 1946                                        <&gpi_dma1 1 4 QCOM_GPI_SPI>;
 1947                                 dma-names = "tx", "rx";
 1948                                 status = "disabled";
 1949                         };
 1950 
 1951                         uart12: serial@a90000 {
 1952                                 compatible = "qcom,geni-uart";
 1953                                 reg = <0 0x00a90000 0 0x4000>;
 1954                                 clock-names = "se";
 1955                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 1956                                 pinctrl-names = "default";
 1957                                 pinctrl-0 = <&qup_uart12_default>;
 1958                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 1959                                 power-domains = <&rpmhpd SDM845_CX>;
 1960                                 operating-points-v2 = <&qup_opp_table>;
 1961                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1962                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 1963                                 interconnect-names = "qup-core", "qup-config";
 1964                                 status = "disabled";
 1965                         };
 1966 
 1967                         i2c13: i2c@a94000 {
 1968                                 compatible = "qcom,geni-i2c";
 1969                                 reg = <0 0x00a94000 0 0x4000>;
 1970                                 clock-names = "se";
 1971                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 1972                                 pinctrl-names = "default";
 1973                                 pinctrl-0 = <&qup_i2c13_default>;
 1974                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 1975                                 #address-cells = <1>;
 1976                                 #size-cells = <0>;
 1977                                 power-domains = <&rpmhpd SDM845_CX>;
 1978                                 operating-points-v2 = <&qup_opp_table>;
 1979                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 1980                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 1981                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 1982                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 1983                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
 1984                                        <&gpi_dma1 1 5 QCOM_GPI_I2C>;
 1985                                 dma-names = "tx", "rx";
 1986                                 status = "disabled";
 1987                         };
 1988 
 1989                         spi13: spi@a94000 {
 1990                                 compatible = "qcom,geni-spi";
 1991                                 reg = <0 0x00a94000 0 0x4000>;
 1992                                 clock-names = "se";
 1993                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 1994                                 pinctrl-names = "default";
 1995                                 pinctrl-0 = <&qup_spi13_default>;
 1996                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 1997                                 #address-cells = <1>;
 1998                                 #size-cells = <0>;
 1999                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2000                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 2001                                 interconnect-names = "qup-core", "qup-config";
 2002                                 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
 2003                                        <&gpi_dma1 1 5 QCOM_GPI_SPI>;
 2004                                 dma-names = "tx", "rx";
 2005                                 status = "disabled";
 2006                         };
 2007 
 2008                         uart13: serial@a94000 {
 2009                                 compatible = "qcom,geni-uart";
 2010                                 reg = <0 0x00a94000 0 0x4000>;
 2011                                 clock-names = "se";
 2012                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
 2013                                 pinctrl-names = "default";
 2014                                 pinctrl-0 = <&qup_uart13_default>;
 2015                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 2016                                 power-domains = <&rpmhpd SDM845_CX>;
 2017                                 operating-points-v2 = <&qup_opp_table>;
 2018                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2019                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 2020                                 interconnect-names = "qup-core", "qup-config";
 2021                                 status = "disabled";
 2022                         };
 2023 
 2024                         i2c14: i2c@a98000 {
 2025                                 compatible = "qcom,geni-i2c";
 2026                                 reg = <0 0x00a98000 0 0x4000>;
 2027                                 clock-names = "se";
 2028                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 2029                                 pinctrl-names = "default";
 2030                                 pinctrl-0 = <&qup_i2c14_default>;
 2031                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 2032                                 #address-cells = <1>;
 2033                                 #size-cells = <0>;
 2034                                 power-domains = <&rpmhpd SDM845_CX>;
 2035                                 operating-points-v2 = <&qup_opp_table>;
 2036                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2037                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 2038                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 2039                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 2040                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
 2041                                        <&gpi_dma1 1 6 QCOM_GPI_I2C>;
 2042                                 dma-names = "tx", "rx";
 2043                                 status = "disabled";
 2044                         };
 2045 
 2046                         spi14: spi@a98000 {
 2047                                 compatible = "qcom,geni-spi";
 2048                                 reg = <0 0x00a98000 0 0x4000>;
 2049                                 clock-names = "se";
 2050                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 2051                                 pinctrl-names = "default";
 2052                                 pinctrl-0 = <&qup_spi14_default>;
 2053                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 2054                                 #address-cells = <1>;
 2055                                 #size-cells = <0>;
 2056                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2057                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 2058                                 interconnect-names = "qup-core", "qup-config";
 2059                                 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
 2060                                        <&gpi_dma1 1 6 QCOM_GPI_SPI>;
 2061                                 dma-names = "tx", "rx";
 2062                                 status = "disabled";
 2063                         };
 2064 
 2065                         uart14: serial@a98000 {
 2066                                 compatible = "qcom,geni-uart";
 2067                                 reg = <0 0x00a98000 0 0x4000>;
 2068                                 clock-names = "se";
 2069                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
 2070                                 pinctrl-names = "default";
 2071                                 pinctrl-0 = <&qup_uart14_default>;
 2072                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 2073                                 power-domains = <&rpmhpd SDM845_CX>;
 2074                                 operating-points-v2 = <&qup_opp_table>;
 2075                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2076                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 2077                                 interconnect-names = "qup-core", "qup-config";
 2078                                 status = "disabled";
 2079                         };
 2080 
 2081                         i2c15: i2c@a9c000 {
 2082                                 compatible = "qcom,geni-i2c";
 2083                                 reg = <0 0x00a9c000 0 0x4000>;
 2084                                 clock-names = "se";
 2085                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 2086                                 pinctrl-names = "default";
 2087                                 pinctrl-0 = <&qup_i2c15_default>;
 2088                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 2089                                 #address-cells = <1>;
 2090                                 #size-cells = <0>;
 2091                                 power-domains = <&rpmhpd SDM845_CX>;
 2092                                 operating-points-v2 = <&qup_opp_table>;
 2093                                 status = "disabled";
 2094                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2095                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>,
 2096                                                 <&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>;
 2097                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 2098                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
 2099                                        <&gpi_dma1 1 7 QCOM_GPI_I2C>;
 2100                                 dma-names = "tx", "rx";
 2101                         };
 2102 
 2103                         spi15: spi@a9c000 {
 2104                                 compatible = "qcom,geni-spi";
 2105                                 reg = <0 0x00a9c000 0 0x4000>;
 2106                                 clock-names = "se";
 2107                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 2108                                 pinctrl-names = "default";
 2109                                 pinctrl-0 = <&qup_spi15_default>;
 2110                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 2111                                 #address-cells = <1>;
 2112                                 #size-cells = <0>;
 2113                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2114                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 2115                                 interconnect-names = "qup-core", "qup-config";
 2116                                 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
 2117                                        <&gpi_dma1 1 7 QCOM_GPI_SPI>;
 2118                                 dma-names = "tx", "rx";
 2119                                 status = "disabled";
 2120                         };
 2121 
 2122                         uart15: serial@a9c000 {
 2123                                 compatible = "qcom,geni-uart";
 2124                                 reg = <0 0x00a9c000 0 0x4000>;
 2125                                 clock-names = "se";
 2126                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
 2127                                 pinctrl-names = "default";
 2128                                 pinctrl-0 = <&qup_uart15_default>;
 2129                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 2130                                 power-domains = <&rpmhpd SDM845_CX>;
 2131                                 operating-points-v2 = <&qup_opp_table>;
 2132                                 interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>,
 2133                                                 <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>;
 2134                                 interconnect-names = "qup-core", "qup-config";
 2135                                 status = "disabled";
 2136                         };
 2137                 };
 2138 
 2139                 llcc: system-cache-controller@1100000 {
 2140                         compatible = "qcom,sdm845-llcc";
 2141                         reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
 2142                         reg-names = "llcc_base", "llcc_broadcast_base";
 2143                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 2144                 };
 2145 
 2146                 pmu@1436400 {
 2147                         compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
 2148                         reg = <0 0x01436400 0 0x600>;
 2149                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
 2150                         interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
 2151 
 2152                         operating-points-v2 = <&cpu_bwmon_opp_table>;
 2153 
 2154                         cpu_bwmon_opp_table: opp-table {
 2155                                 compatible = "operating-points-v2";
 2156 
 2157                                 /*
 2158                                  * The interconnect path bandwidth taken from
 2159                                  * cpu4_opp_table bandwidth for OSM L3
 2160                                  * interconnect.  This also matches the OSM L3
 2161                                  * from bandwidth table of qcom,cpu4-l3lat-mon
 2162                                  * (qcom,core-dev-table, bus width: 16 bytes)
 2163                                  * from msm-4.9 downstream kernel.
 2164                                  */
 2165                                 opp-0 {
 2166                                         opp-peak-kBps = <4800000>;
 2167                                 };
 2168                                 opp-1 {
 2169                                         opp-peak-kBps = <9216000>;
 2170                                 };
 2171                                 opp-2 {
 2172                                         opp-peak-kBps = <15052800>;
 2173                                 };
 2174                                 opp-3 {
 2175                                         opp-peak-kBps = <20889600>;
 2176                                 };
 2177                                 opp-4 {
 2178                                         opp-peak-kBps = <25497600>;
 2179                                 };
 2180                         };
 2181                 };
 2182 
 2183                 pcie0: pci@1c00000 {
 2184                         compatible = "qcom,pcie-sdm845";
 2185                         reg = <0 0x01c00000 0 0x2000>,
 2186                               <0 0x60000000 0 0xf1d>,
 2187                               <0 0x60000f20 0 0xa8>,
 2188                               <0 0x60100000 0 0x100000>;
 2189                         reg-names = "parf", "dbi", "elbi", "config";
 2190                         device_type = "pci";
 2191                         linux,pci-domain = <0>;
 2192                         bus-range = <0x00 0xff>;
 2193                         num-lanes = <1>;
 2194 
 2195                         #address-cells = <3>;
 2196                         #size-cells = <2>;
 2197 
 2198                         ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
 2199                                  <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
 2200 
 2201                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 2202                         interrupt-names = "msi";
 2203                         #interrupt-cells = <1>;
 2204                         interrupt-map-mask = <0 0 0 0x7>;
 2205                         interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 2206                                         <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 2207                                         <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 2208                                         <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 2209 
 2210                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 2211                                  <&gcc GCC_PCIE_0_AUX_CLK>,
 2212                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 2213                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 2214                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 2215                                  <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
 2216                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
 2217                         clock-names = "pipe",
 2218                                       "aux",
 2219                                       "cfg",
 2220                                       "bus_master",
 2221                                       "bus_slave",
 2222                                       "slave_q2a",
 2223                                       "tbu";
 2224 
 2225                         iommus = <&apps_smmu 0x1c10 0xf>;
 2226                         iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
 2227                                     <0x100 &apps_smmu 0x1c11 0x1>,
 2228                                     <0x200 &apps_smmu 0x1c12 0x1>,
 2229                                     <0x300 &apps_smmu 0x1c13 0x1>,
 2230                                     <0x400 &apps_smmu 0x1c14 0x1>,
 2231                                     <0x500 &apps_smmu 0x1c15 0x1>,
 2232                                     <0x600 &apps_smmu 0x1c16 0x1>,
 2233                                     <0x700 &apps_smmu 0x1c17 0x1>,
 2234                                     <0x800 &apps_smmu 0x1c18 0x1>,
 2235                                     <0x900 &apps_smmu 0x1c19 0x1>,
 2236                                     <0xa00 &apps_smmu 0x1c1a 0x1>,
 2237                                     <0xb00 &apps_smmu 0x1c1b 0x1>,
 2238                                     <0xc00 &apps_smmu 0x1c1c 0x1>,
 2239                                     <0xd00 &apps_smmu 0x1c1d 0x1>,
 2240                                     <0xe00 &apps_smmu 0x1c1e 0x1>,
 2241                                     <0xf00 &apps_smmu 0x1c1f 0x1>;
 2242 
 2243                         resets = <&gcc GCC_PCIE_0_BCR>;
 2244                         reset-names = "pci";
 2245 
 2246                         power-domains = <&gcc PCIE_0_GDSC>;
 2247 
 2248                         phys = <&pcie0_lane>;
 2249                         phy-names = "pciephy";
 2250 
 2251                         status = "disabled";
 2252                 };
 2253 
 2254                 pcie0_phy: phy@1c06000 {
 2255                         compatible = "qcom,sdm845-qmp-pcie-phy";
 2256                         reg = <0 0x01c06000 0 0x18c>;
 2257                         #address-cells = <2>;
 2258                         #size-cells = <2>;
 2259                         ranges;
 2260                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 2261                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 2262                                  <&gcc GCC_PCIE_0_CLKREF_CLK>,
 2263                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
 2264                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
 2265 
 2266                         resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 2267                         reset-names = "phy";
 2268 
 2269                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
 2270                         assigned-clock-rates = <100000000>;
 2271 
 2272                         status = "disabled";
 2273 
 2274                         pcie0_lane: phy@1c06200 {
 2275                                 reg = <0 0x01c06200 0 0x128>,
 2276                                       <0 0x01c06400 0 0x1fc>,
 2277                                       <0 0x01c06800 0 0x218>,
 2278                                       <0 0x01c06600 0 0x70>;
 2279                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 2280                                 clock-names = "pipe0";
 2281 
 2282                                 #clock-cells = <0>;
 2283                                 #phy-cells = <0>;
 2284                                 clock-output-names = "pcie_0_pipe_clk";
 2285                         };
 2286                 };
 2287 
 2288                 pcie1: pci@1c08000 {
 2289                         compatible = "qcom,pcie-sdm845";
 2290                         reg = <0 0x01c08000 0 0x2000>,
 2291                               <0 0x40000000 0 0xf1d>,
 2292                               <0 0x40000f20 0 0xa8>,
 2293                               <0 0x40100000 0 0x100000>;
 2294                         reg-names = "parf", "dbi", "elbi", "config";
 2295                         device_type = "pci";
 2296                         linux,pci-domain = <1>;
 2297                         bus-range = <0x00 0xff>;
 2298                         num-lanes = <1>;
 2299 
 2300                         #address-cells = <3>;
 2301                         #size-cells = <2>;
 2302 
 2303                         ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
 2304                                  <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
 2305 
 2306                         interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>;
 2307                         interrupt-names = "msi";
 2308                         #interrupt-cells = <1>;
 2309                         interrupt-map-mask = <0 0 0 0x7>;
 2310                         interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 2311                                         <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 2312                                         <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 2313                                         <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 2314 
 2315                         clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 2316                                  <&gcc GCC_PCIE_1_AUX_CLK>,
 2317                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 2318                                  <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 2319                                  <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
 2320                                  <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
 2321                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
 2322                                  <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
 2323                         clock-names = "pipe",
 2324                                       "aux",
 2325                                       "cfg",
 2326                                       "bus_master",
 2327                                       "bus_slave",
 2328                                       "slave_q2a",
 2329                                       "ref",
 2330                                       "tbu";
 2331 
 2332                         assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
 2333                         assigned-clock-rates = <19200000>;
 2334 
 2335                         iommus = <&apps_smmu 0x1c00 0xf>;
 2336                         iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
 2337                                     <0x100 &apps_smmu 0x1c01 0x1>,
 2338                                     <0x200 &apps_smmu 0x1c02 0x1>,
 2339                                     <0x300 &apps_smmu 0x1c03 0x1>,
 2340                                     <0x400 &apps_smmu 0x1c04 0x1>,
 2341                                     <0x500 &apps_smmu 0x1c05 0x1>,
 2342                                     <0x600 &apps_smmu 0x1c06 0x1>,
 2343                                     <0x700 &apps_smmu 0x1c07 0x1>,
 2344                                     <0x800 &apps_smmu 0x1c08 0x1>,
 2345                                     <0x900 &apps_smmu 0x1c09 0x1>,
 2346                                     <0xa00 &apps_smmu 0x1c0a 0x1>,
 2347                                     <0xb00 &apps_smmu 0x1c0b 0x1>,
 2348                                     <0xc00 &apps_smmu 0x1c0c 0x1>,
 2349                                     <0xd00 &apps_smmu 0x1c0d 0x1>,
 2350                                     <0xe00 &apps_smmu 0x1c0e 0x1>,
 2351                                     <0xf00 &apps_smmu 0x1c0f 0x1>;
 2352 
 2353                         resets = <&gcc GCC_PCIE_1_BCR>;
 2354                         reset-names = "pci";
 2355 
 2356                         power-domains = <&gcc PCIE_1_GDSC>;
 2357 
 2358                         phys = <&pcie1_lane>;
 2359                         phy-names = "pciephy";
 2360 
 2361                         status = "disabled";
 2362                 };
 2363 
 2364                 pcie1_phy: phy@1c0a000 {
 2365                         compatible = "qcom,sdm845-qhp-pcie-phy";
 2366                         reg = <0 0x01c0a000 0 0x800>;
 2367                         #address-cells = <2>;
 2368                         #size-cells = <2>;
 2369                         ranges;
 2370                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 2371                                  <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 2372                                  <&gcc GCC_PCIE_1_CLKREF_CLK>,
 2373                                  <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
 2374                         clock-names = "aux", "cfg_ahb", "ref", "refgen";
 2375 
 2376                         resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 2377                         reset-names = "phy";
 2378 
 2379                         assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
 2380                         assigned-clock-rates = <100000000>;
 2381 
 2382                         status = "disabled";
 2383 
 2384                         pcie1_lane: phy@1c06200 {
 2385                                 reg = <0 0x01c0a800 0 0x800>,
 2386                                       <0 0x01c0a800 0 0x800>,
 2387                                       <0 0x01c0b800 0 0x400>;
 2388                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 2389                                 clock-names = "pipe0";
 2390 
 2391                                 #clock-cells = <0>;
 2392                                 #phy-cells = <0>;
 2393                                 clock-output-names = "pcie_1_pipe_clk";
 2394                         };
 2395                 };
 2396 
 2397                 mem_noc: interconnect@1380000 {
 2398                         compatible = "qcom,sdm845-mem-noc";
 2399                         reg = <0 0x01380000 0 0x27200>;
 2400                         #interconnect-cells = <2>;
 2401                         qcom,bcm-voters = <&apps_bcm_voter>;
 2402                 };
 2403 
 2404                 dc_noc: interconnect@14e0000 {
 2405                         compatible = "qcom,sdm845-dc-noc";
 2406                         reg = <0 0x014e0000 0 0x400>;
 2407                         #interconnect-cells = <2>;
 2408                         qcom,bcm-voters = <&apps_bcm_voter>;
 2409                 };
 2410 
 2411                 config_noc: interconnect@1500000 {
 2412                         compatible = "qcom,sdm845-config-noc";
 2413                         reg = <0 0x01500000 0 0x5080>;
 2414                         #interconnect-cells = <2>;
 2415                         qcom,bcm-voters = <&apps_bcm_voter>;
 2416                 };
 2417 
 2418                 system_noc: interconnect@1620000 {
 2419                         compatible = "qcom,sdm845-system-noc";
 2420                         reg = <0 0x01620000 0 0x18080>;
 2421                         #interconnect-cells = <2>;
 2422                         qcom,bcm-voters = <&apps_bcm_voter>;
 2423                 };
 2424 
 2425                 aggre1_noc: interconnect@16e0000 {
 2426                         compatible = "qcom,sdm845-aggre1-noc";
 2427                         reg = <0 0x016e0000 0 0x15080>;
 2428                         #interconnect-cells = <2>;
 2429                         qcom,bcm-voters = <&apps_bcm_voter>;
 2430                 };
 2431 
 2432                 aggre2_noc: interconnect@1700000 {
 2433                         compatible = "qcom,sdm845-aggre2-noc";
 2434                         reg = <0 0x01700000 0 0x1f300>;
 2435                         #interconnect-cells = <2>;
 2436                         qcom,bcm-voters = <&apps_bcm_voter>;
 2437                 };
 2438 
 2439                 mmss_noc: interconnect@1740000 {
 2440                         compatible = "qcom,sdm845-mmss-noc";
 2441                         reg = <0 0x01740000 0 0x1c100>;
 2442                         #interconnect-cells = <2>;
 2443                         qcom,bcm-voters = <&apps_bcm_voter>;
 2444                 };
 2445 
 2446                 ufs_mem_hc: ufshc@1d84000 {
 2447                         compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
 2448                                      "jedec,ufs-2.0";
 2449                         reg = <0 0x01d84000 0 0x2500>,
 2450                               <0 0x01d90000 0 0x8000>;
 2451                         reg-names = "std", "ice";
 2452                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 2453                         phys = <&ufs_mem_phy_lanes>;
 2454                         phy-names = "ufsphy";
 2455                         lanes-per-direction = <2>;
 2456                         power-domains = <&gcc UFS_PHY_GDSC>;
 2457                         #reset-cells = <1>;
 2458                         resets = <&gcc GCC_UFS_PHY_BCR>;
 2459                         reset-names = "rst";
 2460 
 2461                         iommus = <&apps_smmu 0x100 0xf>;
 2462 
 2463                         clock-names =
 2464                                 "core_clk",
 2465                                 "bus_aggr_clk",
 2466                                 "iface_clk",
 2467                                 "core_clk_unipro",
 2468                                 "ref_clk",
 2469                                 "tx_lane0_sync_clk",
 2470                                 "rx_lane0_sync_clk",
 2471                                 "rx_lane1_sync_clk",
 2472                                 "ice_core_clk";
 2473                         clocks =
 2474                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
 2475                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 2476                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
 2477                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 2478                                 <&rpmhcc RPMH_CXO_CLK>,
 2479                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 2480                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 2481                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
 2482                                 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
 2483                         freq-table-hz =
 2484                                 <50000000 200000000>,
 2485                                 <0 0>,
 2486                                 <0 0>,
 2487                                 <37500000 150000000>,
 2488                                 <0 0>,
 2489                                 <0 0>,
 2490                                 <0 0>,
 2491                                 <0 0>,
 2492                                 <0 300000000>;
 2493 
 2494                         status = "disabled";
 2495                 };
 2496 
 2497                 ufs_mem_phy: phy@1d87000 {
 2498                         compatible = "qcom,sdm845-qmp-ufs-phy";
 2499                         reg = <0 0x01d87000 0 0x18c>;
 2500                         #address-cells = <2>;
 2501                         #size-cells = <2>;
 2502                         ranges;
 2503                         clock-names = "ref",
 2504                                       "ref_aux";
 2505                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
 2506                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 2507 
 2508                         resets = <&ufs_mem_hc 0>;
 2509                         reset-names = "ufsphy";
 2510                         status = "disabled";
 2511 
 2512                         ufs_mem_phy_lanes: phy@1d87400 {
 2513                                 reg = <0 0x01d87400 0 0x108>,
 2514                                       <0 0x01d87600 0 0x1e0>,
 2515                                       <0 0x01d87c00 0 0x1dc>,
 2516                                       <0 0x01d87800 0 0x108>,
 2517                                       <0 0x01d87a00 0 0x1e0>;
 2518                                 #phy-cells = <0>;
 2519                         };
 2520                 };
 2521 
 2522                 cryptobam: dma-controller@1dc4000 {
 2523                         compatible = "qcom,bam-v1.7.0";
 2524                         reg = <0 0x01dc4000 0 0x24000>;
 2525                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 2526                         clocks = <&rpmhcc RPMH_CE_CLK>;
 2527                         clock-names = "bam_clk";
 2528                         #dma-cells = <1>;
 2529                         qcom,ee = <0>;
 2530                         qcom,controlled-remotely;
 2531                         iommus = <&apps_smmu 0x704 0x1>,
 2532                                  <&apps_smmu 0x706 0x1>,
 2533                                  <&apps_smmu 0x714 0x1>,
 2534                                  <&apps_smmu 0x716 0x1>;
 2535                 };
 2536 
 2537                 crypto: crypto@1dfa000 {
 2538                         compatible = "qcom,crypto-v5.4";
 2539                         reg = <0 0x01dfa000 0 0x6000>;
 2540                         clocks = <&gcc GCC_CE1_AHB_CLK>,
 2541                                  <&gcc GCC_CE1_AXI_CLK>,
 2542                                  <&rpmhcc RPMH_CE_CLK>;
 2543                         clock-names = "iface", "bus", "core";
 2544                         dmas = <&cryptobam 6>, <&cryptobam 7>;
 2545                         dma-names = "rx", "tx";
 2546                         iommus = <&apps_smmu 0x704 0x1>,
 2547                                  <&apps_smmu 0x706 0x1>,
 2548                                  <&apps_smmu 0x714 0x1>,
 2549                                  <&apps_smmu 0x716 0x1>;
 2550                 };
 2551 
 2552                 ipa: ipa@1e40000 {
 2553                         compatible = "qcom,sdm845-ipa";
 2554 
 2555                         iommus = <&apps_smmu 0x720 0x0>,
 2556                                  <&apps_smmu 0x722 0x0>;
 2557                         reg = <0 0x1e40000 0 0x7000>,
 2558                               <0 0x1e47000 0 0x2000>,
 2559                               <0 0x1e04000 0 0x2c000>;
 2560                         reg-names = "ipa-reg",
 2561                                     "ipa-shared",
 2562                                     "gsi";
 2563 
 2564                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
 2565                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
 2566                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 2567                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
 2568                         interrupt-names = "ipa",
 2569                                           "gsi",
 2570                                           "ipa-clock-query",
 2571                                           "ipa-setup-ready";
 2572 
 2573                         clocks = <&rpmhcc RPMH_IPA_CLK>;
 2574                         clock-names = "core";
 2575 
 2576                         interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>,
 2577                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
 2578                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
 2579                         interconnect-names = "memory",
 2580                                              "imem",
 2581                                              "config";
 2582 
 2583                         qcom,smem-states = <&ipa_smp2p_out 0>,
 2584                                            <&ipa_smp2p_out 1>;
 2585                         qcom,smem-state-names = "ipa-clock-enabled-valid",
 2586                                                 "ipa-clock-enabled";
 2587 
 2588                         status = "disabled";
 2589                 };
 2590 
 2591                 tcsr_mutex_regs: syscon@1f40000 {
 2592                         compatible = "syscon";
 2593                         reg = <0 0x01f40000 0 0x40000>;
 2594                 };
 2595 
 2596                 tlmm: pinctrl@3400000 {
 2597                         compatible = "qcom,sdm845-pinctrl";
 2598                         reg = <0 0x03400000 0 0xc00000>;
 2599                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 2600                         gpio-controller;
 2601                         #gpio-cells = <2>;
 2602                         interrupt-controller;
 2603                         #interrupt-cells = <2>;
 2604                         gpio-ranges = <&tlmm 0 0 151>;
 2605                         wakeup-parent = <&pdc_intc>;
 2606 
 2607                         cci0_default: cci0-default {
 2608                                 /* SDA, SCL */
 2609                                 pins = "gpio17", "gpio18";
 2610                                 function = "cci_i2c";
 2611 
 2612                                 bias-pull-up;
 2613                                 drive-strength = <2>; /* 2 mA */
 2614                         };
 2615 
 2616                         cci0_sleep: cci0-sleep {
 2617                                 /* SDA, SCL */
 2618                                 pins = "gpio17", "gpio18";
 2619                                 function = "cci_i2c";
 2620 
 2621                                 drive-strength = <2>; /* 2 mA */
 2622                                 bias-pull-down;
 2623                         };
 2624 
 2625                         cci1_default: cci1-default {
 2626                                 /* SDA, SCL */
 2627                                 pins = "gpio19", "gpio20";
 2628                                 function = "cci_i2c";
 2629 
 2630                                 bias-pull-up;
 2631                                 drive-strength = <2>; /* 2 mA */
 2632                         };
 2633 
 2634                         cci1_sleep: cci1-sleep {
 2635                                 /* SDA, SCL */
 2636                                 pins = "gpio19", "gpio20";
 2637                                 function = "cci_i2c";
 2638 
 2639                                 drive-strength = <2>; /* 2 mA */
 2640                                 bias-pull-down;
 2641                         };
 2642 
 2643                         qspi_clk: qspi-clk {
 2644                                 pinmux {
 2645                                         pins = "gpio95";
 2646                                         function = "qspi_clk";
 2647                                 };
 2648                         };
 2649 
 2650                         qspi_cs0: qspi-cs0 {
 2651                                 pinmux {
 2652                                         pins = "gpio90";
 2653                                         function = "qspi_cs";
 2654                                 };
 2655                         };
 2656 
 2657                         qspi_cs1: qspi-cs1 {
 2658                                 pinmux {
 2659                                         pins = "gpio89";
 2660                                         function = "qspi_cs";
 2661                                 };
 2662                         };
 2663 
 2664                         qspi_data01: qspi-data01 {
 2665                                 pinmux-data {
 2666                                         pins = "gpio91", "gpio92";
 2667                                         function = "qspi_data";
 2668                                 };
 2669                         };
 2670 
 2671                         qspi_data12: qspi-data12 {
 2672                                 pinmux-data {
 2673                                         pins = "gpio93", "gpio94";
 2674                                         function = "qspi_data";
 2675                                 };
 2676                         };
 2677 
 2678                         qup_i2c0_default: qup-i2c0-default {
 2679                                 pinmux {
 2680                                         pins = "gpio0", "gpio1";
 2681                                         function = "qup0";
 2682                                 };
 2683                         };
 2684 
 2685                         qup_i2c1_default: qup-i2c1-default {
 2686                                 pinmux {
 2687                                         pins = "gpio17", "gpio18";
 2688                                         function = "qup1";
 2689                                 };
 2690                         };
 2691 
 2692                         qup_i2c2_default: qup-i2c2-default {
 2693                                 pinmux {
 2694                                         pins = "gpio27", "gpio28";
 2695                                         function = "qup2";
 2696                                 };
 2697                         };
 2698 
 2699                         qup_i2c3_default: qup-i2c3-default {
 2700                                 pinmux {
 2701                                         pins = "gpio41", "gpio42";
 2702                                         function = "qup3";
 2703                                 };
 2704                         };
 2705 
 2706                         qup_i2c4_default: qup-i2c4-default {
 2707                                 pinmux {
 2708                                         pins = "gpio89", "gpio90";
 2709                                         function = "qup4";
 2710                                 };
 2711                         };
 2712 
 2713                         qup_i2c5_default: qup-i2c5-default {
 2714                                 pinmux {
 2715                                         pins = "gpio85", "gpio86";
 2716                                         function = "qup5";
 2717                                 };
 2718                         };
 2719 
 2720                         qup_i2c6_default: qup-i2c6-default {
 2721                                 pinmux {
 2722                                         pins = "gpio45", "gpio46";
 2723                                         function = "qup6";
 2724                                 };
 2725                         };
 2726 
 2727                         qup_i2c7_default: qup-i2c7-default {
 2728                                 pinmux {
 2729                                         pins = "gpio93", "gpio94";
 2730                                         function = "qup7";
 2731                                 };
 2732                         };
 2733 
 2734                         qup_i2c8_default: qup-i2c8-default {
 2735                                 pinmux {
 2736                                         pins = "gpio65", "gpio66";
 2737                                         function = "qup8";
 2738                                 };
 2739                         };
 2740 
 2741                         qup_i2c9_default: qup-i2c9-default {
 2742                                 pinmux {
 2743                                         pins = "gpio6", "gpio7";
 2744                                         function = "qup9";
 2745                                 };
 2746                         };
 2747 
 2748                         qup_i2c10_default: qup-i2c10-default {
 2749                                 pinmux {
 2750                                         pins = "gpio55", "gpio56";
 2751                                         function = "qup10";
 2752                                 };
 2753                         };
 2754 
 2755                         qup_i2c11_default: qup-i2c11-default {
 2756                                 pinmux {
 2757                                         pins = "gpio31", "gpio32";
 2758                                         function = "qup11";
 2759                                 };
 2760                         };
 2761 
 2762                         qup_i2c12_default: qup-i2c12-default {
 2763                                 pinmux {
 2764                                         pins = "gpio49", "gpio50";
 2765                                         function = "qup12";
 2766                                 };
 2767                         };
 2768 
 2769                         qup_i2c13_default: qup-i2c13-default {
 2770                                 pinmux {
 2771                                         pins = "gpio105", "gpio106";
 2772                                         function = "qup13";
 2773                                 };
 2774                         };
 2775 
 2776                         qup_i2c14_default: qup-i2c14-default {
 2777                                 pinmux {
 2778                                         pins = "gpio33", "gpio34";
 2779                                         function = "qup14";
 2780                                 };
 2781                         };
 2782 
 2783                         qup_i2c15_default: qup-i2c15-default {
 2784                                 pinmux {
 2785                                         pins = "gpio81", "gpio82";
 2786                                         function = "qup15";
 2787                                 };
 2788                         };
 2789 
 2790                         qup_spi0_default: qup-spi0-default {
 2791                                 pinmux {
 2792                                         pins = "gpio0", "gpio1",
 2793                                                "gpio2", "gpio3";
 2794                                         function = "qup0";
 2795                                 };
 2796 
 2797                                 config {
 2798                                         pins = "gpio0", "gpio1",
 2799                                                "gpio2", "gpio3";
 2800                                         drive-strength = <6>;
 2801                                         bias-disable;
 2802                                 };
 2803                         };
 2804 
 2805                         qup_spi1_default: qup-spi1-default {
 2806                                 pinmux {
 2807                                         pins = "gpio17", "gpio18",
 2808                                                "gpio19", "gpio20";
 2809                                         function = "qup1";
 2810                                 };
 2811                         };
 2812 
 2813                         qup_spi2_default: qup-spi2-default {
 2814                                 pinmux {
 2815                                         pins = "gpio27", "gpio28",
 2816                                                "gpio29", "gpio30";
 2817                                         function = "qup2";
 2818                                 };
 2819                         };
 2820 
 2821                         qup_spi3_default: qup-spi3-default {
 2822                                 pinmux {
 2823                                         pins = "gpio41", "gpio42",
 2824                                                "gpio43", "gpio44";
 2825                                         function = "qup3";
 2826                                 };
 2827                         };
 2828 
 2829                         qup_spi4_default: qup-spi4-default {
 2830                                 pinmux {
 2831                                         pins = "gpio89", "gpio90",
 2832                                                "gpio91", "gpio92";
 2833                                         function = "qup4";
 2834                                 };
 2835                         };
 2836 
 2837                         qup_spi5_default: qup-spi5-default {
 2838                                 pinmux {
 2839                                         pins = "gpio85", "gpio86",
 2840                                                "gpio87", "gpio88";
 2841                                         function = "qup5";
 2842                                 };
 2843                         };
 2844 
 2845                         qup_spi6_default: qup-spi6-default {
 2846                                 pinmux {
 2847                                         pins = "gpio45", "gpio46",
 2848                                                "gpio47", "gpio48";
 2849                                         function = "qup6";
 2850                                 };
 2851                         };
 2852 
 2853                         qup_spi7_default: qup-spi7-default {
 2854                                 pinmux {
 2855                                         pins = "gpio93", "gpio94",
 2856                                                "gpio95", "gpio96";
 2857                                         function = "qup7";
 2858                                 };
 2859                         };
 2860 
 2861                         qup_spi8_default: qup-spi8-default {
 2862                                 pinmux {
 2863                                         pins = "gpio65", "gpio66",
 2864                                                "gpio67", "gpio68";
 2865                                         function = "qup8";
 2866                                 };
 2867                         };
 2868 
 2869                         qup_spi9_default: qup-spi9-default {
 2870                                 pinmux {
 2871                                         pins = "gpio6", "gpio7",
 2872                                                "gpio4", "gpio5";
 2873                                         function = "qup9";
 2874                                 };
 2875                         };
 2876 
 2877                         qup_spi10_default: qup-spi10-default {
 2878                                 pinmux {
 2879                                         pins = "gpio55", "gpio56",
 2880                                                "gpio53", "gpio54";
 2881                                         function = "qup10";
 2882                                 };
 2883                         };
 2884 
 2885                         qup_spi11_default: qup-spi11-default {
 2886                                 pinmux {
 2887                                         pins = "gpio31", "gpio32",
 2888                                                "gpio33", "gpio34";
 2889                                         function = "qup11";
 2890                                 };
 2891                         };
 2892 
 2893                         qup_spi12_default: qup-spi12-default {
 2894                                 pinmux {
 2895                                         pins = "gpio49", "gpio50",
 2896                                                "gpio51", "gpio52";
 2897                                         function = "qup12";
 2898                                 };
 2899                         };
 2900 
 2901                         qup_spi13_default: qup-spi13-default {
 2902                                 pinmux {
 2903                                         pins = "gpio105", "gpio106",
 2904                                                "gpio107", "gpio108";
 2905                                         function = "qup13";
 2906                                 };
 2907                         };
 2908 
 2909                         qup_spi14_default: qup-spi14-default {
 2910                                 pinmux {
 2911                                         pins = "gpio33", "gpio34",
 2912                                                "gpio31", "gpio32";
 2913                                         function = "qup14";
 2914                                 };
 2915                         };
 2916 
 2917                         qup_spi15_default: qup-spi15-default {
 2918                                 pinmux {
 2919                                         pins = "gpio81", "gpio82",
 2920                                                "gpio83", "gpio84";
 2921                                         function = "qup15";
 2922                                 };
 2923                         };
 2924 
 2925                         qup_uart0_default: qup-uart0-default {
 2926                                 pinmux {
 2927                                         pins = "gpio2", "gpio3";
 2928                                         function = "qup0";
 2929                                 };
 2930                         };
 2931 
 2932                         qup_uart1_default: qup-uart1-default {
 2933                                 pinmux {
 2934                                         pins = "gpio19", "gpio20";
 2935                                         function = "qup1";
 2936                                 };
 2937                         };
 2938 
 2939                         qup_uart2_default: qup-uart2-default {
 2940                                 pinmux {
 2941                                         pins = "gpio29", "gpio30";
 2942                                         function = "qup2";
 2943                                 };
 2944                         };
 2945 
 2946                         qup_uart3_default: qup-uart3-default {
 2947                                 pinmux {
 2948                                         pins = "gpio43", "gpio44";
 2949                                         function = "qup3";
 2950                                 };
 2951                         };
 2952 
 2953                         qup_uart4_default: qup-uart4-default {
 2954                                 pinmux {
 2955                                         pins = "gpio91", "gpio92";
 2956                                         function = "qup4";
 2957                                 };
 2958                         };
 2959 
 2960                         qup_uart5_default: qup-uart5-default {
 2961                                 pinmux {
 2962                                         pins = "gpio87", "gpio88";
 2963                                         function = "qup5";
 2964                                 };
 2965                         };
 2966 
 2967                         qup_uart6_default: qup-uart6-default {
 2968                                 pinmux {
 2969                                         pins = "gpio47", "gpio48";
 2970                                         function = "qup6";
 2971                                 };
 2972                         };
 2973 
 2974                         qup_uart7_default: qup-uart7-default {
 2975                                 pinmux {
 2976                                         pins = "gpio95", "gpio96";
 2977                                         function = "qup7";
 2978                                 };
 2979                         };
 2980 
 2981                         qup_uart8_default: qup-uart8-default {
 2982                                 pinmux {
 2983                                         pins = "gpio67", "gpio68";
 2984                                         function = "qup8";
 2985                                 };
 2986                         };
 2987 
 2988                         qup_uart9_default: qup-uart9-default {
 2989                                 pinmux {
 2990                                         pins = "gpio4", "gpio5";
 2991                                         function = "qup9";
 2992                                 };
 2993                         };
 2994 
 2995                         qup_uart10_default: qup-uart10-default {
 2996                                 pinmux {
 2997                                         pins = "gpio53", "gpio54";
 2998                                         function = "qup10";
 2999                                 };
 3000                         };
 3001 
 3002                         qup_uart11_default: qup-uart11-default {
 3003                                 pinmux {
 3004                                         pins = "gpio33", "gpio34";
 3005                                         function = "qup11";
 3006                                 };
 3007                         };
 3008 
 3009                         qup_uart12_default: qup-uart12-default {
 3010                                 pinmux {
 3011                                         pins = "gpio51", "gpio52";
 3012                                         function = "qup12";
 3013                                 };
 3014                         };
 3015 
 3016                         qup_uart13_default: qup-uart13-default {
 3017                                 pinmux {
 3018                                         pins = "gpio107", "gpio108";
 3019                                         function = "qup13";
 3020                                 };
 3021                         };
 3022 
 3023                         qup_uart14_default: qup-uart14-default {
 3024                                 pinmux {
 3025                                         pins = "gpio31", "gpio32";
 3026                                         function = "qup14";
 3027                                 };
 3028                         };
 3029 
 3030                         qup_uart15_default: qup-uart15-default {
 3031                                 pinmux {
 3032                                         pins = "gpio83", "gpio84";
 3033                                         function = "qup15";
 3034                                 };
 3035                         };
 3036 
 3037                         quat_mi2s_sleep: quat_mi2s_sleep {
 3038                                 mux {
 3039                                         pins = "gpio58", "gpio59";
 3040                                         function = "gpio";
 3041                                 };
 3042 
 3043                                 config {
 3044                                         pins = "gpio58", "gpio59";
 3045                                         drive-strength = <2>;
 3046                                         bias-pull-down;
 3047                                         input-enable;
 3048                                 };
 3049                         };
 3050 
 3051                         quat_mi2s_active: quat_mi2s_active {
 3052                                 mux {
 3053                                         pins = "gpio58", "gpio59";
 3054                                         function = "qua_mi2s";
 3055                                 };
 3056 
 3057                                 config {
 3058                                         pins = "gpio58", "gpio59";
 3059                                         drive-strength = <8>;
 3060                                         bias-disable;
 3061                                         output-high;
 3062                                 };
 3063                         };
 3064 
 3065                         quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
 3066                                 mux {
 3067                                         pins = "gpio60";
 3068                                         function = "gpio";
 3069                                 };
 3070 
 3071                                 config {
 3072                                         pins = "gpio60";
 3073                                         drive-strength = <2>;
 3074                                         bias-pull-down;
 3075                                         input-enable;
 3076                                 };
 3077                         };
 3078 
 3079                         quat_mi2s_sd0_active: quat_mi2s_sd0_active {
 3080                                 mux {
 3081                                         pins = "gpio60";
 3082                                         function = "qua_mi2s";
 3083                                 };
 3084 
 3085                                 config {
 3086                                         pins = "gpio60";
 3087                                         drive-strength = <8>;
 3088                                         bias-disable;
 3089                                 };
 3090                         };
 3091 
 3092                         quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
 3093                                 mux {
 3094                                         pins = "gpio61";
 3095                                         function = "gpio";
 3096                                 };
 3097 
 3098                                 config {
 3099                                         pins = "gpio61";
 3100                                         drive-strength = <2>;
 3101                                         bias-pull-down;
 3102                                         input-enable;
 3103                                 };
 3104                         };
 3105 
 3106                         quat_mi2s_sd1_active: quat_mi2s_sd1_active {
 3107                                 mux {
 3108                                         pins = "gpio61";
 3109                                         function = "qua_mi2s";
 3110                                 };
 3111 
 3112                                 config {
 3113                                         pins = "gpio61";
 3114                                         drive-strength = <8>;
 3115                                         bias-disable;
 3116                                 };
 3117                         };
 3118 
 3119                         quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
 3120                                 mux {
 3121                                         pins = "gpio62";
 3122                                         function = "gpio";
 3123                                 };
 3124 
 3125                                 config {
 3126                                         pins = "gpio62";
 3127                                         drive-strength = <2>;
 3128                                         bias-pull-down;
 3129                                         input-enable;
 3130                                 };
 3131                         };
 3132 
 3133                         quat_mi2s_sd2_active: quat_mi2s_sd2_active {
 3134                                 mux {
 3135                                         pins = "gpio62";
 3136                                         function = "qua_mi2s";
 3137                                 };
 3138 
 3139                                 config {
 3140                                         pins = "gpio62";
 3141                                         drive-strength = <8>;
 3142                                         bias-disable;
 3143                                 };
 3144                         };
 3145 
 3146                         quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
 3147                                 mux {
 3148                                         pins = "gpio63";
 3149                                         function = "gpio";
 3150                                 };
 3151 
 3152                                 config {
 3153                                         pins = "gpio63";
 3154                                         drive-strength = <2>;
 3155                                         bias-pull-down;
 3156                                         input-enable;
 3157                                 };
 3158                         };
 3159 
 3160                         quat_mi2s_sd3_active: quat_mi2s_sd3_active {
 3161                                 mux {
 3162                                         pins = "gpio63";
 3163                                         function = "qua_mi2s";
 3164                                 };
 3165 
 3166                                 config {
 3167                                         pins = "gpio63";
 3168                                         drive-strength = <8>;
 3169                                         bias-disable;
 3170                                 };
 3171                         };
 3172                 };
 3173 
 3174                 mss_pil: remoteproc@4080000 {
 3175                         compatible = "qcom,sdm845-mss-pil";
 3176                         reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
 3177                         reg-names = "qdsp6", "rmb";
 3178 
 3179                         interrupts-extended =
 3180                                 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
 3181                                 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 3182                                 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 3183                                 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 3184                                 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
 3185                                 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
 3186                         interrupt-names = "wdog", "fatal", "ready",
 3187                                           "handover", "stop-ack",
 3188                                           "shutdown-ack";
 3189 
 3190                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 3191                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
 3192                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 3193                                  <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
 3194                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
 3195                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
 3196                                  <&gcc GCC_PRNG_AHB_CLK>,
 3197                                  <&rpmhcc RPMH_CXO_CLK>;
 3198                         clock-names = "iface", "bus", "mem", "gpll0_mss",
 3199                                       "snoc_axi", "mnoc_axi", "prng", "xo";
 3200 
 3201                         qcom,qmp = <&aoss_qmp>;
 3202 
 3203                         qcom,smem-states = <&modem_smp2p_out 0>;
 3204                         qcom,smem-state-names = "stop";
 3205 
 3206                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
 3207                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
 3208                         reset-names = "mss_restart", "pdc_reset";
 3209 
 3210                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
 3211 
 3212                         power-domains = <&rpmhpd SDM845_CX>,
 3213                                         <&rpmhpd SDM845_MX>,
 3214                                         <&rpmhpd SDM845_MSS>;
 3215                         power-domain-names = "cx", "mx", "mss";
 3216 
 3217                         status = "disabled";
 3218 
 3219                         mba {
 3220                                 memory-region = <&mba_region>;
 3221                         };
 3222 
 3223                         mpss {
 3224                                 memory-region = <&mpss_region>;
 3225                         };
 3226 
 3227                         glink-edge {
 3228                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
 3229                                 label = "modem";
 3230                                 qcom,remote-pid = <1>;
 3231                                 mboxes = <&apss_shared 12>;
 3232                         };
 3233                 };
 3234 
 3235                 gpucc: clock-controller@5090000 {
 3236                         compatible = "qcom,sdm845-gpucc";
 3237                         reg = <0 0x05090000 0 0x9000>;
 3238                         #clock-cells = <1>;
 3239                         #reset-cells = <1>;
 3240                         #power-domain-cells = <1>;
 3241                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 3242                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
 3243                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
 3244                         clock-names = "bi_tcxo",
 3245                                       "gcc_gpu_gpll0_clk_src",
 3246                                       "gcc_gpu_gpll0_div_clk_src";
 3247                 };
 3248 
 3249                 stm@6002000 {
 3250                         compatible = "arm,coresight-stm", "arm,primecell";
 3251                         reg = <0 0x06002000 0 0x1000>,
 3252                               <0 0x16280000 0 0x180000>;
 3253                         reg-names = "stm-base", "stm-stimulus-base";
 3254 
 3255                         clocks = <&aoss_qmp>;
 3256                         clock-names = "apb_pclk";
 3257 
 3258                         out-ports {
 3259                                 port {
 3260                                         stm_out: endpoint {
 3261                                                 remote-endpoint =
 3262                                                   <&funnel0_in7>;
 3263                                         };
 3264                                 };
 3265                         };
 3266                 };
 3267 
 3268                 funnel@6041000 {
 3269                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 3270                         reg = <0 0x06041000 0 0x1000>;
 3271 
 3272                         clocks = <&aoss_qmp>;
 3273                         clock-names = "apb_pclk";
 3274 
 3275                         out-ports {
 3276                                 port {
 3277                                         funnel0_out: endpoint {
 3278                                                 remote-endpoint =
 3279                                                   <&merge_funnel_in0>;
 3280                                         };
 3281                                 };
 3282                         };
 3283 
 3284                         in-ports {
 3285                                 #address-cells = <1>;
 3286                                 #size-cells = <0>;
 3287 
 3288                                 port@7 {
 3289                                         reg = <7>;
 3290                                         funnel0_in7: endpoint {
 3291                                                 remote-endpoint = <&stm_out>;
 3292                                         };
 3293                                 };
 3294                         };
 3295                 };
 3296 
 3297                 funnel@6043000 {
 3298                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 3299                         reg = <0 0x06043000 0 0x1000>;
 3300 
 3301                         clocks = <&aoss_qmp>;
 3302                         clock-names = "apb_pclk";
 3303 
 3304                         out-ports {
 3305                                 port {
 3306                                         funnel2_out: endpoint {
 3307                                                 remote-endpoint =
 3308                                                   <&merge_funnel_in2>;
 3309                                         };
 3310                                 };
 3311                         };
 3312 
 3313                         in-ports {
 3314                                 #address-cells = <1>;
 3315                                 #size-cells = <0>;
 3316 
 3317                                 port@5 {
 3318                                         reg = <5>;
 3319                                         funnel2_in5: endpoint {
 3320                                                 remote-endpoint =
 3321                                                   <&apss_merge_funnel_out>;
 3322                                         };
 3323                                 };
 3324                         };
 3325                 };
 3326 
 3327                 funnel@6045000 {
 3328                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 3329                         reg = <0 0x06045000 0 0x1000>;
 3330 
 3331                         clocks = <&aoss_qmp>;
 3332                         clock-names = "apb_pclk";
 3333 
 3334                         out-ports {
 3335                                 port {
 3336                                         merge_funnel_out: endpoint {
 3337                                                 remote-endpoint = <&etf_in>;
 3338                                         };
 3339                                 };
 3340                         };
 3341 
 3342                         in-ports {
 3343                                 #address-cells = <1>;
 3344                                 #size-cells = <0>;
 3345 
 3346                                 port@0 {
 3347                                         reg = <0>;
 3348                                         merge_funnel_in0: endpoint {
 3349                                                 remote-endpoint =
 3350                                                   <&funnel0_out>;
 3351                                         };
 3352                                 };
 3353 
 3354                                 port@2 {
 3355                                         reg = <2>;
 3356                                         merge_funnel_in2: endpoint {
 3357                                                 remote-endpoint =
 3358                                                   <&funnel2_out>;
 3359                                         };
 3360                                 };
 3361                         };
 3362                 };
 3363 
 3364                 replicator@6046000 {
 3365                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
 3366                         reg = <0 0x06046000 0 0x1000>;
 3367 
 3368                         clocks = <&aoss_qmp>;
 3369                         clock-names = "apb_pclk";
 3370 
 3371                         out-ports {
 3372                                 port {
 3373                                         replicator_out: endpoint {
 3374                                                 remote-endpoint = <&etr_in>;
 3375                                         };
 3376                                 };
 3377                         };
 3378 
 3379                         in-ports {
 3380                                 port {
 3381                                         replicator_in: endpoint {
 3382                                                 remote-endpoint = <&etf_out>;
 3383                                         };
 3384                                 };
 3385                         };
 3386                 };
 3387 
 3388                 etf@6047000 {
 3389                         compatible = "arm,coresight-tmc", "arm,primecell";
 3390                         reg = <0 0x06047000 0 0x1000>;
 3391 
 3392                         clocks = <&aoss_qmp>;
 3393                         clock-names = "apb_pclk";
 3394 
 3395                         out-ports {
 3396                                 port {
 3397                                         etf_out: endpoint {
 3398                                                 remote-endpoint =
 3399                                                   <&replicator_in>;
 3400                                         };
 3401                                 };
 3402                         };
 3403 
 3404                         in-ports {
 3405                                 #address-cells = <1>;
 3406                                 #size-cells = <0>;
 3407 
 3408                                 port@1 {
 3409                                         reg = <1>;
 3410                                         etf_in: endpoint {
 3411                                                 remote-endpoint =
 3412                                                   <&merge_funnel_out>;
 3413                                         };
 3414                                 };
 3415                         };
 3416                 };
 3417 
 3418                 etr@6048000 {
 3419                         compatible = "arm,coresight-tmc", "arm,primecell";
 3420                         reg = <0 0x06048000 0 0x1000>;
 3421 
 3422                         clocks = <&aoss_qmp>;
 3423                         clock-names = "apb_pclk";
 3424                         arm,scatter-gather;
 3425 
 3426                         in-ports {
 3427                                 port {
 3428                                         etr_in: endpoint {
 3429                                                 remote-endpoint =
 3430                                                   <&replicator_out>;
 3431                                         };
 3432                                 };
 3433                         };
 3434                 };
 3435 
 3436                 etm@7040000 {
 3437                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3438                         reg = <0 0x07040000 0 0x1000>;
 3439 
 3440                         cpu = <&CPU0>;
 3441 
 3442                         clocks = <&aoss_qmp>;
 3443                         clock-names = "apb_pclk";
 3444                         arm,coresight-loses-context-with-cpu;
 3445 
 3446                         out-ports {
 3447                                 port {
 3448                                         etm0_out: endpoint {
 3449                                                 remote-endpoint =
 3450                                                   <&apss_funnel_in0>;
 3451                                         };
 3452                                 };
 3453                         };
 3454                 };
 3455 
 3456                 etm@7140000 {
 3457                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3458                         reg = <0 0x07140000 0 0x1000>;
 3459 
 3460                         cpu = <&CPU1>;
 3461 
 3462                         clocks = <&aoss_qmp>;
 3463                         clock-names = "apb_pclk";
 3464                         arm,coresight-loses-context-with-cpu;
 3465 
 3466                         out-ports {
 3467                                 port {
 3468                                         etm1_out: endpoint {
 3469                                                 remote-endpoint =
 3470                                                   <&apss_funnel_in1>;
 3471                                         };
 3472                                 };
 3473                         };
 3474                 };
 3475 
 3476                 etm@7240000 {
 3477                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3478                         reg = <0 0x07240000 0 0x1000>;
 3479 
 3480                         cpu = <&CPU2>;
 3481 
 3482                         clocks = <&aoss_qmp>;
 3483                         clock-names = "apb_pclk";
 3484                         arm,coresight-loses-context-with-cpu;
 3485 
 3486                         out-ports {
 3487                                 port {
 3488                                         etm2_out: endpoint {
 3489                                                 remote-endpoint =
 3490                                                   <&apss_funnel_in2>;
 3491                                         };
 3492                                 };
 3493                         };
 3494                 };
 3495 
 3496                 etm@7340000 {
 3497                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3498                         reg = <0 0x07340000 0 0x1000>;
 3499 
 3500                         cpu = <&CPU3>;
 3501 
 3502                         clocks = <&aoss_qmp>;
 3503                         clock-names = "apb_pclk";
 3504                         arm,coresight-loses-context-with-cpu;
 3505 
 3506                         out-ports {
 3507                                 port {
 3508                                         etm3_out: endpoint {
 3509                                                 remote-endpoint =
 3510                                                   <&apss_funnel_in3>;
 3511                                         };
 3512                                 };
 3513                         };
 3514                 };
 3515 
 3516                 etm@7440000 {
 3517                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3518                         reg = <0 0x07440000 0 0x1000>;
 3519 
 3520                         cpu = <&CPU4>;
 3521 
 3522                         clocks = <&aoss_qmp>;
 3523                         clock-names = "apb_pclk";
 3524                         arm,coresight-loses-context-with-cpu;
 3525 
 3526                         out-ports {
 3527                                 port {
 3528                                         etm4_out: endpoint {
 3529                                                 remote-endpoint =
 3530                                                   <&apss_funnel_in4>;
 3531                                         };
 3532                                 };
 3533                         };
 3534                 };
 3535 
 3536                 etm@7540000 {
 3537                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3538                         reg = <0 0x07540000 0 0x1000>;
 3539 
 3540                         cpu = <&CPU5>;
 3541 
 3542                         clocks = <&aoss_qmp>;
 3543                         clock-names = "apb_pclk";
 3544                         arm,coresight-loses-context-with-cpu;
 3545 
 3546                         out-ports {
 3547                                 port {
 3548                                         etm5_out: endpoint {
 3549                                                 remote-endpoint =
 3550                                                   <&apss_funnel_in5>;
 3551                                         };
 3552                                 };
 3553                         };
 3554                 };
 3555 
 3556                 etm@7640000 {
 3557                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3558                         reg = <0 0x07640000 0 0x1000>;
 3559 
 3560                         cpu = <&CPU6>;
 3561 
 3562                         clocks = <&aoss_qmp>;
 3563                         clock-names = "apb_pclk";
 3564                         arm,coresight-loses-context-with-cpu;
 3565 
 3566                         out-ports {
 3567                                 port {
 3568                                         etm6_out: endpoint {
 3569                                                 remote-endpoint =
 3570                                                   <&apss_funnel_in6>;
 3571                                         };
 3572                                 };
 3573                         };
 3574                 };
 3575 
 3576                 etm@7740000 {
 3577                         compatible = "arm,coresight-etm4x", "arm,primecell";
 3578                         reg = <0 0x07740000 0 0x1000>;
 3579 
 3580                         cpu = <&CPU7>;
 3581 
 3582                         clocks = <&aoss_qmp>;
 3583                         clock-names = "apb_pclk";
 3584                         arm,coresight-loses-context-with-cpu;
 3585 
 3586                         out-ports {
 3587                                 port {
 3588                                         etm7_out: endpoint {
 3589                                                 remote-endpoint =
 3590                                                   <&apss_funnel_in7>;
 3591                                         };
 3592                                 };
 3593                         };
 3594                 };
 3595 
 3596                 funnel@7800000 { /* APSS Funnel */
 3597                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 3598                         reg = <0 0x07800000 0 0x1000>;
 3599 
 3600                         clocks = <&aoss_qmp>;
 3601                         clock-names = "apb_pclk";
 3602 
 3603                         out-ports {
 3604                                 port {
 3605                                         apss_funnel_out: endpoint {
 3606                                                 remote-endpoint =
 3607                                                   <&apss_merge_funnel_in>;
 3608                                         };
 3609                                 };
 3610                         };
 3611 
 3612                         in-ports {
 3613                                 #address-cells = <1>;
 3614                                 #size-cells = <0>;
 3615 
 3616                                 port@0 {
 3617                                         reg = <0>;
 3618                                         apss_funnel_in0: endpoint {
 3619                                                 remote-endpoint =
 3620                                                   <&etm0_out>;
 3621                                         };
 3622                                 };
 3623 
 3624                                 port@1 {
 3625                                         reg = <1>;
 3626                                         apss_funnel_in1: endpoint {
 3627                                                 remote-endpoint =
 3628                                                   <&etm1_out>;
 3629                                         };
 3630                                 };
 3631 
 3632                                 port@2 {
 3633                                         reg = <2>;
 3634                                         apss_funnel_in2: endpoint {
 3635                                                 remote-endpoint =
 3636                                                   <&etm2_out>;
 3637                                         };
 3638                                 };
 3639 
 3640                                 port@3 {
 3641                                         reg = <3>;
 3642                                         apss_funnel_in3: endpoint {
 3643                                                 remote-endpoint =
 3644                                                   <&etm3_out>;
 3645                                         };
 3646                                 };
 3647 
 3648                                 port@4 {
 3649                                         reg = <4>;
 3650                                         apss_funnel_in4: endpoint {
 3651                                                 remote-endpoint =
 3652                                                   <&etm4_out>;
 3653                                         };
 3654                                 };
 3655 
 3656                                 port@5 {
 3657                                         reg = <5>;
 3658                                         apss_funnel_in5: endpoint {
 3659                                                 remote-endpoint =
 3660                                                   <&etm5_out>;
 3661                                         };
 3662                                 };
 3663 
 3664                                 port@6 {
 3665                                         reg = <6>;
 3666                                         apss_funnel_in6: endpoint {
 3667                                                 remote-endpoint =
 3668                                                   <&etm6_out>;
 3669                                         };
 3670                                 };
 3671 
 3672                                 port@7 {
 3673                                         reg = <7>;
 3674                                         apss_funnel_in7: endpoint {
 3675                                                 remote-endpoint =
 3676                                                   <&etm7_out>;
 3677                                         };
 3678                                 };
 3679                         };
 3680                 };
 3681 
 3682                 funnel@7810000 {
 3683                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 3684                         reg = <0 0x07810000 0 0x1000>;
 3685 
 3686                         clocks = <&aoss_qmp>;
 3687                         clock-names = "apb_pclk";
 3688 
 3689                         out-ports {
 3690                                 port {
 3691                                         apss_merge_funnel_out: endpoint {
 3692                                                 remote-endpoint =
 3693                                                   <&funnel2_in5>;
 3694                                         };
 3695                                 };
 3696                         };
 3697 
 3698                         in-ports {
 3699                                 port {
 3700                                         apss_merge_funnel_in: endpoint {
 3701                                                 remote-endpoint =
 3702                                                   <&apss_funnel_out>;
 3703                                         };
 3704                                 };
 3705                         };
 3706                 };
 3707 
 3708                 sdhc_2: mmc@8804000 {
 3709                         compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
 3710                         reg = <0 0x08804000 0 0x1000>;
 3711 
 3712                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 3713                                      <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 3714                         interrupt-names = "hc_irq", "pwr_irq";
 3715 
 3716                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 3717                                  <&gcc GCC_SDCC2_APPS_CLK>,
 3718                                  <&rpmhcc RPMH_CXO_CLK>;
 3719                         clock-names = "iface", "core", "xo";
 3720                         iommus = <&apps_smmu 0xa0 0xf>;
 3721                         power-domains = <&rpmhpd SDM845_CX>;
 3722                         operating-points-v2 = <&sdhc2_opp_table>;
 3723 
 3724                         status = "disabled";
 3725 
 3726                         sdhc2_opp_table: opp-table {
 3727                                 compatible = "operating-points-v2";
 3728 
 3729                                 opp-9600000 {
 3730                                         opp-hz = /bits/ 64 <9600000>;
 3731                                         required-opps = <&rpmhpd_opp_min_svs>;
 3732                                 };
 3733 
 3734                                 opp-19200000 {
 3735                                         opp-hz = /bits/ 64 <19200000>;
 3736                                         required-opps = <&rpmhpd_opp_low_svs>;
 3737                                 };
 3738 
 3739                                 opp-100000000 {
 3740                                         opp-hz = /bits/ 64 <100000000>;
 3741                                         required-opps = <&rpmhpd_opp_svs>;
 3742                                 };
 3743 
 3744                                 opp-201500000 {
 3745                                         opp-hz = /bits/ 64 <201500000>;
 3746                                         required-opps = <&rpmhpd_opp_svs_l1>;
 3747                                 };
 3748                         };
 3749                 };
 3750 
 3751                 qspi_opp_table: opp-table-qspi {
 3752                         compatible = "operating-points-v2";
 3753 
 3754                         opp-19200000 {
 3755                                 opp-hz = /bits/ 64 <19200000>;
 3756                                 required-opps = <&rpmhpd_opp_min_svs>;
 3757                         };
 3758 
 3759                         opp-100000000 {
 3760                                 opp-hz = /bits/ 64 <100000000>;
 3761                                 required-opps = <&rpmhpd_opp_low_svs>;
 3762                         };
 3763 
 3764                         opp-150000000 {
 3765                                 opp-hz = /bits/ 64 <150000000>;
 3766                                 required-opps = <&rpmhpd_opp_svs>;
 3767                         };
 3768 
 3769                         opp-300000000 {
 3770                                 opp-hz = /bits/ 64 <300000000>;
 3771                                 required-opps = <&rpmhpd_opp_nom>;
 3772                         };
 3773                 };
 3774 
 3775                 qspi: spi@88df000 {
 3776                         compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
 3777                         reg = <0 0x088df000 0 0x600>;
 3778                         #address-cells = <1>;
 3779                         #size-cells = <0>;
 3780                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 3781                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
 3782                                  <&gcc GCC_QSPI_CORE_CLK>;
 3783                         clock-names = "iface", "core";
 3784                         power-domains = <&rpmhpd SDM845_CX>;
 3785                         operating-points-v2 = <&qspi_opp_table>;
 3786                         status = "disabled";
 3787                 };
 3788 
 3789                 slim: slim@171c0000 {
 3790                         compatible = "qcom,slim-ngd-v2.1.0";
 3791                         reg = <0 0x171c0000 0 0x2c000>;
 3792                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 3793 
 3794                         qcom,apps-ch-pipes = <0x780000>;
 3795                         qcom,ea-pc = <0x270>;
 3796                         status = "okay";
 3797                         dmas = <&slimbam 3>, <&slimbam 4>,
 3798                                 <&slimbam 5>, <&slimbam 6>;
 3799                         dma-names = "rx", "tx", "tx2", "rx2";
 3800 
 3801                         iommus = <&apps_smmu 0x1806 0x0>;
 3802                         #address-cells = <1>;
 3803                         #size-cells = <0>;
 3804 
 3805                         ngd@1 {
 3806                                 reg = <1>;
 3807                                 #address-cells = <2>;
 3808                                 #size-cells = <0>;
 3809 
 3810                                 wcd9340_ifd: ifd@0{
 3811                                         compatible = "slim217,250";
 3812                                         reg = <0 0>;
 3813                                 };
 3814 
 3815                                 wcd9340: codec@1{
 3816                                         compatible = "slim217,250";
 3817                                         reg = <1 0>;
 3818                                         slim-ifc-dev = <&wcd9340_ifd>;
 3819 
 3820                                         #sound-dai-cells = <1>;
 3821 
 3822                                         interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>;
 3823                                         interrupt-controller;
 3824                                         #interrupt-cells = <1>;
 3825 
 3826                                         #clock-cells = <0>;
 3827                                         clock-frequency = <9600000>;
 3828                                         clock-output-names = "mclk";
 3829                                         qcom,micbias1-microvolt = <1800000>;
 3830                                         qcom,micbias2-microvolt = <1800000>;
 3831                                         qcom,micbias3-microvolt = <1800000>;
 3832                                         qcom,micbias4-microvolt = <1800000>;
 3833 
 3834                                         #address-cells = <1>;
 3835                                         #size-cells = <1>;
 3836 
 3837                                         wcdgpio: gpio-controller@42 {
 3838                                                 compatible = "qcom,wcd9340-gpio";
 3839                                                 gpio-controller;
 3840                                                 #gpio-cells = <2>;
 3841                                                 reg = <0x42 0x2>;
 3842                                         };
 3843 
 3844                                         swm: swm@c85 {
 3845                                                 compatible = "qcom,soundwire-v1.3.0";
 3846                                                 reg = <0xc85 0x40>;
 3847                                                 interrupts-extended = <&wcd9340 20>;
 3848 
 3849                                                 qcom,dout-ports = <6>;
 3850                                                 qcom,din-ports = <2>;
 3851                                                 qcom,ports-sinterval-low =/bits/ 8  <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
 3852                                                 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
 3853                                                 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>;
 3854 
 3855                                                 #sound-dai-cells = <1>;
 3856                                                 clocks = <&wcd9340>;
 3857                                                 clock-names = "iface";
 3858                                                 #address-cells = <2>;
 3859                                                 #size-cells = <0>;
 3860 
 3861 
 3862                                         };
 3863                                 };
 3864                         };
 3865                 };
 3866 
 3867                 lmh_cluster1: lmh@17d70800 {
 3868                         compatible = "qcom,sdm845-lmh";
 3869                         reg = <0 0x17d70800 0 0x400>;
 3870                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 3871                         cpus = <&CPU4>;
 3872                         qcom,lmh-temp-arm-millicelsius = <65000>;
 3873                         qcom,lmh-temp-low-millicelsius = <94500>;
 3874                         qcom,lmh-temp-high-millicelsius = <95000>;
 3875                         interrupt-controller;
 3876                         #interrupt-cells = <1>;
 3877                 };
 3878 
 3879                 lmh_cluster0: lmh@17d78800 {
 3880                         compatible = "qcom,sdm845-lmh";
 3881                         reg = <0 0x17d78800 0 0x400>;
 3882                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 3883                         cpus = <&CPU0>;
 3884                         qcom,lmh-temp-arm-millicelsius = <65000>;
 3885                         qcom,lmh-temp-low-millicelsius = <94500>;
 3886                         qcom,lmh-temp-high-millicelsius = <95000>;
 3887                         interrupt-controller;
 3888                         #interrupt-cells = <1>;
 3889                 };
 3890 
 3891                 sound: sound {
 3892                 };
 3893 
 3894                 usb_1_hsphy: phy@88e2000 {
 3895                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
 3896                         reg = <0 0x088e2000 0 0x400>;
 3897                         status = "disabled";
 3898                         #phy-cells = <0>;
 3899 
 3900                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 3901                                  <&rpmhcc RPMH_CXO_CLK>;
 3902                         clock-names = "cfg_ahb", "ref";
 3903 
 3904                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 3905 
 3906                         nvmem-cells = <&qusb2p_hstx_trim>;
 3907                 };
 3908 
 3909                 usb_2_hsphy: phy@88e3000 {
 3910                         compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy";
 3911                         reg = <0 0x088e3000 0 0x400>;
 3912                         status = "disabled";
 3913                         #phy-cells = <0>;
 3914 
 3915                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 3916                                  <&rpmhcc RPMH_CXO_CLK>;
 3917                         clock-names = "cfg_ahb", "ref";
 3918 
 3919                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 3920 
 3921                         nvmem-cells = <&qusb2s_hstx_trim>;
 3922                 };
 3923 
 3924                 usb_1_qmpphy: phy@88e9000 {
 3925                         compatible = "qcom,sdm845-qmp-usb3-phy";
 3926                         reg = <0 0x088e9000 0 0x18c>,
 3927                               <0 0x088e8000 0 0x10>;
 3928                         status = "disabled";
 3929                         #address-cells = <2>;
 3930                         #size-cells = <2>;
 3931                         ranges;
 3932 
 3933                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 3934                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 3935                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 3936                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 3937                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 3938 
 3939                         resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
 3940                                  <&gcc GCC_USB3_PHY_PRIM_BCR>;
 3941                         reset-names = "phy", "common";
 3942 
 3943                         usb_1_ssphy: phy@88e9200 {
 3944                                 reg = <0 0x088e9200 0 0x128>,
 3945                                       <0 0x088e9400 0 0x200>,
 3946                                       <0 0x088e9c00 0 0x218>,
 3947                                       <0 0x088e9600 0 0x128>,
 3948                                       <0 0x088e9800 0 0x200>,
 3949                                       <0 0x088e9a00 0 0x100>;
 3950                                 #clock-cells = <0>;
 3951                                 #phy-cells = <0>;
 3952                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 3953                                 clock-names = "pipe0";
 3954                                 clock-output-names = "usb3_phy_pipe_clk_src";
 3955                         };
 3956                 };
 3957 
 3958                 usb_2_qmpphy: phy@88eb000 {
 3959                         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
 3960                         reg = <0 0x088eb000 0 0x18c>;
 3961                         status = "disabled";
 3962                         #address-cells = <2>;
 3963                         #size-cells = <2>;
 3964                         ranges;
 3965 
 3966                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
 3967                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 3968                                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
 3969                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
 3970                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 3971 
 3972                         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
 3973                                  <&gcc GCC_USB3_PHY_SEC_BCR>;
 3974                         reset-names = "phy", "common";
 3975 
 3976                         usb_2_ssphy: phy@88eb200 {
 3977                                 reg = <0 0x088eb200 0 0x128>,
 3978                                       <0 0x088eb400 0 0x1fc>,
 3979                                       <0 0x088eb800 0 0x218>,
 3980                                       <0 0x088eb600 0 0x70>;
 3981                                 #clock-cells = <0>;
 3982                                 #phy-cells = <0>;
 3983                                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
 3984                                 clock-names = "pipe0";
 3985                                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
 3986                         };
 3987                 };
 3988 
 3989                 usb_1: usb@a6f8800 {
 3990                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
 3991                         reg = <0 0x0a6f8800 0 0x400>;
 3992                         status = "disabled";
 3993                         #address-cells = <2>;
 3994                         #size-cells = <2>;
 3995                         ranges;
 3996                         dma-ranges;
 3997 
 3998                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
 3999                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 4000                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
 4001                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
 4002                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
 4003                         clock-names = "cfg_noc",
 4004                                       "core",
 4005                                       "iface",
 4006                                       "sleep",
 4007                                       "mock_utmi";
 4008 
 4009                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 4010                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 4011                         assigned-clock-rates = <19200000>, <150000000>;
 4012 
 4013                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 4014                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
 4015                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
 4016                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
 4017                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
 4018                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
 4019 
 4020                         power-domains = <&gcc USB30_PRIM_GDSC>;
 4021 
 4022                         resets = <&gcc GCC_USB30_PRIM_BCR>;
 4023 
 4024                         interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>,
 4025                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
 4026                         interconnect-names = "usb-ddr", "apps-usb";
 4027 
 4028                         usb_1_dwc3: usb@a600000 {
 4029                                 compatible = "snps,dwc3";
 4030                                 reg = <0 0x0a600000 0 0xcd00>;
 4031                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 4032                                 iommus = <&apps_smmu 0x740 0>;
 4033                                 snps,dis_u2_susphy_quirk;
 4034                                 snps,dis_enblslpm_quirk;
 4035                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
 4036                                 phy-names = "usb2-phy", "usb3-phy";
 4037                         };
 4038                 };
 4039 
 4040                 usb_2: usb@a8f8800 {
 4041                         compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
 4042                         reg = <0 0x0a8f8800 0 0x400>;
 4043                         status = "disabled";
 4044                         #address-cells = <2>;
 4045                         #size-cells = <2>;
 4046                         ranges;
 4047                         dma-ranges;
 4048 
 4049                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
 4050                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
 4051                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
 4052                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
 4053                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
 4054                         clock-names = "cfg_noc",
 4055                                       "core",
 4056                                       "iface",
 4057                                       "sleep",
 4058                                       "mock_utmi";
 4059 
 4060                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
 4061                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
 4062                         assigned-clock-rates = <19200000>, <150000000>;
 4063 
 4064                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 4065                                      <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>,
 4066                                      <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
 4067                                      <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
 4068                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
 4069                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
 4070 
 4071                         power-domains = <&gcc USB30_SEC_GDSC>;
 4072 
 4073                         resets = <&gcc GCC_USB30_SEC_BCR>;
 4074 
 4075                         interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>,
 4076                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
 4077                         interconnect-names = "usb-ddr", "apps-usb";
 4078 
 4079                         usb_2_dwc3: usb@a800000 {
 4080                                 compatible = "snps,dwc3";
 4081                                 reg = <0 0x0a800000 0 0xcd00>;
 4082                                 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 4083                                 iommus = <&apps_smmu 0x760 0>;
 4084                                 snps,dis_u2_susphy_quirk;
 4085                                 snps,dis_enblslpm_quirk;
 4086                                 phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
 4087                                 phy-names = "usb2-phy", "usb3-phy";
 4088                         };
 4089                 };
 4090 
 4091                 venus: video-codec@aa00000 {
 4092                         compatible = "qcom,sdm845-venus-v2";
 4093                         reg = <0 0x0aa00000 0 0xff000>;
 4094                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 4095                         power-domains = <&videocc VENUS_GDSC>,
 4096                                         <&videocc VCODEC0_GDSC>,
 4097                                         <&videocc VCODEC1_GDSC>,
 4098                                         <&rpmhpd SDM845_CX>;
 4099                         power-domain-names = "venus", "vcodec0", "vcodec1", "cx";
 4100                         operating-points-v2 = <&venus_opp_table>;
 4101                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
 4102                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
 4103                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
 4104                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
 4105                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
 4106                                  <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
 4107                                  <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
 4108                         clock-names = "core", "iface", "bus",
 4109                                       "vcodec0_core", "vcodec0_bus",
 4110                                       "vcodec1_core", "vcodec1_bus";
 4111                         iommus = <&apps_smmu 0x10a0 0x8>,
 4112                                  <&apps_smmu 0x10b0 0x0>;
 4113                         memory-region = <&venus_mem>;
 4114                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>,
 4115                                         <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
 4116                         interconnect-names = "video-mem", "cpu-cfg";
 4117 
 4118                         status = "disabled";
 4119 
 4120                         video-core0 {
 4121                                 compatible = "venus-decoder";
 4122                         };
 4123 
 4124                         video-core1 {
 4125                                 compatible = "venus-encoder";
 4126                         };
 4127 
 4128                         venus_opp_table: opp-table {
 4129                                 compatible = "operating-points-v2";
 4130 
 4131                                 opp-100000000 {
 4132                                         opp-hz = /bits/ 64 <100000000>;
 4133                                         required-opps = <&rpmhpd_opp_min_svs>;
 4134                                 };
 4135 
 4136                                 opp-200000000 {
 4137                                         opp-hz = /bits/ 64 <200000000>;
 4138                                         required-opps = <&rpmhpd_opp_low_svs>;
 4139                                 };
 4140 
 4141                                 opp-320000000 {
 4142                                         opp-hz = /bits/ 64 <320000000>;
 4143                                         required-opps = <&rpmhpd_opp_svs>;
 4144                                 };
 4145 
 4146                                 opp-380000000 {
 4147                                         opp-hz = /bits/ 64 <380000000>;
 4148                                         required-opps = <&rpmhpd_opp_svs_l1>;
 4149                                 };
 4150 
 4151                                 opp-444000000 {
 4152                                         opp-hz = /bits/ 64 <444000000>;
 4153                                         required-opps = <&rpmhpd_opp_nom>;
 4154                                 };
 4155 
 4156                                 opp-533000097 {
 4157                                         opp-hz = /bits/ 64 <533000097>;
 4158                                         required-opps = <&rpmhpd_opp_turbo>;
 4159                                 };
 4160                         };
 4161                 };
 4162 
 4163                 videocc: clock-controller@ab00000 {
 4164                         compatible = "qcom,sdm845-videocc";
 4165                         reg = <0 0x0ab00000 0 0x10000>;
 4166                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 4167                         clock-names = "bi_tcxo";
 4168                         #clock-cells = <1>;
 4169                         #power-domain-cells = <1>;
 4170                         #reset-cells = <1>;
 4171                 };
 4172 
 4173                 camss: camss@a00000 {
 4174                         compatible = "qcom,sdm845-camss";
 4175 
 4176                         reg = <0 0xacb3000 0 0x1000>,
 4177                                 <0 0xacba000 0 0x1000>,
 4178                                 <0 0xacc8000 0 0x1000>,
 4179                                 <0 0xac65000 0 0x1000>,
 4180                                 <0 0xac66000 0 0x1000>,
 4181                                 <0 0xac67000 0 0x1000>,
 4182                                 <0 0xac68000 0 0x1000>,
 4183                                 <0 0xacaf000 0 0x4000>,
 4184                                 <0 0xacb6000 0 0x4000>,
 4185                                 <0 0xacc4000 0 0x4000>;
 4186                         reg-names = "csid0",
 4187                                 "csid1",
 4188                                 "csid2",
 4189                                 "csiphy0",
 4190                                 "csiphy1",
 4191                                 "csiphy2",
 4192                                 "csiphy3",
 4193                                 "vfe0",
 4194                                 "vfe1",
 4195                                 "vfe_lite";
 4196 
 4197                         interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
 4198                                 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
 4199                                 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
 4200                                 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
 4201                                 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
 4202                                 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
 4203                                 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
 4204                                 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
 4205                                 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
 4206                                 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
 4207                         interrupt-names = "csid0",
 4208                                 "csid1",
 4209                                 "csid2",
 4210                                 "csiphy0",
 4211                                 "csiphy1",
 4212                                 "csiphy2",
 4213                                 "csiphy3",
 4214                                 "vfe0",
 4215                                 "vfe1",
 4216                                 "vfe_lite";
 4217 
 4218                         power-domains = <&clock_camcc IFE_0_GDSC>,
 4219                                 <&clock_camcc IFE_1_GDSC>,
 4220                                 <&clock_camcc TITAN_TOP_GDSC>;
 4221 
 4222                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
 4223                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
 4224                                 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
 4225                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
 4226                                 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
 4227                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
 4228                                 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
 4229                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
 4230                                 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
 4231                                 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
 4232                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
 4233                                 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
 4234                                 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
 4235                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
 4236                                 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
 4237                                 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
 4238                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
 4239                                 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
 4240                                 <&clock_camcc CAM_CC_CSIPHY3_CLK>,
 4241                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
 4242                                 <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
 4243                                 <&gcc GCC_CAMERA_AHB_CLK>,
 4244                                 <&gcc GCC_CAMERA_AXI_CLK>,
 4245                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
 4246                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
 4247                                 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
 4248                                 <&clock_camcc CAM_CC_IFE_0_CLK>,
 4249                                 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
 4250                                 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
 4251                                 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
 4252                                 <&clock_camcc CAM_CC_IFE_1_CLK>,
 4253                                 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
 4254                                 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
 4255                                 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
 4256                                 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
 4257                                 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
 4258                         clock-names = "camnoc_axi",
 4259                                 "cpas_ahb",
 4260                                 "cphy_rx_src",
 4261                                 "csi0",
 4262                                 "csi0_src",
 4263                                 "csi1",
 4264                                 "csi1_src",
 4265                                 "csi2",
 4266                                 "csi2_src",
 4267                                 "csiphy0",
 4268                                 "csiphy0_timer",
 4269                                 "csiphy0_timer_src",
 4270                                 "csiphy1",
 4271                                 "csiphy1_timer",
 4272                                 "csiphy1_timer_src",
 4273                                 "csiphy2",
 4274                                 "csiphy2_timer",
 4275                                 "csiphy2_timer_src",
 4276                                 "csiphy3",
 4277                                 "csiphy3_timer",
 4278                                 "csiphy3_timer_src",
 4279                                 "gcc_camera_ahb",
 4280                                 "gcc_camera_axi",
 4281                                 "slow_ahb_src",
 4282                                 "soc_ahb",
 4283                                 "vfe0_axi",
 4284                                 "vfe0",
 4285                                 "vfe0_cphy_rx",
 4286                                 "vfe0_src",
 4287                                 "vfe1_axi",
 4288                                 "vfe1",
 4289                                 "vfe1_cphy_rx",
 4290                                 "vfe1_src",
 4291                                 "vfe_lite",
 4292                                 "vfe_lite_cphy_rx",
 4293                                 "vfe_lite_src";
 4294 
 4295                         iommus = <&apps_smmu 0x0808 0x0>,
 4296                                  <&apps_smmu 0x0810 0x8>,
 4297                                  <&apps_smmu 0x0c08 0x0>,
 4298                                  <&apps_smmu 0x0c10 0x8>;
 4299 
 4300                         status = "disabled";
 4301 
 4302                         ports {
 4303                                 #address-cells = <1>;
 4304                                 #size-cells = <0>;
 4305                         };
 4306                 };
 4307 
 4308                 cci: cci@ac4a000 {
 4309                         compatible = "qcom,sdm845-cci";
 4310                         #address-cells = <1>;
 4311                         #size-cells = <0>;
 4312 
 4313                         reg = <0 0x0ac4a000 0 0x4000>;
 4314                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
 4315                         power-domains = <&clock_camcc TITAN_TOP_GDSC>;
 4316 
 4317                         clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
 4318                                 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
 4319                                 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
 4320                                 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
 4321                                 <&clock_camcc CAM_CC_CCI_CLK>,
 4322                                 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
 4323                         clock-names = "camnoc_axi",
 4324                                 "soc_ahb",
 4325                                 "slow_ahb_src",
 4326                                 "cpas_ahb",
 4327                                 "cci",
 4328                                 "cci_src";
 4329 
 4330                         assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
 4331                                 <&clock_camcc CAM_CC_CCI_CLK>;
 4332                         assigned-clock-rates = <80000000>, <37500000>;
 4333 
 4334                         pinctrl-names = "default", "sleep";
 4335                         pinctrl-0 = <&cci0_default &cci1_default>;
 4336                         pinctrl-1 = <&cci0_sleep &cci1_sleep>;
 4337 
 4338                         status = "disabled";
 4339 
 4340                         cci_i2c0: i2c-bus@0 {
 4341                                 reg = <0>;
 4342                                 clock-frequency = <1000000>;
 4343                                 #address-cells = <1>;
 4344                                 #size-cells = <0>;
 4345                         };
 4346 
 4347                         cci_i2c1: i2c-bus@1 {
 4348                                 reg = <1>;
 4349                                 clock-frequency = <1000000>;
 4350                                 #address-cells = <1>;
 4351                                 #size-cells = <0>;
 4352                         };
 4353                 };
 4354 
 4355                 clock_camcc: clock-controller@ad00000 {
 4356                         compatible = "qcom,sdm845-camcc";
 4357                         reg = <0 0x0ad00000 0 0x10000>;
 4358                         #clock-cells = <1>;
 4359                         #reset-cells = <1>;
 4360                         #power-domain-cells = <1>;
 4361                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 4362                         clock-names = "bi_tcxo";
 4363                 };
 4364 
 4365                 dsi_opp_table: opp-table-dsi {
 4366                         compatible = "operating-points-v2";
 4367 
 4368                         opp-19200000 {
 4369                                 opp-hz = /bits/ 64 <19200000>;
 4370                                 required-opps = <&rpmhpd_opp_min_svs>;
 4371                         };
 4372 
 4373                         opp-180000000 {
 4374                                 opp-hz = /bits/ 64 <180000000>;
 4375                                 required-opps = <&rpmhpd_opp_low_svs>;
 4376                         };
 4377 
 4378                         opp-275000000 {
 4379                                 opp-hz = /bits/ 64 <275000000>;
 4380                                 required-opps = <&rpmhpd_opp_svs>;
 4381                         };
 4382 
 4383                         opp-328580000 {
 4384                                 opp-hz = /bits/ 64 <328580000>;
 4385                                 required-opps = <&rpmhpd_opp_svs_l1>;
 4386                         };
 4387 
 4388                         opp-358000000 {
 4389                                 opp-hz = /bits/ 64 <358000000>;
 4390                                 required-opps = <&rpmhpd_opp_nom>;
 4391                         };
 4392                 };
 4393 
 4394                 mdss: mdss@ae00000 {
 4395                         compatible = "qcom,sdm845-mdss";
 4396                         reg = <0 0x0ae00000 0 0x1000>;
 4397                         reg-names = "mdss";
 4398 
 4399                         power-domains = <&dispcc MDSS_GDSC>;
 4400 
 4401                         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 4402                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
 4403                         clock-names = "iface", "core";
 4404 
 4405                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 4406                         interrupt-controller;
 4407                         #interrupt-cells = <1>;
 4408 
 4409                         interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>,
 4410                                         <&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>;
 4411                         interconnect-names = "mdp0-mem", "mdp1-mem";
 4412 
 4413                         iommus = <&apps_smmu 0x880 0x8>,
 4414                                  <&apps_smmu 0xc80 0x8>;
 4415 
 4416                         status = "disabled";
 4417 
 4418                         #address-cells = <2>;
 4419                         #size-cells = <2>;
 4420                         ranges;
 4421 
 4422                         mdss_mdp: display-controller@ae01000 {
 4423                                 compatible = "qcom,sdm845-dpu";
 4424                                 reg = <0 0x0ae01000 0 0x8f000>,
 4425                                       <0 0x0aeb0000 0 0x2008>;
 4426                                 reg-names = "mdp", "vbif";
 4427 
 4428                                 clocks = <&gcc GCC_DISP_AXI_CLK>,
 4429                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
 4430                                          <&dispcc DISP_CC_MDSS_AXI_CLK>,
 4431                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
 4432                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 4433                                 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
 4434 
 4435                                 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
 4436                                 assigned-clock-rates = <19200000>;
 4437                                 operating-points-v2 = <&mdp_opp_table>;
 4438                                 power-domains = <&rpmhpd SDM845_CX>;
 4439 
 4440                                 interrupt-parent = <&mdss>;
 4441                                 interrupts = <0>;
 4442 
 4443                                 ports {
 4444                                         #address-cells = <1>;
 4445                                         #size-cells = <0>;
 4446 
 4447                                         port@0 {
 4448                                                 reg = <0>;
 4449                                                 dpu_intf1_out: endpoint {
 4450                                                         remote-endpoint = <&dsi0_in>;
 4451                                                 };
 4452                                         };
 4453 
 4454                                         port@1 {
 4455                                                 reg = <1>;
 4456                                                 dpu_intf2_out: endpoint {
 4457                                                         remote-endpoint = <&dsi1_in>;
 4458                                                 };
 4459                                         };
 4460                                 };
 4461 
 4462                                 mdp_opp_table: opp-table {
 4463                                         compatible = "operating-points-v2";
 4464 
 4465                                         opp-19200000 {
 4466                                                 opp-hz = /bits/ 64 <19200000>;
 4467                                                 required-opps = <&rpmhpd_opp_min_svs>;
 4468                                         };
 4469 
 4470                                         opp-171428571 {
 4471                                                 opp-hz = /bits/ 64 <171428571>;
 4472                                                 required-opps = <&rpmhpd_opp_low_svs>;
 4473                                         };
 4474 
 4475                                         opp-344000000 {
 4476                                                 opp-hz = /bits/ 64 <344000000>;
 4477                                                 required-opps = <&rpmhpd_opp_svs_l1>;
 4478                                         };
 4479 
 4480                                         opp-430000000 {
 4481                                                 opp-hz = /bits/ 64 <430000000>;
 4482                                                 required-opps = <&rpmhpd_opp_nom>;
 4483                                         };
 4484                                 };
 4485                         };
 4486 
 4487                         dsi0: dsi@ae94000 {
 4488                                 compatible = "qcom,mdss-dsi-ctrl";
 4489                                 reg = <0 0x0ae94000 0 0x400>;
 4490                                 reg-names = "dsi_ctrl";
 4491 
 4492                                 interrupt-parent = <&mdss>;
 4493                                 interrupts = <4>;
 4494 
 4495                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 4496                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 4497                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 4498                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 4499                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
 4500                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
 4501                                 clock-names = "byte",
 4502                                               "byte_intf",
 4503                                               "pixel",
 4504                                               "core",
 4505                                               "iface",
 4506                                               "bus";
 4507                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
 4508                                 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
 4509 
 4510                                 operating-points-v2 = <&dsi_opp_table>;
 4511                                 power-domains = <&rpmhpd SDM845_CX>;
 4512 
 4513                                 phys = <&dsi0_phy>;
 4514                                 phy-names = "dsi";
 4515 
 4516                                 status = "disabled";
 4517 
 4518                                 #address-cells = <1>;
 4519                                 #size-cells = <0>;
 4520 
 4521                                 ports {
 4522                                         #address-cells = <1>;
 4523                                         #size-cells = <0>;
 4524 
 4525                                         port@0 {
 4526                                                 reg = <0>;
 4527                                                 dsi0_in: endpoint {
 4528                                                         remote-endpoint = <&dpu_intf1_out>;
 4529                                                 };
 4530                                         };
 4531 
 4532                                         port@1 {
 4533                                                 reg = <1>;
 4534                                                 dsi0_out: endpoint {
 4535                                                 };
 4536                                         };
 4537                                 };
 4538                         };
 4539 
 4540                         dsi0_phy: dsi-phy@ae94400 {
 4541                                 compatible = "qcom,dsi-phy-10nm";
 4542                                 reg = <0 0x0ae94400 0 0x200>,
 4543                                       <0 0x0ae94600 0 0x280>,
 4544                                       <0 0x0ae94a00 0 0x1e0>;
 4545                                 reg-names = "dsi_phy",
 4546                                             "dsi_phy_lane",
 4547                                             "dsi_pll";
 4548 
 4549                                 #clock-cells = <1>;
 4550                                 #phy-cells = <0>;
 4551 
 4552                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 4553                                          <&rpmhcc RPMH_CXO_CLK>;
 4554                                 clock-names = "iface", "ref";
 4555 
 4556                                 status = "disabled";
 4557                         };
 4558 
 4559                         dsi1: dsi@ae96000 {
 4560                                 compatible = "qcom,mdss-dsi-ctrl";
 4561                                 reg = <0 0x0ae96000 0 0x400>;
 4562                                 reg-names = "dsi_ctrl";
 4563 
 4564                                 interrupt-parent = <&mdss>;
 4565                                 interrupts = <5>;
 4566 
 4567                                 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
 4568                                          <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
 4569                                          <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
 4570                                          <&dispcc DISP_CC_MDSS_ESC1_CLK>,
 4571                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
 4572                                          <&dispcc DISP_CC_MDSS_AXI_CLK>;
 4573                                 clock-names = "byte",
 4574                                               "byte_intf",
 4575                                               "pixel",
 4576                                               "core",
 4577                                               "iface",
 4578                                               "bus";
 4579                                 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
 4580                                 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
 4581 
 4582                                 operating-points-v2 = <&dsi_opp_table>;
 4583                                 power-domains = <&rpmhpd SDM845_CX>;
 4584 
 4585                                 phys = <&dsi1_phy>;
 4586                                 phy-names = "dsi";
 4587 
 4588                                 status = "disabled";
 4589 
 4590                                 #address-cells = <1>;
 4591                                 #size-cells = <0>;
 4592 
 4593                                 ports {
 4594                                         #address-cells = <1>;
 4595                                         #size-cells = <0>;
 4596 
 4597                                         port@0 {
 4598                                                 reg = <0>;
 4599                                                 dsi1_in: endpoint {
 4600                                                         remote-endpoint = <&dpu_intf2_out>;
 4601                                                 };
 4602                                         };
 4603 
 4604                                         port@1 {
 4605                                                 reg = <1>;
 4606                                                 dsi1_out: endpoint {
 4607                                                 };
 4608                                         };
 4609                                 };
 4610                         };
 4611 
 4612                         dsi1_phy: dsi-phy@ae96400 {
 4613                                 compatible = "qcom,dsi-phy-10nm";
 4614                                 reg = <0 0x0ae96400 0 0x200>,
 4615                                       <0 0x0ae96600 0 0x280>,
 4616                                       <0 0x0ae96a00 0 0x10e>;
 4617                                 reg-names = "dsi_phy",
 4618                                             "dsi_phy_lane",
 4619                                             "dsi_pll";
 4620 
 4621                                 #clock-cells = <1>;
 4622                                 #phy-cells = <0>;
 4623 
 4624                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
 4625                                          <&rpmhcc RPMH_CXO_CLK>;
 4626                                 clock-names = "iface", "ref";
 4627 
 4628                                 status = "disabled";
 4629                         };
 4630                 };
 4631 
 4632                 gpu: gpu@5000000 {
 4633                         compatible = "qcom,adreno-630.2", "qcom,adreno";
 4634 
 4635                         reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
 4636                         reg-names = "kgsl_3d0_reg_memory", "cx_mem";
 4637 
 4638                         /*
 4639                          * Look ma, no clocks! The GPU clocks and power are
 4640                          * controlled entirely by the GMU
 4641                          */
 4642 
 4643                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
 4644 
 4645                         iommus = <&adreno_smmu 0>;
 4646 
 4647                         operating-points-v2 = <&gpu_opp_table>;
 4648 
 4649                         qcom,gmu = <&gmu>;
 4650 
 4651                         interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>;
 4652                         interconnect-names = "gfx-mem";
 4653 
 4654                         status = "disabled";
 4655 
 4656                         gpu_opp_table: opp-table {
 4657                                 compatible = "operating-points-v2";
 4658 
 4659                                 opp-710000000 {
 4660                                         opp-hz = /bits/ 64 <710000000>;
 4661                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 4662                                         opp-peak-kBps = <7216000>;
 4663                                 };
 4664 
 4665                                 opp-675000000 {
 4666                                         opp-hz = /bits/ 64 <675000000>;
 4667                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 4668                                         opp-peak-kBps = <7216000>;
 4669                                 };
 4670 
 4671                                 opp-596000000 {
 4672                                         opp-hz = /bits/ 64 <596000000>;
 4673                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 4674                                         opp-peak-kBps = <6220000>;
 4675                                 };
 4676 
 4677                                 opp-520000000 {
 4678                                         opp-hz = /bits/ 64 <520000000>;
 4679                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 4680                                         opp-peak-kBps = <6220000>;
 4681                                 };
 4682 
 4683                                 opp-414000000 {
 4684                                         opp-hz = /bits/ 64 <414000000>;
 4685                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 4686                                         opp-peak-kBps = <4068000>;
 4687                                 };
 4688 
 4689                                 opp-342000000 {
 4690                                         opp-hz = /bits/ 64 <342000000>;
 4691                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 4692                                         opp-peak-kBps = <2724000>;
 4693                                 };
 4694 
 4695                                 opp-257000000 {
 4696                                         opp-hz = /bits/ 64 <257000000>;
 4697                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 4698                                         opp-peak-kBps = <1648000>;
 4699                                 };
 4700                         };
 4701                 };
 4702 
 4703                 adreno_smmu: iommu@5040000 {
 4704                         compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
 4705                         reg = <0 0x5040000 0 0x10000>;
 4706                         #iommu-cells = <1>;
 4707                         #global-interrupts = <2>;
 4708                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
 4709                                      <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
 4710                                      <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 4711                                      <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 4712                                      <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
 4713                                      <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
 4714                                      <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
 4715                                      <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
 4716                                      <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
 4717                                      <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
 4718                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 4719                                  <&gcc GCC_GPU_CFG_AHB_CLK>;
 4720                         clock-names = "bus", "iface";
 4721 
 4722                         power-domains = <&gpucc GPU_CX_GDSC>;
 4723                 };
 4724 
 4725                 gmu: gmu@506a000 {
 4726                         compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
 4727 
 4728                         reg = <0 0x506a000 0 0x30000>,
 4729                               <0 0xb280000 0 0x10000>,
 4730                               <0 0xb480000 0 0x10000>;
 4731                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
 4732 
 4733                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
 4734                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
 4735                         interrupt-names = "hfi", "gmu";
 4736 
 4737                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
 4738                                  <&gpucc GPU_CC_CXO_CLK>,
 4739                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
 4740                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
 4741                         clock-names = "gmu", "cxo", "axi", "memnoc";
 4742 
 4743                         power-domains = <&gpucc GPU_CX_GDSC>,
 4744                                         <&gpucc GPU_GX_GDSC>;
 4745                         power-domain-names = "cx", "gx";
 4746 
 4747                         iommus = <&adreno_smmu 5>;
 4748 
 4749                         operating-points-v2 = <&gmu_opp_table>;
 4750 
 4751                         status = "disabled";
 4752 
 4753                         gmu_opp_table: opp-table {
 4754                                 compatible = "operating-points-v2";
 4755 
 4756                                 opp-400000000 {
 4757                                         opp-hz = /bits/ 64 <400000000>;
 4758                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 4759                                 };
 4760 
 4761                                 opp-200000000 {
 4762                                         opp-hz = /bits/ 64 <200000000>;
 4763                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 4764                                 };
 4765                         };
 4766                 };
 4767 
 4768                 dispcc: clock-controller@af00000 {
 4769                         compatible = "qcom,sdm845-dispcc";
 4770                         reg = <0 0x0af00000 0 0x10000>;
 4771                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 4772                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
 4773                                  <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
 4774                                  <&dsi0_phy 0>,
 4775                                  <&dsi0_phy 1>,
 4776                                  <&dsi1_phy 0>,
 4777                                  <&dsi1_phy 1>,
 4778                                  <0>,
 4779                                  <0>;
 4780                         clock-names = "bi_tcxo",
 4781                                       "gcc_disp_gpll0_clk_src",
 4782                                       "gcc_disp_gpll0_div_clk_src",
 4783                                       "dsi0_phy_pll_out_byteclk",
 4784                                       "dsi0_phy_pll_out_dsiclk",
 4785                                       "dsi1_phy_pll_out_byteclk",
 4786                                       "dsi1_phy_pll_out_dsiclk",
 4787                                       "dp_link_clk_divsel_ten",
 4788                                       "dp_vco_divided_clk_src_mux";
 4789                         #clock-cells = <1>;
 4790                         #reset-cells = <1>;
 4791                         #power-domain-cells = <1>;
 4792                 };
 4793 
 4794                 pdc_intc: interrupt-controller@b220000 {
 4795                         compatible = "qcom,sdm845-pdc", "qcom,pdc";
 4796                         reg = <0 0x0b220000 0 0x30000>;
 4797                         qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
 4798                         #interrupt-cells = <2>;
 4799                         interrupt-parent = <&intc>;
 4800                         interrupt-controller;
 4801                 };
 4802 
 4803                 pdc_reset: reset-controller@b2e0000 {
 4804                         compatible = "qcom,sdm845-pdc-global";
 4805                         reg = <0 0x0b2e0000 0 0x20000>;
 4806                         #reset-cells = <1>;
 4807                 };
 4808 
 4809                 tsens0: thermal-sensor@c263000 {
 4810                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
 4811                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
 4812                               <0 0x0c222000 0 0x1ff>; /* SROT */
 4813                         #qcom,sensors = <13>;
 4814                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
 4815                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
 4816                         interrupt-names = "uplow", "critical";
 4817                         #thermal-sensor-cells = <1>;
 4818                 };
 4819 
 4820                 tsens1: thermal-sensor@c265000 {
 4821                         compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
 4822                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
 4823                               <0 0x0c223000 0 0x1ff>; /* SROT */
 4824                         #qcom,sensors = <8>;
 4825                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
 4826                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
 4827                         interrupt-names = "uplow", "critical";
 4828                         #thermal-sensor-cells = <1>;
 4829                 };
 4830 
 4831                 aoss_reset: reset-controller@c2a0000 {
 4832                         compatible = "qcom,sdm845-aoss-cc";
 4833                         reg = <0 0x0c2a0000 0 0x31000>;
 4834                         #reset-cells = <1>;
 4835                 };
 4836 
 4837                 aoss_qmp: power-controller@c300000 {
 4838                         compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
 4839                         reg = <0 0x0c300000 0 0x100000>;
 4840                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
 4841                         mboxes = <&apss_shared 0>;
 4842 
 4843                         #clock-cells = <0>;
 4844 
 4845                         cx_cdev: cx {
 4846                                 #cooling-cells = <2>;
 4847                         };
 4848 
 4849                         ebi_cdev: ebi {
 4850                                 #cooling-cells = <2>;
 4851                         };
 4852                 };
 4853 
 4854                 spmi_bus: spmi@c440000 {
 4855                         compatible = "qcom,spmi-pmic-arb";
 4856                         reg = <0 0x0c440000 0 0x1100>,
 4857                               <0 0x0c600000 0 0x2000000>,
 4858                               <0 0x0e600000 0 0x100000>,
 4859                               <0 0x0e700000 0 0xa0000>,
 4860                               <0 0x0c40a000 0 0x26000>;
 4861                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 4862                         interrupt-names = "periph_irq";
 4863                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
 4864                         qcom,ee = <0>;
 4865                         qcom,channel = <0>;
 4866                         #address-cells = <2>;
 4867                         #size-cells = <0>;
 4868                         interrupt-controller;
 4869                         #interrupt-cells = <4>;
 4870                         cell-index = <0>;
 4871                 };
 4872 
 4873                 sram@146bf000 {
 4874                         compatible = "qcom,sdm845-imem", "syscon", "simple-mfd";
 4875                         reg = <0 0x146bf000 0 0x1000>;
 4876 
 4877                         #address-cells = <1>;
 4878                         #size-cells = <1>;
 4879 
 4880                         ranges = <0 0 0x146bf000 0x1000>;
 4881 
 4882                         pil-reloc@94c {
 4883                                 compatible = "qcom,pil-reloc-info";
 4884                                 reg = <0x94c 0xc8>;
 4885                         };
 4886                 };
 4887 
 4888                 apps_smmu: iommu@15000000 {
 4889                         compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
 4890                         reg = <0 0x15000000 0 0x80000>;
 4891                         #iommu-cells = <2>;
 4892                         #global-interrupts = <1>;
 4893                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
 4894                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 4895                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 4896                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 4897                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 4898                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 4899                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 4900                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 4901                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 4902                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 4903                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 4904                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 4905                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 4906                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 4907                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 4908                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 4909                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 4910                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 4911                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 4912                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 4913                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 4914                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 4915                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 4916                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 4917                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 4918                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 4919                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 4920                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 4921                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 4922                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 4923                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 4924                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 4925                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 4926                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 4927                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 4928                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 4929                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
 4930                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
 4931                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
 4932                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
 4933                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
 4934                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 4935                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 4936                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 4937                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 4938                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 4939                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
 4940                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
 4941                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
 4942                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
 4943                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
 4944                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
 4945                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
 4946                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
 4947                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
 4948                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
 4949                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
 4950                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
 4951                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
 4952                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
 4953                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
 4954                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
 4955                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
 4956                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
 4957                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 4958                 };
 4959 
 4960                 lpasscc: clock-controller@17014000 {
 4961                         compatible = "qcom,sdm845-lpasscc";
 4962                         reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>;
 4963                         reg-names = "cc", "qdsp6ss";
 4964                         #clock-cells = <1>;
 4965                         status = "disabled";
 4966                 };
 4967 
 4968                 gladiator_noc: interconnect@17900000 {
 4969                         compatible = "qcom,sdm845-gladiator-noc";
 4970                         reg = <0 0x17900000 0 0xd080>;
 4971                         #interconnect-cells = <2>;
 4972                         qcom,bcm-voters = <&apps_bcm_voter>;
 4973                 };
 4974 
 4975                 watchdog@17980000 {
 4976                         compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt";
 4977                         reg = <0 0x17980000 0 0x1000>;
 4978                         clocks = <&sleep_clk>;
 4979                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 4980                 };
 4981 
 4982                 apss_shared: mailbox@17990000 {
 4983                         compatible = "qcom,sdm845-apss-shared";
 4984                         reg = <0 0x17990000 0 0x1000>;
 4985                         #mbox-cells = <1>;
 4986                 };
 4987 
 4988                 apps_rsc: rsc@179c0000 {
 4989                         label = "apps_rsc";
 4990                         compatible = "qcom,rpmh-rsc";
 4991                         reg = <0 0x179c0000 0 0x10000>,
 4992                               <0 0x179d0000 0 0x10000>,
 4993                               <0 0x179e0000 0 0x10000>;
 4994                         reg-names = "drv-0", "drv-1", "drv-2";
 4995                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 4996                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 4997                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 4998                         qcom,tcs-offset = <0xd00>;
 4999                         qcom,drv-id = <2>;
 5000                         qcom,tcs-config = <ACTIVE_TCS  2>,
 5001                                           <SLEEP_TCS   3>,
 5002                                           <WAKE_TCS    3>,
 5003                                           <CONTROL_TCS 1>;
 5004 
 5005                         apps_bcm_voter: bcm-voter {
 5006                                 compatible = "qcom,bcm-voter";
 5007                         };
 5008 
 5009                         rpmhcc: clock-controller {
 5010                                 compatible = "qcom,sdm845-rpmh-clk";
 5011                                 #clock-cells = <1>;
 5012                                 clock-names = "xo";
 5013                                 clocks = <&xo_board>;
 5014                         };
 5015 
 5016                         rpmhpd: power-controller {
 5017                                 compatible = "qcom,sdm845-rpmhpd";
 5018                                 #power-domain-cells = <1>;
 5019                                 operating-points-v2 = <&rpmhpd_opp_table>;
 5020 
 5021                                 rpmhpd_opp_table: opp-table {
 5022                                         compatible = "operating-points-v2";
 5023 
 5024                                         rpmhpd_opp_ret: opp1 {
 5025                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 5026                                         };
 5027 
 5028                                         rpmhpd_opp_min_svs: opp2 {
 5029                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 5030                                         };
 5031 
 5032                                         rpmhpd_opp_low_svs: opp3 {
 5033                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 5034                                         };
 5035 
 5036                                         rpmhpd_opp_svs: opp4 {
 5037                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 5038                                         };
 5039 
 5040                                         rpmhpd_opp_svs_l1: opp5 {
 5041                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 5042                                         };
 5043 
 5044                                         rpmhpd_opp_nom: opp6 {
 5045                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 5046                                         };
 5047 
 5048                                         rpmhpd_opp_nom_l1: opp7 {
 5049                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 5050                                         };
 5051 
 5052                                         rpmhpd_opp_nom_l2: opp8 {
 5053                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
 5054                                         };
 5055 
 5056                                         rpmhpd_opp_turbo: opp9 {
 5057                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 5058                                         };
 5059 
 5060                                         rpmhpd_opp_turbo_l1: opp10 {
 5061                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 5062                                         };
 5063                                 };
 5064                         };
 5065                 };
 5066 
 5067                 intc: interrupt-controller@17a00000 {
 5068                         compatible = "arm,gic-v3";
 5069                         #address-cells = <2>;
 5070                         #size-cells = <2>;
 5071                         ranges;
 5072                         #interrupt-cells = <3>;
 5073                         interrupt-controller;
 5074                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
 5075                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
 5076                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 5077 
 5078                         msi-controller@17a40000 {
 5079                                 compatible = "arm,gic-v3-its";
 5080                                 msi-controller;
 5081                                 #msi-cells = <1>;
 5082                                 reg = <0 0x17a40000 0 0x20000>;
 5083                                 status = "disabled";
 5084                         };
 5085                 };
 5086 
 5087                 slimbam: dma-controller@17184000 {
 5088                         compatible = "qcom,bam-v1.7.0";
 5089                         qcom,controlled-remotely;
 5090                         reg = <0 0x17184000 0 0x2a000>;
 5091                         num-channels = <31>;
 5092                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 5093                         #dma-cells = <1>;
 5094                         qcom,ee = <1>;
 5095                         qcom,num-ees = <2>;
 5096                         iommus = <&apps_smmu 0x1806 0x0>;
 5097                 };
 5098 
 5099                 timer@17c90000 {
 5100                         #address-cells = <1>;
 5101                         #size-cells = <1>;
 5102                         ranges = <0 0 0 0x20000000>;
 5103                         compatible = "arm,armv7-timer-mem";
 5104                         reg = <0 0x17c90000 0 0x1000>;
 5105 
 5106                         frame@17ca0000 {
 5107                                 frame-number = <0>;
 5108                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 5109                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 5110                                 reg = <0x17ca0000 0x1000>,
 5111                                       <0x17cb0000 0x1000>;
 5112                         };
 5113 
 5114                         frame@17cc0000 {
 5115                                 frame-number = <1>;
 5116                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 5117                                 reg = <0x17cc0000 0x1000>;
 5118                                 status = "disabled";
 5119                         };
 5120 
 5121                         frame@17cd0000 {
 5122                                 frame-number = <2>;
 5123                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 5124                                 reg = <0x17cd0000 0x1000>;
 5125                                 status = "disabled";
 5126                         };
 5127 
 5128                         frame@17ce0000 {
 5129                                 frame-number = <3>;
 5130                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 5131                                 reg = <0x17ce0000 0x1000>;
 5132                                 status = "disabled";
 5133                         };
 5134 
 5135                         frame@17cf0000 {
 5136                                 frame-number = <4>;
 5137                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 5138                                 reg = <0x17cf0000 0x1000>;
 5139                                 status = "disabled";
 5140                         };
 5141 
 5142                         frame@17d00000 {
 5143                                 frame-number = <5>;
 5144                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 5145                                 reg = <0x17d00000 0x1000>;
 5146                                 status = "disabled";
 5147                         };
 5148 
 5149                         frame@17d10000 {
 5150                                 frame-number = <6>;
 5151                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 5152                                 reg = <0x17d10000 0x1000>;
 5153                                 status = "disabled";
 5154                         };
 5155                 };
 5156 
 5157                 osm_l3: interconnect@17d41000 {
 5158                         compatible = "qcom,sdm845-osm-l3";
 5159                         reg = <0 0x17d41000 0 0x1400>;
 5160 
 5161                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 5162                         clock-names = "xo", "alternate";
 5163 
 5164                         #interconnect-cells = <1>;
 5165                 };
 5166 
 5167                 cpufreq_hw: cpufreq@17d43000 {
 5168                         compatible = "qcom,cpufreq-hw";
 5169                         reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
 5170                         reg-names = "freq-domain0", "freq-domain1";
 5171 
 5172                         interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>;
 5173 
 5174                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 5175                         clock-names = "xo", "alternate";
 5176 
 5177                         #freq-domain-cells = <1>;
 5178                 };
 5179 
 5180                 wifi: wifi@18800000 {
 5181                         compatible = "qcom,wcn3990-wifi";
 5182                         status = "disabled";
 5183                         reg = <0 0x18800000 0 0x800000>;
 5184                         reg-names = "membase";
 5185                         memory-region = <&wlan_msa_mem>;
 5186                         clock-names = "cxo_ref_clk_pin";
 5187                         clocks = <&rpmhcc RPMH_RF_CLK2>;
 5188                         interrupts =
 5189                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
 5190                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
 5191                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
 5192                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
 5193                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
 5194                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
 5195                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
 5196                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
 5197                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
 5198                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
 5199                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
 5200                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
 5201                         iommus = <&apps_smmu 0x0040 0x1>;
 5202                 };
 5203         };
 5204 
 5205         thermal-zones {
 5206                 cpu0-thermal {
 5207                         polling-delay-passive = <250>;
 5208                         polling-delay = <1000>;
 5209 
 5210                         thermal-sensors = <&tsens0 1>;
 5211 
 5212                         trips {
 5213                                 cpu0_alert0: trip-point0 {
 5214                                         temperature = <90000>;
 5215                                         hysteresis = <2000>;
 5216                                         type = "passive";
 5217                                 };
 5218 
 5219                                 cpu0_alert1: trip-point1 {
 5220                                         temperature = <95000>;
 5221                                         hysteresis = <2000>;
 5222                                         type = "passive";
 5223                                 };
 5224 
 5225                                 cpu0_crit: cpu_crit {
 5226                                         temperature = <110000>;
 5227                                         hysteresis = <1000>;
 5228                                         type = "critical";
 5229                                 };
 5230                         };
 5231                 };
 5232 
 5233                 cpu1-thermal {
 5234                         polling-delay-passive = <250>;
 5235                         polling-delay = <1000>;
 5236 
 5237                         thermal-sensors = <&tsens0 2>;
 5238 
 5239                         trips {
 5240                                 cpu1_alert0: trip-point0 {
 5241                                         temperature = <90000>;
 5242                                         hysteresis = <2000>;
 5243                                         type = "passive";
 5244                                 };
 5245 
 5246                                 cpu1_alert1: trip-point1 {
 5247                                         temperature = <95000>;
 5248                                         hysteresis = <2000>;
 5249                                         type = "passive";
 5250                                 };
 5251 
 5252                                 cpu1_crit: cpu_crit {
 5253                                         temperature = <110000>;
 5254                                         hysteresis = <1000>;
 5255                                         type = "critical";
 5256                                 };
 5257                         };
 5258                 };
 5259 
 5260                 cpu2-thermal {
 5261                         polling-delay-passive = <250>;
 5262                         polling-delay = <1000>;
 5263 
 5264                         thermal-sensors = <&tsens0 3>;
 5265 
 5266                         trips {
 5267                                 cpu2_alert0: trip-point0 {
 5268                                         temperature = <90000>;
 5269                                         hysteresis = <2000>;
 5270                                         type = "passive";
 5271                                 };
 5272 
 5273                                 cpu2_alert1: trip-point1 {
 5274                                         temperature = <95000>;
 5275                                         hysteresis = <2000>;
 5276                                         type = "passive";
 5277                                 };
 5278 
 5279                                 cpu2_crit: cpu_crit {
 5280                                         temperature = <110000>;
 5281                                         hysteresis = <1000>;
 5282                                         type = "critical";
 5283                                 };
 5284                         };
 5285                 };
 5286 
 5287                 cpu3-thermal {
 5288                         polling-delay-passive = <250>;
 5289                         polling-delay = <1000>;
 5290 
 5291                         thermal-sensors = <&tsens0 4>;
 5292 
 5293                         trips {
 5294                                 cpu3_alert0: trip-point0 {
 5295                                         temperature = <90000>;
 5296                                         hysteresis = <2000>;
 5297                                         type = "passive";
 5298                                 };
 5299 
 5300                                 cpu3_alert1: trip-point1 {
 5301                                         temperature = <95000>;
 5302                                         hysteresis = <2000>;
 5303                                         type = "passive";
 5304                                 };
 5305 
 5306                                 cpu3_crit: cpu_crit {
 5307                                         temperature = <110000>;
 5308                                         hysteresis = <1000>;
 5309                                         type = "critical";
 5310                                 };
 5311                         };
 5312                 };
 5313 
 5314                 cpu4-thermal {
 5315                         polling-delay-passive = <250>;
 5316                         polling-delay = <1000>;
 5317 
 5318                         thermal-sensors = <&tsens0 7>;
 5319 
 5320                         trips {
 5321                                 cpu4_alert0: trip-point0 {
 5322                                         temperature = <90000>;
 5323                                         hysteresis = <2000>;
 5324                                         type = "passive";
 5325                                 };
 5326 
 5327                                 cpu4_alert1: trip-point1 {
 5328                                         temperature = <95000>;
 5329                                         hysteresis = <2000>;
 5330                                         type = "passive";
 5331                                 };
 5332 
 5333                                 cpu4_crit: cpu_crit {
 5334                                         temperature = <110000>;
 5335                                         hysteresis = <1000>;
 5336                                         type = "critical";
 5337                                 };
 5338                         };
 5339                 };
 5340 
 5341                 cpu5-thermal {
 5342                         polling-delay-passive = <250>;
 5343                         polling-delay = <1000>;
 5344 
 5345                         thermal-sensors = <&tsens0 8>;
 5346 
 5347                         trips {
 5348                                 cpu5_alert0: trip-point0 {
 5349                                         temperature = <90000>;
 5350                                         hysteresis = <2000>;
 5351                                         type = "passive";
 5352                                 };
 5353 
 5354                                 cpu5_alert1: trip-point1 {
 5355                                         temperature = <95000>;
 5356                                         hysteresis = <2000>;
 5357                                         type = "passive";
 5358                                 };
 5359 
 5360                                 cpu5_crit: cpu_crit {
 5361                                         temperature = <110000>;
 5362                                         hysteresis = <1000>;
 5363                                         type = "critical";
 5364                                 };
 5365                         };
 5366                 };
 5367 
 5368                 cpu6-thermal {
 5369                         polling-delay-passive = <250>;
 5370                         polling-delay = <1000>;
 5371 
 5372                         thermal-sensors = <&tsens0 9>;
 5373 
 5374                         trips {
 5375                                 cpu6_alert0: trip-point0 {
 5376                                         temperature = <90000>;
 5377                                         hysteresis = <2000>;
 5378                                         type = "passive";
 5379                                 };
 5380 
 5381                                 cpu6_alert1: trip-point1 {
 5382                                         temperature = <95000>;
 5383                                         hysteresis = <2000>;
 5384                                         type = "passive";
 5385                                 };
 5386 
 5387                                 cpu6_crit: cpu_crit {
 5388                                         temperature = <110000>;
 5389                                         hysteresis = <1000>;
 5390                                         type = "critical";
 5391                                 };
 5392                         };
 5393                 };
 5394 
 5395                 cpu7-thermal {
 5396                         polling-delay-passive = <250>;
 5397                         polling-delay = <1000>;
 5398 
 5399                         thermal-sensors = <&tsens0 10>;
 5400 
 5401                         trips {
 5402                                 cpu7_alert0: trip-point0 {
 5403                                         temperature = <90000>;
 5404                                         hysteresis = <2000>;
 5405                                         type = "passive";
 5406                                 };
 5407 
 5408                                 cpu7_alert1: trip-point1 {
 5409                                         temperature = <95000>;
 5410                                         hysteresis = <2000>;
 5411                                         type = "passive";
 5412                                 };
 5413 
 5414                                 cpu7_crit: cpu_crit {
 5415                                         temperature = <110000>;
 5416                                         hysteresis = <1000>;
 5417                                         type = "critical";
 5418                                 };
 5419                         };
 5420                 };
 5421 
 5422                 aoss0-thermal {
 5423                         polling-delay-passive = <250>;
 5424                         polling-delay = <1000>;
 5425 
 5426                         thermal-sensors = <&tsens0 0>;
 5427 
 5428                         trips {
 5429                                 aoss0_alert0: trip-point0 {
 5430                                         temperature = <90000>;
 5431                                         hysteresis = <2000>;
 5432                                         type = "hot";
 5433                                 };
 5434                         };
 5435                 };
 5436 
 5437                 cluster0-thermal {
 5438                         polling-delay-passive = <250>;
 5439                         polling-delay = <1000>;
 5440 
 5441                         thermal-sensors = <&tsens0 5>;
 5442 
 5443                         trips {
 5444                                 cluster0_alert0: trip-point0 {
 5445                                         temperature = <90000>;
 5446                                         hysteresis = <2000>;
 5447                                         type = "hot";
 5448                                 };
 5449                                 cluster0_crit: cluster0_crit {
 5450                                         temperature = <110000>;
 5451                                         hysteresis = <2000>;
 5452                                         type = "critical";
 5453                                 };
 5454                         };
 5455                 };
 5456 
 5457                 cluster1-thermal {
 5458                         polling-delay-passive = <250>;
 5459                         polling-delay = <1000>;
 5460 
 5461                         thermal-sensors = <&tsens0 6>;
 5462 
 5463                         trips {
 5464                                 cluster1_alert0: trip-point0 {
 5465                                         temperature = <90000>;
 5466                                         hysteresis = <2000>;
 5467                                         type = "hot";
 5468                                 };
 5469                                 cluster1_crit: cluster1_crit {
 5470                                         temperature = <110000>;
 5471                                         hysteresis = <2000>;
 5472                                         type = "critical";
 5473                                 };
 5474                         };
 5475                 };
 5476 
 5477                 gpu-top-thermal {
 5478                         polling-delay-passive = <250>;
 5479                         polling-delay = <1000>;
 5480 
 5481                         thermal-sensors = <&tsens0 11>;
 5482 
 5483                         trips {
 5484                                 gpu1_alert0: trip-point0 {
 5485                                         temperature = <90000>;
 5486                                         hysteresis = <2000>;
 5487                                         type = "hot";
 5488                                 };
 5489                         };
 5490                 };
 5491 
 5492                 gpu-bottom-thermal {
 5493                         polling-delay-passive = <250>;
 5494                         polling-delay = <1000>;
 5495 
 5496                         thermal-sensors = <&tsens0 12>;
 5497 
 5498                         trips {
 5499                                 gpu2_alert0: trip-point0 {
 5500                                         temperature = <90000>;
 5501                                         hysteresis = <2000>;
 5502                                         type = "hot";
 5503                                 };
 5504                         };
 5505                 };
 5506 
 5507                 aoss1-thermal {
 5508                         polling-delay-passive = <250>;
 5509                         polling-delay = <1000>;
 5510 
 5511                         thermal-sensors = <&tsens1 0>;
 5512 
 5513                         trips {
 5514                                 aoss1_alert0: trip-point0 {
 5515                                         temperature = <90000>;
 5516                                         hysteresis = <2000>;
 5517                                         type = "hot";
 5518                                 };
 5519                         };
 5520                 };
 5521 
 5522                 q6-modem-thermal {
 5523                         polling-delay-passive = <250>;
 5524                         polling-delay = <1000>;
 5525 
 5526                         thermal-sensors = <&tsens1 1>;
 5527 
 5528                         trips {
 5529                                 q6_modem_alert0: trip-point0 {
 5530                                         temperature = <90000>;
 5531                                         hysteresis = <2000>;
 5532                                         type = "hot";
 5533                                 };
 5534                         };
 5535                 };
 5536 
 5537                 mem-thermal {
 5538                         polling-delay-passive = <250>;
 5539                         polling-delay = <1000>;
 5540 
 5541                         thermal-sensors = <&tsens1 2>;
 5542 
 5543                         trips {
 5544                                 mem_alert0: trip-point0 {
 5545                                         temperature = <90000>;
 5546                                         hysteresis = <2000>;
 5547                                         type = "hot";
 5548                                 };
 5549                         };
 5550                 };
 5551 
 5552                 wlan-thermal {
 5553                         polling-delay-passive = <250>;
 5554                         polling-delay = <1000>;
 5555 
 5556                         thermal-sensors = <&tsens1 3>;
 5557 
 5558                         trips {
 5559                                 wlan_alert0: trip-point0 {
 5560                                         temperature = <90000>;
 5561                                         hysteresis = <2000>;
 5562                                         type = "hot";
 5563                                 };
 5564                         };
 5565                 };
 5566 
 5567                 q6-hvx-thermal {
 5568                         polling-delay-passive = <250>;
 5569                         polling-delay = <1000>;
 5570 
 5571                         thermal-sensors = <&tsens1 4>;
 5572 
 5573                         trips {
 5574                                 q6_hvx_alert0: trip-point0 {
 5575                                         temperature = <90000>;
 5576                                         hysteresis = <2000>;
 5577                                         type = "hot";
 5578                                 };
 5579                         };
 5580                 };
 5581 
 5582                 camera-thermal {
 5583                         polling-delay-passive = <250>;
 5584                         polling-delay = <1000>;
 5585 
 5586                         thermal-sensors = <&tsens1 5>;
 5587 
 5588                         trips {
 5589                                 camera_alert0: trip-point0 {
 5590                                         temperature = <90000>;
 5591                                         hysteresis = <2000>;
 5592                                         type = "hot";
 5593                                 };
 5594                         };
 5595                 };
 5596 
 5597                 video-thermal {
 5598                         polling-delay-passive = <250>;
 5599                         polling-delay = <1000>;
 5600 
 5601                         thermal-sensors = <&tsens1 6>;
 5602 
 5603                         trips {
 5604                                 video_alert0: trip-point0 {
 5605                                         temperature = <90000>;
 5606                                         hysteresis = <2000>;
 5607                                         type = "hot";
 5608                                 };
 5609                         };
 5610                 };
 5611 
 5612                 modem-thermal {
 5613                         polling-delay-passive = <250>;
 5614                         polling-delay = <1000>;
 5615 
 5616                         thermal-sensors = <&tsens1 7>;
 5617 
 5618                         trips {
 5619                                 modem_alert0: trip-point0 {
 5620                                         temperature = <90000>;
 5621                                         hysteresis = <2000>;
 5622                                         type = "hot";
 5623                                 };
 5624                         };
 5625                 };
 5626         };
 5627 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/qcom/sdm845.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/qcom/sdm845.dtsi
