The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/realtek/rtd1293.dtsi

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
    2 /*
    3  * Realtek RTD1293 SoC
    4  *
    5  * Copyright (c) 2017-2019 Andreas Färber
    6  */
    7 
    8 #include "rtd129x.dtsi"
    9 
   10 / {
   11         compatible = "realtek,rtd1293";
   12 
   13         cpus {
   14                 #address-cells = <2>;
   15                 #size-cells = <0>;
   16 
   17                 cpu0: cpu@0 {
   18                         device_type = "cpu";
   19                         compatible = "arm,cortex-a53";
   20                         reg = <0x0 0x0>;
   21                         next-level-cache = <&l2>;
   22                 };
   23 
   24                 cpu1: cpu@1 {
   25                         device_type = "cpu";
   26                         compatible = "arm,cortex-a53";
   27                         reg = <0x0 0x1>;
   28                         next-level-cache = <&l2>;
   29                 };
   30 
   31                 l2: l2-cache {
   32                         compatible = "cache";
   33                 };
   34         };
   35 
   36         timer {
   37                 compatible = "arm,armv8-timer";
   38                 interrupts = <GIC_PPI 13
   39                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   40                              <GIC_PPI 14
   41                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   42                              <GIC_PPI 11
   43                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
   44                              <GIC_PPI 10
   45                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
   46         };
   47 };
   48 
   49 &arm_pmu {
   50         interrupt-affinity = <&cpu0>, <&cpu1>;
   51 };
   52 
   53 &gic {
   54         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
   55 };

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