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sys/contrib/device-tree/src/arm64/renesas/r8a77970.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device Tree Source for the R-Car V3M (R8A77970) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/power/r8a77970-sysc.h> 13 14 / { 15 compatible = "renesas,r8a77970"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 }; 26 27 /* External CAN clock - to be overridden by boards that provide it */ 28 can_clk: can { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 a53_0: cpu@0 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a53"; 41 reg = <0>; 42 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 43 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 44 next-level-cache = <&L2_CA53>; 45 enable-method = "psci"; 46 }; 47 48 a53_1: cpu@1 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a53"; 51 reg = <1>; 52 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 53 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 54 next-level-cache = <&L2_CA53>; 55 enable-method = "psci"; 56 }; 57 58 L2_CA53: cache-controller { 59 compatible = "cache"; 60 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 61 cache-unified; 62 cache-level = <2>; 63 }; 64 }; 65 66 extal_clk: extal { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 /* This value must be overridden by the board */ 70 clock-frequency = <0>; 71 }; 72 73 extalr_clk: extalr { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 /* This value must be overridden by the board */ 77 clock-frequency = <0>; 78 }; 79 80 pmu_a53 { 81 compatible = "arm,cortex-a53-pmu"; 82 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 83 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&a53_0>, <&a53_1>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0", "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 /* External SCIF clock - to be overridden by boards that provide it */ 93 scif_clk: scif { 94 compatible = "fixed-clock"; 95 #clock-cells = <0>; 96 clock-frequency = <0>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 103 #address-cells = <2>; 104 #size-cells = <2>; 105 ranges; 106 107 rwdt: watchdog@e6020000 { 108 compatible = "renesas,r8a77970-wdt", 109 "renesas,rcar-gen3-wdt"; 110 reg = <0 0xe6020000 0 0x0c>; 111 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&cpg CPG_MOD 402>; 113 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 114 resets = <&cpg 402>; 115 status = "disabled"; 116 }; 117 118 gpio0: gpio@e6050000 { 119 compatible = "renesas,gpio-r8a77970", 120 "renesas,rcar-gen3-gpio"; 121 reg = <0 0xe6050000 0 0x50>; 122 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 123 #gpio-cells = <2>; 124 gpio-controller; 125 gpio-ranges = <&pfc 0 0 22>; 126 #interrupt-cells = <2>; 127 interrupt-controller; 128 clocks = <&cpg CPG_MOD 912>; 129 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 130 resets = <&cpg 912>; 131 }; 132 133 gpio1: gpio@e6051000 { 134 compatible = "renesas,gpio-r8a77970", 135 "renesas,rcar-gen3-gpio"; 136 reg = <0 0xe6051000 0 0x50>; 137 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 138 #gpio-cells = <2>; 139 gpio-controller; 140 gpio-ranges = <&pfc 0 32 28>; 141 #interrupt-cells = <2>; 142 interrupt-controller; 143 clocks = <&cpg CPG_MOD 911>; 144 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 145 resets = <&cpg 911>; 146 }; 147 148 gpio2: gpio@e6052000 { 149 compatible = "renesas,gpio-r8a77970", 150 "renesas,rcar-gen3-gpio"; 151 reg = <0 0xe6052000 0 0x50>; 152 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 153 #gpio-cells = <2>; 154 gpio-controller; 155 gpio-ranges = <&pfc 0 64 17>; 156 #interrupt-cells = <2>; 157 interrupt-controller; 158 clocks = <&cpg CPG_MOD 910>; 159 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 160 resets = <&cpg 910>; 161 }; 162 163 gpio3: gpio@e6053000 { 164 compatible = "renesas,gpio-r8a77970", 165 "renesas,rcar-gen3-gpio"; 166 reg = <0 0xe6053000 0 0x50>; 167 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 168 #gpio-cells = <2>; 169 gpio-controller; 170 gpio-ranges = <&pfc 0 96 17>; 171 #interrupt-cells = <2>; 172 interrupt-controller; 173 clocks = <&cpg CPG_MOD 909>; 174 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 175 resets = <&cpg 909>; 176 }; 177 178 gpio4: gpio@e6054000 { 179 compatible = "renesas,gpio-r8a77970", 180 "renesas,rcar-gen3-gpio"; 181 reg = <0 0xe6054000 0 0x50>; 182 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 183 #gpio-cells = <2>; 184 gpio-controller; 185 gpio-ranges = <&pfc 0 128 6>; 186 #interrupt-cells = <2>; 187 interrupt-controller; 188 clocks = <&cpg CPG_MOD 908>; 189 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 190 resets = <&cpg 908>; 191 }; 192 193 gpio5: gpio@e6055000 { 194 compatible = "renesas,gpio-r8a77970", 195 "renesas,rcar-gen3-gpio"; 196 reg = <0 0xe6055000 0 0x50>; 197 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 198 #gpio-cells = <2>; 199 gpio-controller; 200 gpio-ranges = <&pfc 0 160 15>; 201 #interrupt-cells = <2>; 202 interrupt-controller; 203 clocks = <&cpg CPG_MOD 907>; 204 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 205 resets = <&cpg 907>; 206 }; 207 208 pfc: pinctrl@e6060000 { 209 compatible = "renesas,pfc-r8a77970"; 210 reg = <0 0xe6060000 0 0x504>; 211 }; 212 213 cmt0: timer@e60f0000 { 214 compatible = "renesas,r8a77970-cmt0", 215 "renesas,rcar-gen3-cmt0"; 216 reg = <0 0xe60f0000 0 0x1004>; 217 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&cpg CPG_MOD 303>; 220 clock-names = "fck"; 221 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 222 resets = <&cpg 303>; 223 status = "disabled"; 224 }; 225 226 cmt1: timer@e6130000 { 227 compatible = "renesas,r8a77970-cmt1", 228 "renesas,rcar-gen3-cmt1"; 229 reg = <0 0xe6130000 0 0x1004>; 230 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&cpg CPG_MOD 302>; 239 clock-names = "fck"; 240 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 241 resets = <&cpg 302>; 242 status = "disabled"; 243 }; 244 245 cmt2: timer@e6140000 { 246 compatible = "renesas,r8a77970-cmt1", 247 "renesas,rcar-gen3-cmt1"; 248 reg = <0 0xe6140000 0 0x1004>; 249 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cpg CPG_MOD 301>; 258 clock-names = "fck"; 259 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 260 resets = <&cpg 301>; 261 status = "disabled"; 262 }; 263 264 cmt3: timer@e6148000 { 265 compatible = "renesas,r8a77970-cmt1", 266 "renesas,rcar-gen3-cmt1"; 267 reg = <0 0xe6148000 0 0x1004>; 268 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&cpg CPG_MOD 300>; 277 clock-names = "fck"; 278 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 279 resets = <&cpg 300>; 280 status = "disabled"; 281 }; 282 283 cpg: clock-controller@e6150000 { 284 compatible = "renesas,r8a77970-cpg-mssr"; 285 reg = <0 0xe6150000 0 0x1000>; 286 clocks = <&extal_clk>, <&extalr_clk>; 287 clock-names = "extal", "extalr"; 288 #clock-cells = <2>; 289 #power-domain-cells = <0>; 290 #reset-cells = <1>; 291 }; 292 293 rst: reset-controller@e6160000 { 294 compatible = "renesas,r8a77970-rst"; 295 reg = <0 0xe6160000 0 0x200>; 296 }; 297 298 sysc: system-controller@e6180000 { 299 compatible = "renesas,r8a77970-sysc"; 300 reg = <0 0xe6180000 0 0x440>; 301 #power-domain-cells = <1>; 302 }; 303 304 thermal: thermal@e6190000 { 305 compatible = "renesas,thermal-r8a77970"; 306 reg = <0 0xe6190000 0 0x10>, 307 <0 0xe6190100 0 0x120>; 308 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&cpg CPG_MOD 522>; 312 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 313 resets = <&cpg 522>; 314 #thermal-sensor-cells = <0>; 315 }; 316 317 intc_ex: interrupt-controller@e61c0000 { 318 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 reg = <0 0xe61c0000 0 0x200>; 322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cpg CPG_MOD 407>; 329 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 330 resets = <&cpg 407>; 331 }; 332 333 tmu0: timer@e61e0000 { 334 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 335 reg = <0 0xe61e0000 0 0x30>; 336 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&cpg CPG_MOD 125>; 340 clock-names = "fck"; 341 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 342 resets = <&cpg 125>; 343 status = "disabled"; 344 }; 345 346 tmu1: timer@e6fc0000 { 347 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 348 reg = <0 0xe6fc0000 0 0x30>; 349 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 352 clocks = <&cpg CPG_MOD 124>; 353 clock-names = "fck"; 354 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 355 resets = <&cpg 124>; 356 status = "disabled"; 357 }; 358 359 tmu2: timer@e6fd0000 { 360 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 361 reg = <0 0xe6fd0000 0 0x30>; 362 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cpg CPG_MOD 123>; 366 clock-names = "fck"; 367 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 368 resets = <&cpg 123>; 369 status = "disabled"; 370 }; 371 372 tmu3: timer@e6fe0000 { 373 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 374 reg = <0 0xe6fe0000 0 0x30>; 375 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 378 clocks = <&cpg CPG_MOD 122>; 379 clock-names = "fck"; 380 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 381 resets = <&cpg 122>; 382 status = "disabled"; 383 }; 384 385 tmu4: timer@ffc00000 { 386 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 387 reg = <0 0xffc00000 0 0x30>; 388 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&cpg CPG_MOD 121>; 392 clock-names = "fck"; 393 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 394 resets = <&cpg 121>; 395 status = "disabled"; 396 }; 397 398 i2c0: i2c@e6500000 { 399 compatible = "renesas,i2c-r8a77970", 400 "renesas,rcar-gen3-i2c"; 401 reg = <0 0xe6500000 0 0x40>; 402 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&cpg CPG_MOD 931>; 404 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 405 resets = <&cpg 931>; 406 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 407 <&dmac2 0x91>, <&dmac2 0x90>; 408 dma-names = "tx", "rx", "tx", "rx"; 409 i2c-scl-internal-delay-ns = <6>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 status = "disabled"; 413 }; 414 415 i2c1: i2c@e6508000 { 416 compatible = "renesas,i2c-r8a77970", 417 "renesas,rcar-gen3-i2c"; 418 reg = <0 0xe6508000 0 0x40>; 419 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&cpg CPG_MOD 930>; 421 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 422 resets = <&cpg 930>; 423 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 424 <&dmac2 0x93>, <&dmac2 0x92>; 425 dma-names = "tx", "rx", "tx", "rx"; 426 i2c-scl-internal-delay-ns = <6>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 i2c2: i2c@e6510000 { 433 compatible = "renesas,i2c-r8a77970", 434 "renesas,rcar-gen3-i2c"; 435 reg = <0 0xe6510000 0 0x40>; 436 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&cpg CPG_MOD 929>; 438 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 439 resets = <&cpg 929>; 440 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 441 <&dmac2 0x95>, <&dmac2 0x94>; 442 dma-names = "tx", "rx", "tx", "rx"; 443 i2c-scl-internal-delay-ns = <6>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 status = "disabled"; 447 }; 448 449 i2c3: i2c@e66d0000 { 450 compatible = "renesas,i2c-r8a77970", 451 "renesas,rcar-gen3-i2c"; 452 reg = <0 0xe66d0000 0 0x40>; 453 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 454 clocks = <&cpg CPG_MOD 928>; 455 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 456 resets = <&cpg 928>; 457 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 458 <&dmac2 0x97>, <&dmac2 0x96>; 459 dma-names = "tx", "rx", "tx", "rx"; 460 i2c-scl-internal-delay-ns = <6>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 status = "disabled"; 464 }; 465 466 i2c4: i2c@e66d8000 { 467 compatible = "renesas,i2c-r8a77970", 468 "renesas,rcar-gen3-i2c"; 469 reg = <0 0xe66d8000 0 0x40>; 470 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&cpg CPG_MOD 927>; 472 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 473 resets = <&cpg 927>; 474 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 475 <&dmac2 0x99>, <&dmac2 0x98>; 476 dma-names = "tx", "rx", "tx", "rx"; 477 i2c-scl-internal-delay-ns = <6>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 status = "disabled"; 481 }; 482 483 hscif0: serial@e6540000 { 484 compatible = "renesas,hscif-r8a77970", 485 "renesas,rcar-gen3-hscif", 486 "renesas,hscif"; 487 reg = <0 0xe6540000 0 96>; 488 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&cpg CPG_MOD 520>, 490 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 491 <&scif_clk>; 492 clock-names = "fck", "brg_int", "scif_clk"; 493 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 494 <&dmac2 0x31>, <&dmac2 0x30>; 495 dma-names = "tx", "rx", "tx", "rx"; 496 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 497 resets = <&cpg 520>; 498 status = "disabled"; 499 }; 500 501 hscif1: serial@e6550000 { 502 compatible = "renesas,hscif-r8a77970", 503 "renesas,rcar-gen3-hscif", 504 "renesas,hscif"; 505 reg = <0 0xe6550000 0 96>; 506 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cpg CPG_MOD 519>, 508 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 509 <&scif_clk>; 510 clock-names = "fck", "brg_int", "scif_clk"; 511 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 512 <&dmac2 0x33>, <&dmac2 0x32>; 513 dma-names = "tx", "rx", "tx", "rx"; 514 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 515 resets = <&cpg 519>; 516 status = "disabled"; 517 }; 518 519 hscif2: serial@e6560000 { 520 compatible = "renesas,hscif-r8a77970", 521 "renesas,rcar-gen3-hscif", 522 "renesas,hscif"; 523 reg = <0 0xe6560000 0 96>; 524 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&cpg CPG_MOD 518>, 526 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 527 <&scif_clk>; 528 clock-names = "fck", "brg_int", "scif_clk"; 529 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 530 <&dmac2 0x35>, <&dmac2 0x34>; 531 dma-names = "tx", "rx", "tx", "rx"; 532 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 533 resets = <&cpg 518>; 534 status = "disabled"; 535 }; 536 537 hscif3: serial@e66a0000 { 538 compatible = "renesas,hscif-r8a77970", 539 "renesas,rcar-gen3-hscif", "renesas,hscif"; 540 reg = <0 0xe66a0000 0 96>; 541 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&cpg CPG_MOD 517>, 543 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 544 <&scif_clk>; 545 clock-names = "fck", "brg_int", "scif_clk"; 546 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 547 <&dmac2 0x37>, <&dmac2 0x36>; 548 dma-names = "tx", "rx", "tx", "rx"; 549 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 550 resets = <&cpg 517>; 551 status = "disabled"; 552 }; 553 554 canfd: can@e66c0000 { 555 compatible = "renesas,r8a77970-canfd", 556 "renesas,rcar-gen3-canfd"; 557 reg = <0 0xe66c0000 0 0x8000>; 558 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "ch_int", "g_int"; 561 clocks = <&cpg CPG_MOD 914>, 562 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 563 <&can_clk>; 564 clock-names = "fck", "canfd", "can_clk"; 565 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 566 assigned-clock-rates = <40000000>; 567 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 568 resets = <&cpg 914>; 569 status = "disabled"; 570 571 channel0 { 572 status = "disabled"; 573 }; 574 575 channel1 { 576 status = "disabled"; 577 }; 578 }; 579 580 avb: ethernet@e6800000 { 581 compatible = "renesas,etheravb-r8a77970", 582 "renesas,etheravb-rcar-gen3"; 583 reg = <0 0xe6800000 0 0x800>; 584 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 609 interrupt-names = "ch0", "ch1", "ch2", "ch3", 610 "ch4", "ch5", "ch6", "ch7", 611 "ch8", "ch9", "ch10", "ch11", 612 "ch12", "ch13", "ch14", "ch15", 613 "ch16", "ch17", "ch18", "ch19", 614 "ch20", "ch21", "ch22", "ch23", 615 "ch24"; 616 clocks = <&cpg CPG_MOD 812>; 617 clock-names = "fck"; 618 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 619 resets = <&cpg 812>; 620 phy-mode = "rgmii"; 621 rx-internal-delay-ps = <0>; 622 tx-internal-delay-ps = <0>; 623 iommus = <&ipmmu_rt 3>; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 status = "disabled"; 627 }; 628 629 pwm0: pwm@e6e30000 { 630 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 631 reg = <0 0xe6e30000 0 8>; 632 #pwm-cells = <2>; 633 clocks = <&cpg CPG_MOD 523>; 634 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 635 resets = <&cpg 523>; 636 status = "disabled"; 637 }; 638 639 pwm1: pwm@e6e31000 { 640 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 641 reg = <0 0xe6e31000 0 8>; 642 #pwm-cells = <2>; 643 clocks = <&cpg CPG_MOD 523>; 644 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 645 resets = <&cpg 523>; 646 status = "disabled"; 647 }; 648 649 pwm2: pwm@e6e32000 { 650 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 651 reg = <0 0xe6e32000 0 8>; 652 #pwm-cells = <2>; 653 clocks = <&cpg CPG_MOD 523>; 654 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 655 resets = <&cpg 523>; 656 status = "disabled"; 657 }; 658 659 pwm3: pwm@e6e33000 { 660 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 661 reg = <0 0xe6e33000 0 8>; 662 #pwm-cells = <2>; 663 clocks = <&cpg CPG_MOD 523>; 664 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 665 resets = <&cpg 523>; 666 status = "disabled"; 667 }; 668 669 pwm4: pwm@e6e34000 { 670 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 671 reg = <0 0xe6e34000 0 8>; 672 #pwm-cells = <2>; 673 clocks = <&cpg CPG_MOD 523>; 674 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 675 resets = <&cpg 523>; 676 status = "disabled"; 677 }; 678 679 scif0: serial@e6e60000 { 680 compatible = "renesas,scif-r8a77970", 681 "renesas,rcar-gen3-scif", 682 "renesas,scif"; 683 reg = <0 0xe6e60000 0 64>; 684 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&cpg CPG_MOD 207>, 686 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 687 <&scif_clk>; 688 clock-names = "fck", "brg_int", "scif_clk"; 689 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 690 <&dmac2 0x51>, <&dmac2 0x50>; 691 dma-names = "tx", "rx", "tx", "rx"; 692 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 693 resets = <&cpg 207>; 694 status = "disabled"; 695 }; 696 697 scif1: serial@e6e68000 { 698 compatible = "renesas,scif-r8a77970", 699 "renesas,rcar-gen3-scif", 700 "renesas,scif"; 701 reg = <0 0xe6e68000 0 64>; 702 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&cpg CPG_MOD 206>, 704 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 705 <&scif_clk>; 706 clock-names = "fck", "brg_int", "scif_clk"; 707 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 708 <&dmac2 0x53>, <&dmac2 0x52>; 709 dma-names = "tx", "rx", "tx", "rx"; 710 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 711 resets = <&cpg 206>; 712 status = "disabled"; 713 }; 714 715 scif3: serial@e6c50000 { 716 compatible = "renesas,scif-r8a77970", 717 "renesas,rcar-gen3-scif", 718 "renesas,scif"; 719 reg = <0 0xe6c50000 0 64>; 720 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&cpg CPG_MOD 204>, 722 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 723 <&scif_clk>; 724 clock-names = "fck", "brg_int", "scif_clk"; 725 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 726 <&dmac2 0x57>, <&dmac2 0x56>; 727 dma-names = "tx", "rx", "tx", "rx"; 728 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 729 resets = <&cpg 204>; 730 status = "disabled"; 731 }; 732 733 scif4: serial@e6c40000 { 734 compatible = "renesas,scif-r8a77970", 735 "renesas,rcar-gen3-scif", "renesas,scif"; 736 reg = <0 0xe6c40000 0 64>; 737 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 738 clocks = <&cpg CPG_MOD 203>, 739 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 740 <&scif_clk>; 741 clock-names = "fck", "brg_int", "scif_clk"; 742 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 743 <&dmac2 0x59>, <&dmac2 0x58>; 744 dma-names = "tx", "rx", "tx", "rx"; 745 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 746 resets = <&cpg 203>; 747 status = "disabled"; 748 }; 749 750 tpu: pwm@e6e80000 { 751 compatible = "renesas,tpu-r8a77970", "renesas,tpu"; 752 reg = <0 0xe6e80000 0 0x148>; 753 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&cpg CPG_MOD 304>; 755 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 756 resets = <&cpg 304>; 757 #pwm-cells = <3>; 758 status = "disabled"; 759 }; 760 761 msiof0: spi@e6e90000 { 762 compatible = "renesas,msiof-r8a77970", 763 "renesas,rcar-gen3-msiof"; 764 reg = <0 0xe6e90000 0 0x64>; 765 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&cpg CPG_MOD 211>; 767 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 768 resets = <&cpg 211>; 769 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 770 <&dmac2 0x41>, <&dmac2 0x40>; 771 dma-names = "tx", "rx", "tx", "rx"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 status = "disabled"; 775 }; 776 777 msiof1: spi@e6ea0000 { 778 compatible = "renesas,msiof-r8a77970", 779 "renesas,rcar-gen3-msiof"; 780 reg = <0 0xe6ea0000 0 0x0064>; 781 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&cpg CPG_MOD 210>; 783 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 784 resets = <&cpg 210>; 785 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 786 <&dmac2 0x43>, <&dmac2 0x42>; 787 dma-names = "tx", "rx", "tx", "rx"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 msiof2: spi@e6c00000 { 794 compatible = "renesas,msiof-r8a77970", 795 "renesas,rcar-gen3-msiof"; 796 reg = <0 0xe6c00000 0 0x0064>; 797 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&cpg CPG_MOD 209>; 799 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 800 resets = <&cpg 209>; 801 dmas = <&dmac1 0x45>, <&dmac1 0x44>, 802 <&dmac2 0x45>, <&dmac2 0x44>; 803 dma-names = "tx", "rx", "tx", "rx"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 status = "disabled"; 807 }; 808 809 msiof3: spi@e6c10000 { 810 compatible = "renesas,msiof-r8a77970", 811 "renesas,rcar-gen3-msiof"; 812 reg = <0 0xe6c10000 0 0x0064>; 813 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&cpg CPG_MOD 208>; 815 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 816 resets = <&cpg 208>; 817 dmas = <&dmac1 0x47>, <&dmac1 0x46>, 818 <&dmac2 0x47>, <&dmac2 0x46>; 819 dma-names = "tx", "rx", "tx", "rx"; 820 #address-cells = <1>; 821 #size-cells = <0>; 822 status = "disabled"; 823 }; 824 825 vin0: video@e6ef0000 { 826 compatible = "renesas,vin-r8a77970"; 827 reg = <0 0xe6ef0000 0 0x1000>; 828 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 811>; 830 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 831 resets = <&cpg 811>; 832 renesas,id = <0>; 833 status = "disabled"; 834 835 ports { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 839 port@1 { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 reg = <1>; 844 845 vin0csi40: endpoint@2 { 846 reg = <2>; 847 remote-endpoint = <&csi40vin0>; 848 }; 849 }; 850 }; 851 }; 852 853 vin1: video@e6ef1000 { 854 compatible = "renesas,vin-r8a77970"; 855 reg = <0 0xe6ef1000 0 0x1000>; 856 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&cpg CPG_MOD 810>; 858 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 859 resets = <&cpg 810>; 860 renesas,id = <1>; 861 status = "disabled"; 862 863 ports { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 867 port@1 { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 871 reg = <1>; 872 873 vin1csi40: endpoint@2 { 874 reg = <2>; 875 remote-endpoint = <&csi40vin1>; 876 }; 877 }; 878 }; 879 }; 880 881 vin2: video@e6ef2000 { 882 compatible = "renesas,vin-r8a77970"; 883 reg = <0 0xe6ef2000 0 0x1000>; 884 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&cpg CPG_MOD 809>; 886 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 887 resets = <&cpg 809>; 888 renesas,id = <2>; 889 status = "disabled"; 890 891 ports { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 895 port@1 { 896 #address-cells = <1>; 897 #size-cells = <0>; 898 899 reg = <1>; 900 901 vin2csi40: endpoint@2 { 902 reg = <2>; 903 remote-endpoint = <&csi40vin2>; 904 }; 905 }; 906 }; 907 }; 908 909 vin3: video@e6ef3000 { 910 compatible = "renesas,vin-r8a77970"; 911 reg = <0 0xe6ef3000 0 0x1000>; 912 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&cpg CPG_MOD 808>; 914 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 915 resets = <&cpg 808>; 916 renesas,id = <3>; 917 status = "disabled"; 918 919 ports { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 923 port@1 { 924 #address-cells = <1>; 925 #size-cells = <0>; 926 927 reg = <1>; 928 929 vin3csi40: endpoint@2 { 930 reg = <2>; 931 remote-endpoint = <&csi40vin3>; 932 }; 933 }; 934 }; 935 }; 936 937 dmac1: dma-controller@e7300000 { 938 compatible = "renesas,dmac-r8a77970", 939 "renesas,rcar-dmac"; 940 reg = <0 0xe7300000 0 0x10000>; 941 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "error", 951 "ch0", "ch1", "ch2", "ch3", 952 "ch4", "ch5", "ch6", "ch7"; 953 clocks = <&cpg CPG_MOD 218>; 954 clock-names = "fck"; 955 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 956 resets = <&cpg 218>; 957 #dma-cells = <1>; 958 dma-channels = <8>; 959 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 960 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 961 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 962 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 963 }; 964 965 dmac2: dma-controller@e7310000 { 966 compatible = "renesas,dmac-r8a77970", 967 "renesas,rcar-dmac"; 968 reg = <0 0xe7310000 0 0x10000>; 969 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 978 interrupt-names = "error", 979 "ch0", "ch1", "ch2", "ch3", 980 "ch4", "ch5", "ch6", "ch7"; 981 clocks = <&cpg CPG_MOD 217>; 982 clock-names = "fck"; 983 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 984 resets = <&cpg 217>; 985 #dma-cells = <1>; 986 dma-channels = <8>; 987 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 988 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 989 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 990 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 991 }; 992 993 ipmmu_ds1: iommu@e7740000 { 994 compatible = "renesas,ipmmu-r8a77970"; 995 reg = <0 0xe7740000 0 0x1000>; 996 renesas,ipmmu-main = <&ipmmu_mm 0>; 997 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 998 #iommu-cells = <1>; 999 }; 1000 1001 ipmmu_ir: iommu@ff8b0000 { 1002 compatible = "renesas,ipmmu-r8a77970"; 1003 reg = <0 0xff8b0000 0 0x1000>; 1004 renesas,ipmmu-main = <&ipmmu_mm 3>; 1005 power-domains = <&sysc R8A77970_PD_A3IR>; 1006 #iommu-cells = <1>; 1007 }; 1008 1009 ipmmu_mm: iommu@e67b0000 { 1010 compatible = "renesas,ipmmu-r8a77970"; 1011 reg = <0 0xe67b0000 0 0x1000>; 1012 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1014 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1015 #iommu-cells = <1>; 1016 }; 1017 1018 ipmmu_rt: iommu@ffc80000 { 1019 compatible = "renesas,ipmmu-r8a77970"; 1020 reg = <0 0xffc80000 0 0x1000>; 1021 renesas,ipmmu-main = <&ipmmu_mm 7>; 1022 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1023 #iommu-cells = <1>; 1024 }; 1025 1026 ipmmu_vi0: iommu@febd0000 { 1027 compatible = "renesas,ipmmu-r8a77970"; 1028 reg = <0 0xfebd0000 0 0x1000>; 1029 renesas,ipmmu-main = <&ipmmu_mm 9>; 1030 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1031 #iommu-cells = <1>; 1032 }; 1033 1034 mmc0: mmc@ee140000 { 1035 compatible = "renesas,sdhi-r8a77970", 1036 "renesas,rcar-gen3-sdhi"; 1037 reg = <0 0xee140000 0 0x2000>; 1038 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&cpg CPG_MOD 314>; 1040 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1041 resets = <&cpg 314>; 1042 max-frequency = <200000000>; 1043 iommus = <&ipmmu_ds1 32>; 1044 status = "disabled"; 1045 }; 1046 1047 rpc: spi@ee200000 { 1048 compatible = "renesas,r8a77970-rpc-if", 1049 "renesas,rcar-gen3-rpc-if"; 1050 reg = <0 0xee200000 0 0x200>, 1051 <0 0x08000000 0 0x4000000>, 1052 <0 0xee208000 0 0x100>; 1053 reg-names = "regs", "dirmap", "wbuf"; 1054 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&cpg CPG_MOD 917>; 1056 clock-names = "rpc"; 1057 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1058 resets = <&cpg 917>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 gic: interrupt-controller@f1010000 { 1065 compatible = "arm,gic-400"; 1066 #interrupt-cells = <3>; 1067 #address-cells = <0>; 1068 interrupt-controller; 1069 reg = <0 0xf1010000 0 0x1000>, 1070 <0 0xf1020000 0 0x20000>, 1071 <0 0xf1040000 0 0x20000>, 1072 <0 0xf1060000 0 0x20000>; 1073 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 1074 IRQ_TYPE_LEVEL_HIGH)>; 1075 clocks = <&cpg CPG_MOD 408>; 1076 clock-names = "clk"; 1077 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1078 resets = <&cpg 408>; 1079 }; 1080 1081 vspd0: vsp@fea20000 { 1082 compatible = "renesas,vsp2"; 1083 reg = <0 0xfea20000 0 0x5000>; 1084 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cpg CPG_MOD 623>; 1086 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1087 resets = <&cpg 623>; 1088 renesas,fcp = <&fcpvd0>; 1089 }; 1090 1091 fcpvd0: fcp@fea27000 { 1092 compatible = "renesas,fcpv"; 1093 reg = <0 0xfea27000 0 0x200>; 1094 clocks = <&cpg CPG_MOD 603>; 1095 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1096 resets = <&cpg 603>; 1097 }; 1098 1099 csi40: csi2@feaa0000 { 1100 compatible = "renesas,r8a77970-csi2"; 1101 reg = <0 0xfeaa0000 0 0x10000>; 1102 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&cpg CPG_MOD 716>; 1104 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1105 resets = <&cpg 716>; 1106 status = "disabled"; 1107 1108 ports { 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 1112 port@0 { 1113 reg = <0>; 1114 }; 1115 1116 port@1 { 1117 #address-cells = <1>; 1118 #size-cells = <0>; 1119 1120 reg = <1>; 1121 1122 csi40vin0: endpoint@0 { 1123 reg = <0>; 1124 remote-endpoint = <&vin0csi40>; 1125 }; 1126 csi40vin1: endpoint@1 { 1127 reg = <1>; 1128 remote-endpoint = <&vin1csi40>; 1129 }; 1130 csi40vin2: endpoint@2 { 1131 reg = <2>; 1132 remote-endpoint = <&vin2csi40>; 1133 }; 1134 csi40vin3: endpoint@3 { 1135 reg = <3>; 1136 remote-endpoint = <&vin3csi40>; 1137 }; 1138 }; 1139 }; 1140 }; 1141 1142 du: display@feb00000 { 1143 compatible = "renesas,du-r8a77970"; 1144 reg = <0 0xfeb00000 0 0x80000>; 1145 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&cpg CPG_MOD 724>; 1147 clock-names = "du.0"; 1148 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1149 resets = <&cpg 724>; 1150 reset-names = "du.0"; 1151 renesas,vsps = <&vspd0 0>; 1152 1153 status = "disabled"; 1154 1155 ports { 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 1159 port@0 { 1160 reg = <0>; 1161 }; 1162 1163 port@1 { 1164 reg = <1>; 1165 du_out_lvds0: endpoint { 1166 remote-endpoint = <&lvds0_in>; 1167 }; 1168 }; 1169 }; 1170 }; 1171 1172 lvds0: lvds-encoder@feb90000 { 1173 compatible = "renesas,r8a77970-lvds"; 1174 reg = <0 0xfeb90000 0 0x14>; 1175 clocks = <&cpg CPG_MOD 727>; 1176 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1177 resets = <&cpg 727>; 1178 status = "disabled"; 1179 1180 ports { 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 1184 port@0 { 1185 reg = <0>; 1186 lvds0_in: endpoint { 1187 remote-endpoint = 1188 <&du_out_lvds0>; 1189 }; 1190 }; 1191 port@1 { 1192 reg = <1>; 1193 }; 1194 }; 1195 }; 1196 1197 prr: chipid@fff00044 { 1198 compatible = "renesas,prr"; 1199 reg = <0 0xfff00044 0 4>; 1200 }; 1201 }; 1202 1203 thermal-zones { 1204 cpu-thermal { 1205 polling-delay-passive = <250>; 1206 polling-delay = <1000>; 1207 thermal-sensors = <&thermal>; 1208 1209 cooling-maps { 1210 }; 1211 1212 trips { 1213 cpu-crit { 1214 temperature = <120000>; 1215 hysteresis = <2000>; 1216 type = "critical"; 1217 }; 1218 }; 1219 }; 1220 }; 1221 1222 timer { 1223 compatible = "arm,armv8-timer"; 1224 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1225 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1226 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1227 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1228 }; 1229 };
Cache object: c957478cac371d72d6ff88294ddf2a34
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