r8a77980-v3hsk.dts

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Device Tree Source for the V3H Starter Kit board
    4  *
    5  * Copyright (C) 2018 Renesas Electronics Corp.
    6  * Copyright (C) 2018 Cogent Embedded, Inc.
    7  */
    8 
    9 /dts-v1/;
   10 #include "r8a77980.dtsi"
   11 #include <dt-bindings/gpio/gpio.h>
   12 
   13 / {
   14         model = "Renesas V3H Starter Kit board";
   15         compatible = "renesas,v3hsk", "renesas,r8a77980";
   16 
   17         aliases {
   18                 serial0 = &scif0;
   19                 ethernet0 = &gether;
   20         };
   21 
   22         chosen {
   23                 stdout-path = "serial0:115200n8";
   24         };
   25 
   26         hdmi-out {
   27                 compatible = "hdmi-connector";
   28                 type = "a";
   29 
   30                 port {
   31                         hdmi_con: endpoint {
   32                                 remote-endpoint = <&adv7511_out>;
   33                         };
   34                 };
   35         };
   36 
   37         lvds-decoder {
   38                 compatible = "thine,thc63lvd1024";
   39                 vcc-supply = <&vcc3v3_d5>;
   40 
   41                 ports {
   42                         #address-cells = <1>;
   43                         #size-cells = <0>;
   44 
   45                         port@0 {
   46                                 reg = <0>;
   47                                 thc63lvd1024_in: endpoint {
   48                                         remote-endpoint = <&lvds0_out>;
   49                                 };
   50                         };
   51 
   52                         port@2 {
   53                                 reg = <2>;
   54                                 thc63lvd1024_out: endpoint {
   55                                         remote-endpoint = <&adv7511_in>;
   56                                 };
   57                         };
   58                 };
   59         };
   60 
   61         memory@48000000 {
   62                 device_type = "memory";
   63                 /* first 128MB is reserved for secure area. */
   64                 reg = <0 0x48000000 0 0x78000000>;
   65         };
   66 
   67         osc1_clk: osc1-clock {
   68                 compatible = "fixed-clock";
   69                 #clock-cells = <0>;
   70                 clock-frequency = <148500000>;
   71         };
   72 
   73         vcc1v8_d4: regulator-0 {
   74                 compatible = "regulator-fixed";
   75                 regulator-name = "VCC1V8_D4";
   76                 regulator-min-microvolt = <1800000>;
   77                 regulator-max-microvolt = <1800000>;
   78                 regulator-boot-on;
   79                 regulator-always-on;
   80         };
   81 
   82         vcc3v3_d5: regulator-1 {
   83                 compatible = "regulator-fixed";
   84                 regulator-name = "VCC3V3_D5";
   85                 regulator-min-microvolt = <3300000>;
   86                 regulator-max-microvolt = <3300000>;
   87                 regulator-boot-on;
   88                 regulator-always-on;
   89         };
   90 };
   91 
   92 &du {
   93         clocks = <&cpg CPG_MOD 724>,
   94                  <&osc1_clk>;
   95         clock-names = "du.0", "dclkin.0";
   96         status = "okay";
   97 };
   98 
   99 &extal_clk {
  100         clock-frequency = <16666666>;
  101 };
  102 
  103 &extalr_clk {
  104         clock-frequency = <32768>;
  105 };
  106 
  107 &gether {
  108         pinctrl-0 = <&gether_pins>;
  109         pinctrl-names = "default";
  110 
  111         phy-mode = "rgmii";
  112         phy-handle = <&phy0>;
  113         renesas,no-ether-link;
  114         status = "okay";
  115 
  116         phy0: ethernet-phy@0 {
  117                 compatible = "ethernet-phy-id0022.1622",
  118                              "ethernet-phy-ieee802.3-c22";
  119                 reg = <0>;
  120                 interrupt-parent = <&gpio4>;
  121                 interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
  122                 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
  123         };
  124 };
  125 
  126 &i2c0 {
  127         pinctrl-0 = <&i2c0_pins>;
  128         pinctrl-names = "default";
  129 
  130         status = "okay";
  131         clock-frequency = <400000>;
  132 
  133         hdmi@39 {
  134                 compatible = "adi,adv7511w";
  135                 #sound-dai-cells = <0>;
  136                 reg = <0x39>;
  137                 interrupt-parent = <&gpio1>;
  138                 interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
  139                 avdd-supply = <&vcc1v8_d4>;
  140                 dvdd-supply = <&vcc1v8_d4>;
  141                 pvdd-supply = <&vcc1v8_d4>;
  142                 bgvdd-supply = <&vcc1v8_d4>;
  143                 dvdd-3v-supply = <&vcc3v3_d5>;
  144 
  145                 adi,input-depth = <8>;
  146                 adi,input-colorspace = "rgb";
  147                 adi,input-clock = "1x";
  148 
  149                 ports {
  150                         #address-cells = <1>;
  151                         #size-cells = <0>;
  152 
  153                         port@0 {
  154                                 reg = <0>;
  155                                 adv7511_in: endpoint {
  156                                         remote-endpoint = <&thc63lvd1024_out>;
  157                                 };
  158                         };
  159 
  160                         port@1 {
  161                                 reg = <1>;
  162                                 adv7511_out: endpoint {
  163                                         remote-endpoint = <&hdmi_con>;
  164                                 };
  165                         };
  166                 };
  167         };
  168 };
  169 
  170 &lvds0 {
  171         status = "okay";
  172 
  173         ports {
  174                 port@1 {
  175                         lvds0_out: endpoint {
  176                                 remote-endpoint = <&thc63lvd1024_in>;
  177                         };
  178                 };
  179         };
  180 };
  181 
  182 &pfc {
  183         gether_pins: gether {
  184                 groups = "gether_mdio_a", "gether_rgmii",
  185                          "gether_txcrefclk", "gether_txcrefclk_mega";
  186                 function = "gether";
  187         };
  188 
  189         i2c0_pins: i2c0 {
  190                 groups = "i2c0";
  191                 function = "i2c0";
  192         };
  193 
  194         qspi0_pins: qspi0 {
  195                 groups = "qspi0_ctrl", "qspi0_data4";
  196                 function = "qspi0";
  197         };
  198 
  199         scif0_pins: scif0 {
  200                 groups = "scif0_data";
  201                 function = "scif0";
  202         };
  203 
  204         scif_clk_pins: scif_clk {
  205                 groups = "scif_clk_b";
  206                 function = "scif_clk";
  207         };
  208 };
  209 
  210 &rpc {
  211         pinctrl-0 = <&qspi0_pins>;
  212         pinctrl-names = "default";
  213 
  214         status = "okay";
  215 
  216         flash@0 {
  217                 compatible = "spansion,s25fs512s", "jedec,spi-nor";
  218                 reg = <0>;
  219                 spi-max-frequency = <50000000>;
  220                 spi-rx-bus-width = <4>;
  221 
  222                 partitions {
  223                         compatible = "fixed-partitions";
  224                         #address-cells = <1>;
  225                         #size-cells = <1>;
  226 
  227                         bootparam@0 {
  228                                 reg = <0x00000000 0x040000>;
  229                                 read-only;
  230                         };
  231                         cr7@40000 {
  232                                 reg = <0x00040000 0x080000>;
  233                                 read-only;
  234                         };
  235                         cert_header_sa3@c0000 {
  236                                 reg = <0x000c0000 0x080000>;
  237                                 read-only;
  238                         };
  239                         bl2@140000 {
  240                                 reg = <0x00140000 0x040000>;
  241                                 read-only;
  242                         };
  243                         cert_header_sa6@180000 {
  244                                 reg = <0x00180000 0x040000>;
  245                                 read-only;
  246                         };
  247                         bl31@1c0000 {
  248                                 reg = <0x001c0000 0x460000>;
  249                                 read-only;
  250                         };
  251                         uboot@640000 {
  252                                 reg = <0x00640000 0x0c0000>;
  253                                 read-only;
  254                         };
  255                         uboot-env@700000 {
  256                                 reg = <0x00700000 0x040000>;
  257                                 read-only;
  258                         };
  259                         dtb@740000 {
  260                                 reg = <0x00740000 0x080000>;
  261                         };
  262                         kernel@7c0000 {
  263                                 reg = <0x007c0000 0x1400000>;
  264                         };
  265                         user@1bc0000 {
  266                                 reg = <0x01bc0000 0x2440000>;
  267                         };
  268                 };
  269         };
  270 };
  271 
  272 &rwdt {
  273         timeout-sec = <60>;
  274         status = "okay";
  275 };
  276 
  277 &scif0 {
  278         pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
  279         pinctrl-names = "default";
  280 
  281         status = "okay";
  282 };
  283 
  284 &scif_clk {
  285         clock-frequency = <14745600>;
  286 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/renesas/r8a77980-v3hsk.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/renesas/r8a77980-v3hsk.dts