1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
2 /*
3 * Device Tree Source for the Spider CPU board
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8 #include "r8a779f0.dtsi"
9
10 / {
11 model = "Renesas Spider CPU board";
12 compatible = "renesas,spider-cpu", "renesas,r8a779f0";
13
14 memory@48000000 {
15 device_type = "memory";
16 /* first 128MB is reserved for secure area. */
17 reg = <0x0 0x48000000 0x0 0x78000000>;
18 };
19
20 memory@480000000 {
21 device_type = "memory";
22 reg = <0x4 0x80000000 0x0 0x80000000>;
23 };
24 };
25
26 &extal_clk {
27 clock-frequency = <20000000>;
28 };
29
30 &extalr_clk {
31 clock-frequency = <32768>;
32 };
33
34 &i2c4 {
35 pinctrl-0 = <&i2c4_pins>;
36 pinctrl-names = "default";
37
38 status = "okay";
39 clock-frequency = <400000>;
40
41 eeprom@50 {
42 compatible = "rohm,br24g01", "atmel,24c01";
43 label = "cpu-board";
44 reg = <0x50>;
45 pagesize = <8>;
46 };
47 };
48
49 &pfc {
50 pinctrl-0 = <&scif_clk_pins>;
51 pinctrl-names = "default";
52
53 i2c4_pins: i2c4 {
54 groups = "i2c4";
55 function = "i2c4";
56 };
57
58 scif0_pins: scif0 {
59 groups = "scif0_data", "scif0_ctrl";
60 function = "scif0";
61 };
62
63 scif3_pins: scif3 {
64 groups = "scif3_data", "scif3_ctrl";
65 function = "scif3";
66 };
67
68 scif_clk_pins: scif_clk {
69 groups = "scif_clk";
70 function = "scif_clk";
71 };
72 };
73
74 &rwdt {
75 timeout-sec = <60>;
76 status = "okay";
77 };
78
79 &scif0 {
80 pinctrl-0 = <&scif0_pins>;
81 pinctrl-names = "default";
82
83 uart-has-rtscts;
84 status = "okay";
85 };
86
87 &scif3 {
88 pinctrl-0 = <&scif3_pins>;
89 pinctrl-names = "default";
90
91 uart-has-rtscts;
92 status = "okay";
93 };
94
95 &scif_clk {
96 clock-frequency = <24000000>;
97 };
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