Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/contrib/device-tree/src/arm64/renesas/r9a09g011.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 3 * Device Tree Source for the RZ/V2M SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a09g011-cpg.h> 10 11 / { 12 compatible = "renesas,r9a09g011"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 17 extal_clk: extal { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu-map { 29 cluster0 { 30 core0 { 31 cpu = <&cpu0>; 32 }; 33 }; 34 }; 35 36 cpu0: cpu@0 { 37 compatible = "arm,cortex-a53"; 38 reg = <0>; 39 device_type = "cpu"; 40 clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; 41 }; 42 }; 43 44 soc: soc { 45 compatible = "simple-bus"; 46 interrupt-parent = <&gic>; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 ranges; 50 51 gic: interrupt-controller@82000000 { 52 compatible = "arm,gic-400"; 53 #interrupt-cells = <3>; 54 #address-cells = <0>; 55 interrupt-controller; 56 reg = <0x0 0x82010000 0 0x1000>, 57 <0x0 0x82020000 0 0x20000>, 58 <0x0 0x82040000 0 0x20000>, 59 <0x0 0x82060000 0 0x20000>; 60 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 61 clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; 62 clock-names = "clk"; 63 }; 64 65 avb: ethernet@a3300000 { 66 compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m"; 67 reg = <0 0xa3300000 0 0x800>; 68 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */ 69 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */ 70 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 71 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 72 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 73 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */ 87 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */ 88 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 89 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */ 91 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */ 92 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */ 93 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */ 94 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */ 95 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */ 96 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */ 97 interrupt-names = "ch0", "ch1", "ch2", "ch3", 98 "ch4", "ch5", "ch6", "ch7", 99 "ch8", "ch9", "ch10", "ch11", 100 "ch12", "ch13", "ch14", "ch15", 101 "ch16", "ch17", "ch18", "ch19", 102 "ch20", "ch21", "dia", "dib", 103 "err_a", "err_b", "mgmt_a", "mgmt_b", 104 "line3"; 105 clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>, 106 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>, 107 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>; 108 clock-names = "axi", "chi", "gptp"; 109 resets = <&cpg R9A09G011_ETH0_RST_HW_N>; 110 power-domains = <&cpg>; 111 #address-cells = <1>; 112 #size-cells = <0>; 113 status = "disable"; 114 }; 115 116 cpg: clock-controller@a3500000 { 117 compatible = "renesas,r9a09g011-cpg"; 118 reg = <0 0xa3500000 0 0x1000>; 119 clocks = <&extal_clk>; 120 clock-names = "extal"; 121 #clock-cells = <2>; 122 #reset-cells = <1>; 123 #power-domain-cells = <0>; 124 }; 125 126 uart0: serial@a4040000 { 127 compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; 128 reg = <0 0xa4040000 0 0x80>; 129 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 130 clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, 131 <&cpg CPG_MOD R9A09G011_URT_PCLK>; 132 clock-names = "sclk", "pclk"; 133 status = "disabled"; 134 }; 135 }; 136 137 timer { 138 compatible = "arm,armv8-timer"; 139 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 140 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 141 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 142 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 143 }; 144 };
Cache object: 4bc334fc52e7237de696556dc14507d3
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