rzg2lc-smarc.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
    2 /*
    3  * Device Tree Source for the RZ/G2LC SMARC EVK parts
    4  *
    5  * Copyright (C) 2022 Renesas Electronics Corp.
    6  */
    7 
    8 #include <dt-bindings/gpio/gpio.h>
    9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
   10 
   11 /*
   12  * DIP-Switch SW1 setting on SoM
   13  * 1 : High; 0: Low
   14  * SW1-2 : SW_SD0_DEV_SEL       (1: eMMC; 0: uSD)
   15  * SW1-3 : SW_SCIF_CAN          (1: CAN1; 0: SCIF1)
   16  * SW1-4 : SW_RSPI_CAN          (1: CAN1; 0: RSPI1)
   17  * SW1-5 : SW_I2S0_I2S1         (1: I2S2 (HDMI audio); 0: I2S0)
   18  * Please change below macros according to SW1 setting
   19  */
   20 
   21 #define SW_SD0_DEV_SEL  1
   22 
   23 #define SW_SCIF_CAN     0
   24 #if (SW_SCIF_CAN)
   25 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
   26 #define SW_RSPI_CAN     0
   27 #else
   28 /* Please set SW_RSPI_CAN. Default value is 1 */
   29 #define SW_RSPI_CAN     1
   30 #endif
   31 
   32 #if (SW_SCIF_CAN && SW_RSPI_CAN)
   33 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
   34 #endif
   35 
   36 #include "rzg2lc-smarc-som.dtsi"
   37 #include "rzg2lc-smarc-pinfunction.dtsi"
   38 #include "rz-smarc-common.dtsi"
   39 
   40 /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
   41 #define PMOD1_SER0      1
   42 
   43 / {
   44         aliases {
   45                 serial1 = &scif1;
   46                 i2c2 = &i2c2;
   47         };
   48 };
   49 
   50 #if (SW_SCIF_CAN || SW_RSPI_CAN)
   51 &canfd {
   52         pinctrl-0 = <&can1_pins>;
   53         /delete-node/ channel@0;
   54 };
   55 #else
   56 &canfd {
   57         /delete-property/ pinctrl-0;
   58         /delete-property/ pinctrl-names;
   59         status = "disabled";
   60 };
   61 #endif
   62 
   63 &cpu_dai {
   64         sound-dai = <&ssi0>;
   65 };
   66 
   67 &i2c2 {
   68         pinctrl-0 = <&i2c2_pins>;
   69         pinctrl-names = "default";
   70         clock-frequency = <400000>;
   71 
   72         status = "okay";
   73 
   74         wm8978: codec@1a {
   75                 compatible = "wlf,wm8978";
   76                 #sound-dai-cells = <0>;
   77                 reg = <0x1a>;
   78         };
   79 };
   80 
   81 /*
   82  * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
   83  * SW1 should be at position 2->3 so that SER0_CTS# line is activated
   84  * SW2 should be at position 2->3 so that SER0_TX line is activated
   85  * SW3 should be at position 2->3 so that SER0_RX line is activated
   86  * SW4 should be at position 2->3 so that SER0_RTS# line is activated
   87  */
   88 #if (!SW_SCIF_CAN && PMOD1_SER0)
   89 &scif1 {
   90         pinctrl-0 = <&scif1_pins>;
   91         pinctrl-names = "default";
   92 
   93         uart-has-rtscts;
   94         status = "okay";
   95 };
   96 #endif
   97 
   98 &ssi0 {
   99         pinctrl-0 = <&ssi0_pins>;
  100         pinctrl-names = "default";
  101 
  102         status = "okay";
  103 };
  104 
  105 #if (SW_RSPI_CAN)
  106 &spi1 {
  107         /delete-property/ pinctrl-0;
  108         /delete-property/ pinctrl-names;
  109         status = "disabled";
  110 };
  111 #endif
  112 
  113 &vccq_sdhi1 {
  114         gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
  115 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi