rk3399.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
    4  */
    5 
    6 #include <dt-bindings/clock/rk3399-cru.h>
    7 #include <dt-bindings/gpio/gpio.h>
    8 #include <dt-bindings/interrupt-controller/arm-gic.h>
    9 #include <dt-bindings/interrupt-controller/irq.h>
   10 #include <dt-bindings/pinctrl/rockchip.h>
   11 #include <dt-bindings/power/rk3399-power.h>
   12 #include <dt-bindings/thermal/thermal.h>
   13 
   14 / {
   15         compatible = "rockchip,rk3399";
   16 
   17         interrupt-parent = <&gic>;
   18         #address-cells = <2>;
   19         #size-cells = <2>;
   20 
   21         aliases {
   22                 ethernet0 = &gmac;
   23                 i2c0 = &i2c0;
   24                 i2c1 = &i2c1;
   25                 i2c2 = &i2c2;
   26                 i2c3 = &i2c3;
   27                 i2c4 = &i2c4;
   28                 i2c5 = &i2c5;
   29                 i2c6 = &i2c6;
   30                 i2c7 = &i2c7;
   31                 i2c8 = &i2c8;
   32                 serial0 = &uart0;
   33                 serial1 = &uart1;
   34                 serial2 = &uart2;
   35                 serial3 = &uart3;
   36                 serial4 = &uart4;
   37         };
   38 
   39         cpus {
   40                 #address-cells = <2>;
   41                 #size-cells = <0>;
   42 
   43                 cpu-map {
   44                         cluster0 {
   45                                 core0 {
   46                                         cpu = <&cpu_l0>;
   47                                 };
   48                                 core1 {
   49                                         cpu = <&cpu_l1>;
   50                                 };
   51                                 core2 {
   52                                         cpu = <&cpu_l2>;
   53                                 };
   54                                 core3 {
   55                                         cpu = <&cpu_l3>;
   56                                 };
   57                         };
   58 
   59                         cluster1 {
   60                                 core0 {
   61                                         cpu = <&cpu_b0>;
   62                                 };
   63                                 core1 {
   64                                         cpu = <&cpu_b1>;
   65                                 };
   66                         };
   67                 };
   68 
   69                 cpu_l0: cpu@0 {
   70                         device_type = "cpu";
   71                         compatible = "arm,cortex-a53";
   72                         reg = <0x0 0x0>;
   73                         enable-method = "psci";
   74                         capacity-dmips-mhz = <485>;
   75                         clocks = <&cru ARMCLKL>;
   76                         #cooling-cells = <2>; /* min followed by max */
   77                         dynamic-power-coefficient = <100>;
   78                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   79                 };
   80 
   81                 cpu_l1: cpu@1 {
   82                         device_type = "cpu";
   83                         compatible = "arm,cortex-a53";
   84                         reg = <0x0 0x1>;
   85                         enable-method = "psci";
   86                         capacity-dmips-mhz = <485>;
   87                         clocks = <&cru ARMCLKL>;
   88                         #cooling-cells = <2>; /* min followed by max */
   89                         dynamic-power-coefficient = <100>;
   90                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
   91                 };
   92 
   93                 cpu_l2: cpu@2 {
   94                         device_type = "cpu";
   95                         compatible = "arm,cortex-a53";
   96                         reg = <0x0 0x2>;
   97                         enable-method = "psci";
   98                         capacity-dmips-mhz = <485>;
   99                         clocks = <&cru ARMCLKL>;
  100                         #cooling-cells = <2>; /* min followed by max */
  101                         dynamic-power-coefficient = <100>;
  102                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  103                 };
  104 
  105                 cpu_l3: cpu@3 {
  106                         device_type = "cpu";
  107                         compatible = "arm,cortex-a53";
  108                         reg = <0x0 0x3>;
  109                         enable-method = "psci";
  110                         capacity-dmips-mhz = <485>;
  111                         clocks = <&cru ARMCLKL>;
  112                         #cooling-cells = <2>; /* min followed by max */
  113                         dynamic-power-coefficient = <100>;
  114                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  115                 };
  116 
  117                 cpu_b0: cpu@100 {
  118                         device_type = "cpu";
  119                         compatible = "arm,cortex-a72";
  120                         reg = <0x0 0x100>;
  121                         enable-method = "psci";
  122                         capacity-dmips-mhz = <1024>;
  123                         clocks = <&cru ARMCLKB>;
  124                         #cooling-cells = <2>; /* min followed by max */
  125                         dynamic-power-coefficient = <436>;
  126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  127 
  128                         thermal-idle {
  129                                 #cooling-cells = <2>;
  130                                 duration-us = <10000>;
  131                                 exit-latency-us = <500>;
  132                         };
  133                 };
  134 
  135                 cpu_b1: cpu@101 {
  136                         device_type = "cpu";
  137                         compatible = "arm,cortex-a72";
  138                         reg = <0x0 0x101>;
  139                         enable-method = "psci";
  140                         capacity-dmips-mhz = <1024>;
  141                         clocks = <&cru ARMCLKB>;
  142                         #cooling-cells = <2>; /* min followed by max */
  143                         dynamic-power-coefficient = <436>;
  144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  145 
  146                         thermal-idle {
  147                                 #cooling-cells = <2>;
  148                                 duration-us = <10000>;
  149                                 exit-latency-us = <500>;
  150                         };
  151                 };
  152 
  153                 idle-states {
  154                         entry-method = "psci";
  155 
  156                         CPU_SLEEP: cpu-sleep {
  157                                 compatible = "arm,idle-state";
  158                                 local-timer-stop;
  159                                 arm,psci-suspend-param = <0x0010000>;
  160                                 entry-latency-us = <120>;
  161                                 exit-latency-us = <250>;
  162                                 min-residency-us = <900>;
  163                         };
  164 
  165                         CLUSTER_SLEEP: cluster-sleep {
  166                                 compatible = "arm,idle-state";
  167                                 local-timer-stop;
  168                                 arm,psci-suspend-param = <0x1010000>;
  169                                 entry-latency-us = <400>;
  170                                 exit-latency-us = <500>;
  171                                 min-residency-us = <2000>;
  172                         };
  173                 };
  174         };
  175 
  176         display-subsystem {
  177                 compatible = "rockchip,display-subsystem";
  178                 ports = <&vopl_out>, <&vopb_out>;
  179         };
  180 
  181         dmc: memory-controller {
  182                 compatible = "rockchip,rk3399-dmc";
  183                 rockchip,pmu = <&pmugrf>;
  184                 devfreq-events = <&dfi>;
  185                 clocks = <&cru SCLK_DDRC>;
  186                 clock-names = "dmc_clk";
  187                 status = "disabled";
  188         };
  189 
  190         pmu_a53 {
  191                 compatible = "arm,cortex-a53-pmu";
  192                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
  193         };
  194 
  195         pmu_a72 {
  196                 compatible = "arm,cortex-a72-pmu";
  197                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
  198         };
  199 
  200         psci {
  201                 compatible = "arm,psci-1.0";
  202                 method = "smc";
  203         };
  204 
  205         timer {
  206                 compatible = "arm,armv8-timer";
  207                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
  208                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
  209                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
  210                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
  211                 arm,no-tick-in-suspend;
  212         };
  213 
  214         xin24m: xin24m {
  215                 compatible = "fixed-clock";
  216                 clock-frequency = <24000000>;
  217                 clock-output-names = "xin24m";
  218                 #clock-cells = <0>;
  219         };
  220 
  221         pcie0: pcie@f8000000 {
  222                 compatible = "rockchip,rk3399-pcie";
  223                 reg = <0x0 0xf8000000 0x0 0x2000000>,
  224                       <0x0 0xfd000000 0x0 0x1000000>;
  225                 reg-names = "axi-base", "apb-base";
  226                 device_type = "pci";
  227                 #address-cells = <3>;
  228                 #size-cells = <2>;
  229                 #interrupt-cells = <1>;
  230                 aspm-no-l0s;
  231                 bus-range = <0x0 0x1f>;
  232                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
  233                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
  234                 clock-names = "aclk", "aclk-perf",
  235                               "hclk", "pm";
  236                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
  237                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
  238                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
  239                 interrupt-names = "sys", "legacy", "client";
  240                 interrupt-map-mask = <0 0 0 7>;
  241                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
  242                                 <0 0 0 2 &pcie0_intc 1>,
  243                                 <0 0 0 3 &pcie0_intc 2>,
  244                                 <0 0 0 4 &pcie0_intc 3>;
  245                 max-link-speed = <1>;
  246                 msi-map = <0x0 &its 0x0 0x1000>;
  247                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
  248                        <&pcie_phy 2>, <&pcie_phy 3>;
  249                 phy-names = "pcie-phy-0", "pcie-phy-1",
  250                             "pcie-phy-2", "pcie-phy-3";
  251                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
  252                          <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
  253                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
  254                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
  255                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
  256                          <&cru SRST_A_PCIE>;
  257                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
  258                               "pm", "pclk", "aclk";
  259                 status = "disabled";
  260 
  261                 pcie0_intc: interrupt-controller {
  262                         interrupt-controller;
  263                         #address-cells = <0>;
  264                         #interrupt-cells = <1>;
  265                 };
  266         };
  267 
  268         gmac: ethernet@fe300000 {
  269                 compatible = "rockchip,rk3399-gmac";
  270                 reg = <0x0 0xfe300000 0x0 0x10000>;
  271                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
  272                 interrupt-names = "macirq";
  273                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
  274                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
  275                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
  276                          <&cru PCLK_GMAC>;
  277                 clock-names = "stmmaceth", "mac_clk_rx",
  278                               "mac_clk_tx", "clk_mac_ref",
  279                               "clk_mac_refout", "aclk_mac",
  280                               "pclk_mac";
  281                 power-domains = <&power RK3399_PD_GMAC>;
  282                 resets = <&cru SRST_A_GMAC>;
  283                 reset-names = "stmmaceth";
  284                 rockchip,grf = <&grf>;
  285                 snps,txpbl = <0x4>;
  286                 status = "disabled";
  287         };
  288 
  289         sdio0: mmc@fe310000 {
  290                 compatible = "rockchip,rk3399-dw-mshc",
  291                              "rockchip,rk3288-dw-mshc";
  292                 reg = <0x0 0xfe310000 0x0 0x4000>;
  293                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
  294                 max-frequency = <150000000>;
  295                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
  296                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
  297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  298                 fifo-depth = <0x100>;
  299                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
  300                 resets = <&cru SRST_SDIO0>;
  301                 reset-names = "reset";
  302                 status = "disabled";
  303         };
  304 
  305         sdmmc: mmc@fe320000 {
  306                 compatible = "rockchip,rk3399-dw-mshc",
  307                              "rockchip,rk3288-dw-mshc";
  308                 reg = <0x0 0xfe320000 0x0 0x4000>;
  309                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
  310                 max-frequency = <150000000>;
  311                 assigned-clocks = <&cru HCLK_SD>;
  312                 assigned-clock-rates = <200000000>;
  313                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
  314                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
  315                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  316                 fifo-depth = <0x100>;
  317                 power-domains = <&power RK3399_PD_SD>;
  318                 resets = <&cru SRST_SDMMC>;
  319                 reset-names = "reset";
  320                 status = "disabled";
  321         };
  322 
  323         sdhci: mmc@fe330000 {
  324                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  325                 reg = <0x0 0xfe330000 0x0 0x10000>;
  326                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
  327                 arasan,soc-ctl-syscon = <&grf>;
  328                 assigned-clocks = <&cru SCLK_EMMC>;
  329                 assigned-clock-rates = <200000000>;
  330                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
  331                 clock-names = "clk_xin", "clk_ahb";
  332                 clock-output-names = "emmc_cardclock";
  333                 #clock-cells = <0>;
  334                 phys = <&emmc_phy>;
  335                 phy-names = "phy_arasan";
  336                 power-domains = <&power RK3399_PD_EMMC>;
  337                 disable-cqe-dcmd;
  338                 status = "disabled";
  339         };
  340 
  341         usb_host0_ehci: usb@fe380000 {
  342                 compatible = "generic-ehci";
  343                 reg = <0x0 0xfe380000 0x0 0x20000>;
  344                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
  345                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
  346                          <&u2phy0>;
  347                 phys = <&u2phy0_host>;
  348                 phy-names = "usb";
  349                 status = "disabled";
  350         };
  351 
  352         usb_host0_ohci: usb@fe3a0000 {
  353                 compatible = "generic-ohci";
  354                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
  355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
  356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
  357                          <&u2phy0>;
  358                 phys = <&u2phy0_host>;
  359                 phy-names = "usb";
  360                 status = "disabled";
  361         };
  362 
  363         usb_host1_ehci: usb@fe3c0000 {
  364                 compatible = "generic-ehci";
  365                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
  366                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
  367                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
  368                          <&u2phy1>;
  369                 phys = <&u2phy1_host>;
  370                 phy-names = "usb";
  371                 status = "disabled";
  372         };
  373 
  374         usb_host1_ohci: usb@fe3e0000 {
  375                 compatible = "generic-ohci";
  376                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
  377                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
  378                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
  379                          <&u2phy1>;
  380                 phys = <&u2phy1_host>;
  381                 phy-names = "usb";
  382                 status = "disabled";
  383         };
  384 
  385         debug@fe430000 {
  386                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
  387                 reg = <0 0xfe430000 0 0x1000>;
  388                 clocks = <&cru PCLK_COREDBG_L>;
  389                 clock-names = "apb_pclk";
  390                 cpu = <&cpu_l0>;
  391         };
  392 
  393         debug@fe432000 {
  394                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
  395                 reg = <0 0xfe432000 0 0x1000>;
  396                 clocks = <&cru PCLK_COREDBG_L>;
  397                 clock-names = "apb_pclk";
  398                 cpu = <&cpu_l1>;
  399         };
  400 
  401         debug@fe434000 {
  402                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
  403                 reg = <0 0xfe434000 0 0x1000>;
  404                 clocks = <&cru PCLK_COREDBG_L>;
  405                 clock-names = "apb_pclk";
  406                 cpu = <&cpu_l2>;
  407         };
  408 
  409         debug@fe436000 {
  410                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
  411                 reg = <0 0xfe436000 0 0x1000>;
  412                 clocks = <&cru PCLK_COREDBG_L>;
  413                 clock-names = "apb_pclk";
  414                 cpu = <&cpu_l3>;
  415         };
  416 
  417         debug@fe610000 {
  418                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
  419                 reg = <0 0xfe610000 0 0x1000>;
  420                 clocks = <&cru PCLK_COREDBG_B>;
  421                 clock-names = "apb_pclk";
  422                 cpu = <&cpu_b0>;
  423         };
  424 
  425         debug@fe710000 {
  426                 compatible = "arm,coresight-cpu-debug", "arm,primecell";
  427                 reg = <0 0xfe710000 0 0x1000>;
  428                 clocks = <&cru PCLK_COREDBG_B>;
  429                 clock-names = "apb_pclk";
  430                 cpu = <&cpu_b1>;
  431         };
  432 
  433         usbdrd3_0: usb@fe800000 {
  434                 compatible = "rockchip,rk3399-dwc3";
  435                 #address-cells = <2>;
  436                 #size-cells = <2>;
  437                 ranges;
  438                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
  439                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
  440                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
  441                 clock-names = "ref_clk", "suspend_clk",
  442                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
  443                               "aclk_usb3", "grf_clk";
  444                 resets = <&cru SRST_A_USB3_OTG0>;
  445                 reset-names = "usb3-otg";
  446                 status = "disabled";
  447 
  448                 usbdrd_dwc3_0: usb@fe800000 {
  449                         compatible = "snps,dwc3";
  450                         reg = <0x0 0xfe800000 0x0 0x100000>;
  451                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
  452                         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
  453                                  <&cru SCLK_USB3OTG0_SUSPEND>;
  454                         clock-names = "ref", "bus_early", "suspend";
  455                         dr_mode = "otg";
  456                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
  457                         phy-names = "usb2-phy", "usb3-phy";
  458                         phy_type = "utmi_wide";
  459                         snps,dis_enblslpm_quirk;
  460                         snps,dis-u2-freeclk-exists-quirk;
  461                         snps,dis_u2_susphy_quirk;
  462                         snps,dis-del-phy-power-chg-quirk;
  463                         snps,dis-tx-ipgap-linecheck-quirk;
  464                         power-domains = <&power RK3399_PD_USB3>;
  465                         status = "disabled";
  466                 };
  467         };
  468 
  469         usbdrd3_1: usb@fe900000 {
  470                 compatible = "rockchip,rk3399-dwc3";
  471                 #address-cells = <2>;
  472                 #size-cells = <2>;
  473                 ranges;
  474                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
  475                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
  476                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
  477                 clock-names = "ref_clk", "suspend_clk",
  478                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
  479                               "aclk_usb3", "grf_clk";
  480                 resets = <&cru SRST_A_USB3_OTG1>;
  481                 reset-names = "usb3-otg";
  482                 status = "disabled";
  483 
  484                 usbdrd_dwc3_1: usb@fe900000 {
  485                         compatible = "snps,dwc3";
  486                         reg = <0x0 0xfe900000 0x0 0x100000>;
  487                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
  488                         clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
  489                                  <&cru SCLK_USB3OTG1_SUSPEND>;
  490                         clock-names = "ref", "bus_early", "suspend";
  491                         dr_mode = "otg";
  492                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
  493                         phy-names = "usb2-phy", "usb3-phy";
  494                         phy_type = "utmi_wide";
  495                         snps,dis_enblslpm_quirk;
  496                         snps,dis-u2-freeclk-exists-quirk;
  497                         snps,dis_u2_susphy_quirk;
  498                         snps,dis-del-phy-power-chg-quirk;
  499                         snps,dis-tx-ipgap-linecheck-quirk;
  500                         power-domains = <&power RK3399_PD_USB3>;
  501                         status = "disabled";
  502                 };
  503         };
  504 
  505         cdn_dp: dp@fec00000 {
  506                 compatible = "rockchip,rk3399-cdn-dp";
  507                 reg = <0x0 0xfec00000 0x0 0x100000>;
  508                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
  509                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
  510                 assigned-clock-rates = <100000000>, <200000000>;
  511                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
  512                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
  513                 clock-names = "core-clk", "pclk", "spdif", "grf";
  514                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
  515                 power-domains = <&power RK3399_PD_HDCP>;
  516                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
  517                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
  518                 reset-names = "spdif", "dptx", "apb", "core";
  519                 rockchip,grf = <&grf>;
  520                 #sound-dai-cells = <1>;
  521                 status = "disabled";
  522 
  523                 ports {
  524                         dp_in: port {
  525                                 #address-cells = <1>;
  526                                 #size-cells = <0>;
  527 
  528                                 dp_in_vopb: endpoint@0 {
  529                                         reg = <0>;
  530                                         remote-endpoint = <&vopb_out_dp>;
  531                                 };
  532 
  533                                 dp_in_vopl: endpoint@1 {
  534                                         reg = <1>;
  535                                         remote-endpoint = <&vopl_out_dp>;
  536                                 };
  537                         };
  538                 };
  539         };
  540 
  541         gic: interrupt-controller@fee00000 {
  542                 compatible = "arm,gic-v3";
  543                 #interrupt-cells = <4>;
  544                 #address-cells = <2>;
  545                 #size-cells = <2>;
  546                 ranges;
  547                 interrupt-controller;
  548 
  549                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
  550                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
  551                       <0x0 0xfff00000 0 0x10000>, /* GICC */
  552                       <0x0 0xfff10000 0 0x10000>, /* GICH */
  553                       <0x0 0xfff20000 0 0x10000>; /* GICV */
  554                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
  555                 its: interrupt-controller@fee20000 {
  556                         compatible = "arm,gic-v3-its";
  557                         msi-controller;
  558                         #msi-cells = <1>;
  559                         reg = <0x0 0xfee20000 0x0 0x20000>;
  560                 };
  561 
  562                 ppi-partitions {
  563                         ppi_cluster0: interrupt-partition-0 {
  564                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
  565                         };
  566 
  567                         ppi_cluster1: interrupt-partition-1 {
  568                                 affinity = <&cpu_b0 &cpu_b1>;
  569                         };
  570                 };
  571         };
  572 
  573         saradc: saradc@ff100000 {
  574                 compatible = "rockchip,rk3399-saradc";
  575                 reg = <0x0 0xff100000 0x0 0x100>;
  576                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
  577                 #io-channel-cells = <1>;
  578                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
  579                 clock-names = "saradc", "apb_pclk";
  580                 resets = <&cru SRST_P_SARADC>;
  581                 reset-names = "saradc-apb";
  582                 status = "disabled";
  583         };
  584 
  585         i2c1: i2c@ff110000 {
  586                 compatible = "rockchip,rk3399-i2c";
  587                 reg = <0x0 0xff110000 0x0 0x1000>;
  588                 assigned-clocks = <&cru SCLK_I2C1>;
  589                 assigned-clock-rates = <200000000>;
  590                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
  591                 clock-names = "i2c", "pclk";
  592                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
  593                 pinctrl-names = "default";
  594                 pinctrl-0 = <&i2c1_xfer>;
  595                 #address-cells = <1>;
  596                 #size-cells = <0>;
  597                 status = "disabled";
  598         };
  599 
  600         i2c2: i2c@ff120000 {
  601                 compatible = "rockchip,rk3399-i2c";
  602                 reg = <0x0 0xff120000 0x0 0x1000>;
  603                 assigned-clocks = <&cru SCLK_I2C2>;
  604                 assigned-clock-rates = <200000000>;
  605                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
  606                 clock-names = "i2c", "pclk";
  607                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
  608                 pinctrl-names = "default";
  609                 pinctrl-0 = <&i2c2_xfer>;
  610                 #address-cells = <1>;
  611                 #size-cells = <0>;
  612                 status = "disabled";
  613         };
  614 
  615         i2c3: i2c@ff130000 {
  616                 compatible = "rockchip,rk3399-i2c";
  617                 reg = <0x0 0xff130000 0x0 0x1000>;
  618                 assigned-clocks = <&cru SCLK_I2C3>;
  619                 assigned-clock-rates = <200000000>;
  620                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
  621                 clock-names = "i2c", "pclk";
  622                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
  623                 pinctrl-names = "default";
  624                 pinctrl-0 = <&i2c3_xfer>;
  625                 #address-cells = <1>;
  626                 #size-cells = <0>;
  627                 status = "disabled";
  628         };
  629 
  630         i2c5: i2c@ff140000 {
  631                 compatible = "rockchip,rk3399-i2c";
  632                 reg = <0x0 0xff140000 0x0 0x1000>;
  633                 assigned-clocks = <&cru SCLK_I2C5>;
  634                 assigned-clock-rates = <200000000>;
  635                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
  636                 clock-names = "i2c", "pclk";
  637                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
  638                 pinctrl-names = "default";
  639                 pinctrl-0 = <&i2c5_xfer>;
  640                 #address-cells = <1>;
  641                 #size-cells = <0>;
  642                 status = "disabled";
  643         };
  644 
  645         i2c6: i2c@ff150000 {
  646                 compatible = "rockchip,rk3399-i2c";
  647                 reg = <0x0 0xff150000 0x0 0x1000>;
  648                 assigned-clocks = <&cru SCLK_I2C6>;
  649                 assigned-clock-rates = <200000000>;
  650                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
  651                 clock-names = "i2c", "pclk";
  652                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
  653                 pinctrl-names = "default";
  654                 pinctrl-0 = <&i2c6_xfer>;
  655                 #address-cells = <1>;
  656                 #size-cells = <0>;
  657                 status = "disabled";
  658         };
  659 
  660         i2c7: i2c@ff160000 {
  661                 compatible = "rockchip,rk3399-i2c";
  662                 reg = <0x0 0xff160000 0x0 0x1000>;
  663                 assigned-clocks = <&cru SCLK_I2C7>;
  664                 assigned-clock-rates = <200000000>;
  665                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
  666                 clock-names = "i2c", "pclk";
  667                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
  668                 pinctrl-names = "default";
  669                 pinctrl-0 = <&i2c7_xfer>;
  670                 #address-cells = <1>;
  671                 #size-cells = <0>;
  672                 status = "disabled";
  673         };
  674 
  675         uart0: serial@ff180000 {
  676                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  677                 reg = <0x0 0xff180000 0x0 0x100>;
  678                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  679                 clock-names = "baudclk", "apb_pclk";
  680                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
  681                 reg-shift = <2>;
  682                 reg-io-width = <4>;
  683                 pinctrl-names = "default";
  684                 pinctrl-0 = <&uart0_xfer>;
  685                 status = "disabled";
  686         };
  687 
  688         uart1: serial@ff190000 {
  689                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  690                 reg = <0x0 0xff190000 0x0 0x100>;
  691                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  692                 clock-names = "baudclk", "apb_pclk";
  693                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
  694                 reg-shift = <2>;
  695                 reg-io-width = <4>;
  696                 pinctrl-names = "default";
  697                 pinctrl-0 = <&uart1_xfer>;
  698                 status = "disabled";
  699         };
  700 
  701         uart2: serial@ff1a0000 {
  702                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  703                 reg = <0x0 0xff1a0000 0x0 0x100>;
  704                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
  705                 clock-names = "baudclk", "apb_pclk";
  706                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
  707                 reg-shift = <2>;
  708                 reg-io-width = <4>;
  709                 pinctrl-names = "default";
  710                 pinctrl-0 = <&uart2c_xfer>;
  711                 status = "disabled";
  712         };
  713 
  714         uart3: serial@ff1b0000 {
  715                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
  716                 reg = <0x0 0xff1b0000 0x0 0x100>;
  717                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
  718                 clock-names = "baudclk", "apb_pclk";
  719                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
  720                 reg-shift = <2>;
  721                 reg-io-width = <4>;
  722                 pinctrl-names = "default";
  723                 pinctrl-0 = <&uart3_xfer>;
  724                 status = "disabled";
  725         };
  726 
  727         spi0: spi@ff1c0000 {
  728                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  729                 reg = <0x0 0xff1c0000 0x0 0x1000>;
  730                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
  731                 clock-names = "spiclk", "apb_pclk";
  732                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
  733                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
  734                 dma-names = "tx", "rx";
  735                 pinctrl-names = "default";
  736                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
  737                 #address-cells = <1>;
  738                 #size-cells = <0>;
  739                 status = "disabled";
  740         };
  741 
  742         spi1: spi@ff1d0000 {
  743                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  744                 reg = <0x0 0xff1d0000 0x0 0x1000>;
  745                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
  746                 clock-names = "spiclk", "apb_pclk";
  747                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
  748                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
  749                 dma-names = "tx", "rx";
  750                 pinctrl-names = "default";
  751                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
  752                 #address-cells = <1>;
  753                 #size-cells = <0>;
  754                 status = "disabled";
  755         };
  756 
  757         spi2: spi@ff1e0000 {
  758                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  759                 reg = <0x0 0xff1e0000 0x0 0x1000>;
  760                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
  761                 clock-names = "spiclk", "apb_pclk";
  762                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
  763                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
  764                 dma-names = "tx", "rx";
  765                 pinctrl-names = "default";
  766                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
  767                 #address-cells = <1>;
  768                 #size-cells = <0>;
  769                 status = "disabled";
  770         };
  771 
  772         spi4: spi@ff1f0000 {
  773                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  774                 reg = <0x0 0xff1f0000 0x0 0x1000>;
  775                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
  776                 clock-names = "spiclk", "apb_pclk";
  777                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
  778                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
  779                 dma-names = "tx", "rx";
  780                 pinctrl-names = "default";
  781                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
  782                 #address-cells = <1>;
  783                 #size-cells = <0>;
  784                 status = "disabled";
  785         };
  786 
  787         spi5: spi@ff200000 {
  788                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
  789                 reg = <0x0 0xff200000 0x0 0x1000>;
  790                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
  791                 clock-names = "spiclk", "apb_pclk";
  792                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
  793                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
  794                 dma-names = "tx", "rx";
  795                 pinctrl-names = "default";
  796                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
  797                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
  798                 #address-cells = <1>;
  799                 #size-cells = <0>;
  800                 status = "disabled";
  801         };
  802 
  803         thermal_zones: thermal-zones {
  804                 cpu_thermal: cpu-thermal {
  805                         polling-delay-passive = <100>;
  806                         polling-delay = <1000>;
  807 
  808                         thermal-sensors = <&tsadc 0>;
  809 
  810                         trips {
  811                                 cpu_alert0: cpu_alert0 {
  812                                         temperature = <70000>;
  813                                         hysteresis = <2000>;
  814                                         type = "passive";
  815                                 };
  816                                 cpu_alert1: cpu_alert1 {
  817                                         temperature = <75000>;
  818                                         hysteresis = <2000>;
  819                                         type = "passive";
  820                                 };
  821                                 cpu_crit: cpu_crit {
  822                                         temperature = <95000>;
  823                                         hysteresis = <2000>;
  824                                         type = "critical";
  825                                 };
  826                         };
  827 
  828                         cooling-maps {
  829                                 map0 {
  830                                         trip = <&cpu_alert0>;
  831                                         cooling-device =
  832                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  833                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  834                                 };
  835                                 map1 {
  836                                         trip = <&cpu_alert1>;
  837                                         cooling-device =
  838                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  839                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  840                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  841                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  842                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
  843                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  844                                 };
  845                         };
  846                 };
  847 
  848                 gpu_thermal: gpu-thermal {
  849                         polling-delay-passive = <100>;
  850                         polling-delay = <1000>;
  851 
  852                         thermal-sensors = <&tsadc 1>;
  853 
  854                         trips {
  855                                 gpu_alert0: gpu_alert0 {
  856                                         temperature = <75000>;
  857                                         hysteresis = <2000>;
  858                                         type = "passive";
  859                                 };
  860                                 gpu_crit: gpu_crit {
  861                                         temperature = <95000>;
  862                                         hysteresis = <2000>;
  863                                         type = "critical";
  864                                 };
  865                         };
  866 
  867                         cooling-maps {
  868                                 map0 {
  869                                         trip = <&gpu_alert0>;
  870                                         cooling-device =
  871                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  872                                 };
  873                         };
  874                 };
  875         };
  876 
  877         tsadc: tsadc@ff260000 {
  878                 compatible = "rockchip,rk3399-tsadc";
  879                 reg = <0x0 0xff260000 0x0 0x100>;
  880                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
  881                 assigned-clocks = <&cru SCLK_TSADC>;
  882                 assigned-clock-rates = <750000>;
  883                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
  884                 clock-names = "tsadc", "apb_pclk";
  885                 resets = <&cru SRST_TSADC>;
  886                 reset-names = "tsadc-apb";
  887                 rockchip,grf = <&grf>;
  888                 rockchip,hw-tshut-temp = <95000>;
  889                 pinctrl-names = "init", "default", "sleep";
  890                 pinctrl-0 = <&otp_pin>;
  891                 pinctrl-1 = <&otp_out>;
  892                 pinctrl-2 = <&otp_pin>;
  893                 #thermal-sensor-cells = <1>;
  894                 status = "disabled";
  895         };
  896 
  897         qos_emmc: qos@ffa58000 {
  898                 compatible = "rockchip,rk3399-qos", "syscon";
  899                 reg = <0x0 0xffa58000 0x0 0x20>;
  900         };
  901 
  902         qos_gmac: qos@ffa5c000 {
  903                 compatible = "rockchip,rk3399-qos", "syscon";
  904                 reg = <0x0 0xffa5c000 0x0 0x20>;
  905         };
  906 
  907         qos_pcie: qos@ffa60080 {
  908                 compatible = "rockchip,rk3399-qos", "syscon";
  909                 reg = <0x0 0xffa60080 0x0 0x20>;
  910         };
  911 
  912         qos_usb_host0: qos@ffa60100 {
  913                 compatible = "rockchip,rk3399-qos", "syscon";
  914                 reg = <0x0 0xffa60100 0x0 0x20>;
  915         };
  916 
  917         qos_usb_host1: qos@ffa60180 {
  918                 compatible = "rockchip,rk3399-qos", "syscon";
  919                 reg = <0x0 0xffa60180 0x0 0x20>;
  920         };
  921 
  922         qos_usb_otg0: qos@ffa70000 {
  923                 compatible = "rockchip,rk3399-qos", "syscon";
  924                 reg = <0x0 0xffa70000 0x0 0x20>;
  925         };
  926 
  927         qos_usb_otg1: qos@ffa70080 {
  928                 compatible = "rockchip,rk3399-qos", "syscon";
  929                 reg = <0x0 0xffa70080 0x0 0x20>;
  930         };
  931 
  932         qos_sd: qos@ffa74000 {
  933                 compatible = "rockchip,rk3399-qos", "syscon";
  934                 reg = <0x0 0xffa74000 0x0 0x20>;
  935         };
  936 
  937         qos_sdioaudio: qos@ffa76000 {
  938                 compatible = "rockchip,rk3399-qos", "syscon";
  939                 reg = <0x0 0xffa76000 0x0 0x20>;
  940         };
  941 
  942         qos_hdcp: qos@ffa90000 {
  943                 compatible = "rockchip,rk3399-qos", "syscon";
  944                 reg = <0x0 0xffa90000 0x0 0x20>;
  945         };
  946 
  947         qos_iep: qos@ffa98000 {
  948                 compatible = "rockchip,rk3399-qos", "syscon";
  949                 reg = <0x0 0xffa98000 0x0 0x20>;
  950         };
  951 
  952         qos_isp0_m0: qos@ffaa0000 {
  953                 compatible = "rockchip,rk3399-qos", "syscon";
  954                 reg = <0x0 0xffaa0000 0x0 0x20>;
  955         };
  956 
  957         qos_isp0_m1: qos@ffaa0080 {
  958                 compatible = "rockchip,rk3399-qos", "syscon";
  959                 reg = <0x0 0xffaa0080 0x0 0x20>;
  960         };
  961 
  962         qos_isp1_m0: qos@ffaa8000 {
  963                 compatible = "rockchip,rk3399-qos", "syscon";
  964                 reg = <0x0 0xffaa8000 0x0 0x20>;
  965         };
  966 
  967         qos_isp1_m1: qos@ffaa8080 {
  968                 compatible = "rockchip,rk3399-qos", "syscon";
  969                 reg = <0x0 0xffaa8080 0x0 0x20>;
  970         };
  971 
  972         qos_rga_r: qos@ffab0000 {
  973                 compatible = "rockchip,rk3399-qos", "syscon";
  974                 reg = <0x0 0xffab0000 0x0 0x20>;
  975         };
  976 
  977         qos_rga_w: qos@ffab0080 {
  978                 compatible = "rockchip,rk3399-qos", "syscon";
  979                 reg = <0x0 0xffab0080 0x0 0x20>;
  980         };
  981 
  982         qos_video_m0: qos@ffab8000 {
  983                 compatible = "rockchip,rk3399-qos", "syscon";
  984                 reg = <0x0 0xffab8000 0x0 0x20>;
  985         };
  986 
  987         qos_video_m1_r: qos@ffac0000 {
  988                 compatible = "rockchip,rk3399-qos", "syscon";
  989                 reg = <0x0 0xffac0000 0x0 0x20>;
  990         };
  991 
  992         qos_video_m1_w: qos@ffac0080 {
  993                 compatible = "rockchip,rk3399-qos", "syscon";
  994                 reg = <0x0 0xffac0080 0x0 0x20>;
  995         };
  996 
  997         qos_vop_big_r: qos@ffac8000 {
  998                 compatible = "rockchip,rk3399-qos", "syscon";
  999                 reg = <0x0 0xffac8000 0x0 0x20>;
 1000         };
 1001 
 1002         qos_vop_big_w: qos@ffac8080 {
 1003                 compatible = "rockchip,rk3399-qos", "syscon";
 1004                 reg = <0x0 0xffac8080 0x0 0x20>;
 1005         };
 1006 
 1007         qos_vop_little: qos@ffad0000 {
 1008                 compatible = "rockchip,rk3399-qos", "syscon";
 1009                 reg = <0x0 0xffad0000 0x0 0x20>;
 1010         };
 1011 
 1012         qos_perihp: qos@ffad8080 {
 1013                 compatible = "rockchip,rk3399-qos", "syscon";
 1014                 reg = <0x0 0xffad8080 0x0 0x20>;
 1015         };
 1016 
 1017         qos_gpu: qos@ffae0000 {
 1018                 compatible = "rockchip,rk3399-qos", "syscon";
 1019                 reg = <0x0 0xffae0000 0x0 0x20>;
 1020         };
 1021 
 1022         pmu: power-management@ff310000 {
 1023                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 1024                 reg = <0x0 0xff310000 0x0 0x1000>;
 1025 
 1026                 /*
 1027                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 1028                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 1029                  * Some of the power domains are grouped together for every
 1030                  * voltage domain.
 1031                  * The detail contents as below.
 1032                  */
 1033                 power: power-controller {
 1034                         compatible = "rockchip,rk3399-power-controller";
 1035                         #power-domain-cells = <1>;
 1036                         #address-cells = <1>;
 1037                         #size-cells = <0>;
 1038 
 1039                         /* These power domains are grouped by VD_CENTER */
 1040                         power-domain@RK3399_PD_IEP {
 1041                                 reg = <RK3399_PD_IEP>;
 1042                                 clocks = <&cru ACLK_IEP>,
 1043                                          <&cru HCLK_IEP>;
 1044                                 pm_qos = <&qos_iep>;
 1045                                 #power-domain-cells = <0>;
 1046                         };
 1047                         power-domain@RK3399_PD_RGA {
 1048                                 reg = <RK3399_PD_RGA>;
 1049                                 clocks = <&cru ACLK_RGA>,
 1050                                          <&cru HCLK_RGA>;
 1051                                 pm_qos = <&qos_rga_r>,
 1052                                          <&qos_rga_w>;
 1053                                 #power-domain-cells = <0>;
 1054                         };
 1055                         power-domain@RK3399_PD_VCODEC {
 1056                                 reg = <RK3399_PD_VCODEC>;
 1057                                 clocks = <&cru ACLK_VCODEC>,
 1058                                          <&cru HCLK_VCODEC>;
 1059                                 pm_qos = <&qos_video_m0>;
 1060                                 #power-domain-cells = <0>;
 1061                         };
 1062                         power-domain@RK3399_PD_VDU {
 1063                                 reg = <RK3399_PD_VDU>;
 1064                                 clocks = <&cru ACLK_VDU>,
 1065                                          <&cru HCLK_VDU>;
 1066                                 pm_qos = <&qos_video_m1_r>,
 1067                                          <&qos_video_m1_w>;
 1068                                 #power-domain-cells = <0>;
 1069                         };
 1070 
 1071                         /* These power domains are grouped by VD_GPU */
 1072                         power-domain@RK3399_PD_GPU {
 1073                                 reg = <RK3399_PD_GPU>;
 1074                                 clocks = <&cru ACLK_GPU>;
 1075                                 pm_qos = <&qos_gpu>;
 1076                                 #power-domain-cells = <0>;
 1077                         };
 1078 
 1079                         /* These power domains are grouped by VD_LOGIC */
 1080                         power-domain@RK3399_PD_EDP {
 1081                                 reg = <RK3399_PD_EDP>;
 1082                                 clocks = <&cru PCLK_EDP_CTRL>;
 1083                                 #power-domain-cells = <0>;
 1084                         };
 1085                         power-domain@RK3399_PD_EMMC {
 1086                                 reg = <RK3399_PD_EMMC>;
 1087                                 clocks = <&cru ACLK_EMMC>;
 1088                                 pm_qos = <&qos_emmc>;
 1089                                 #power-domain-cells = <0>;
 1090                         };
 1091                         power-domain@RK3399_PD_GMAC {
 1092                                 reg = <RK3399_PD_GMAC>;
 1093                                 clocks = <&cru ACLK_GMAC>,
 1094                                          <&cru PCLK_GMAC>;
 1095                                 pm_qos = <&qos_gmac>;
 1096                                 #power-domain-cells = <0>;
 1097                         };
 1098                         power-domain@RK3399_PD_SD {
 1099                                 reg = <RK3399_PD_SD>;
 1100                                 clocks = <&cru HCLK_SDMMC>,
 1101                                          <&cru SCLK_SDMMC>;
 1102                                 pm_qos = <&qos_sd>;
 1103                                 #power-domain-cells = <0>;
 1104                         };
 1105                         power-domain@RK3399_PD_SDIOAUDIO {
 1106                                 reg = <RK3399_PD_SDIOAUDIO>;
 1107                                 clocks = <&cru HCLK_SDIO>;
 1108                                 pm_qos = <&qos_sdioaudio>;
 1109                                 #power-domain-cells = <0>;
 1110                         };
 1111                         power-domain@RK3399_PD_TCPD0 {
 1112                                 reg = <RK3399_PD_TCPD0>;
 1113                                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 1114                                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
 1115                                 #power-domain-cells = <0>;
 1116                         };
 1117                         power-domain@RK3399_PD_TCPD1 {
 1118                                 reg = <RK3399_PD_TCPD1>;
 1119                                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 1120                                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
 1121                                 #power-domain-cells = <0>;
 1122                         };
 1123                         power-domain@RK3399_PD_USB3 {
 1124                                 reg = <RK3399_PD_USB3>;
 1125                                 clocks = <&cru ACLK_USB3>;
 1126                                 pm_qos = <&qos_usb_otg0>,
 1127                                          <&qos_usb_otg1>;
 1128                                 #power-domain-cells = <0>;
 1129                         };
 1130                         power-domain@RK3399_PD_VIO {
 1131                                 reg = <RK3399_PD_VIO>;
 1132                                 #power-domain-cells = <1>;
 1133                                 #address-cells = <1>;
 1134                                 #size-cells = <0>;
 1135 
 1136                                 power-domain@RK3399_PD_HDCP {
 1137                                         reg = <RK3399_PD_HDCP>;
 1138                                         clocks = <&cru ACLK_HDCP>,
 1139                                                  <&cru HCLK_HDCP>,
 1140                                                  <&cru PCLK_HDCP>;
 1141                                         pm_qos = <&qos_hdcp>;
 1142                                         #power-domain-cells = <0>;
 1143                                 };
 1144                                 power-domain@RK3399_PD_ISP0 {
 1145                                         reg = <RK3399_PD_ISP0>;
 1146                                         clocks = <&cru ACLK_ISP0>,
 1147                                                  <&cru HCLK_ISP0>;
 1148                                         pm_qos = <&qos_isp0_m0>,
 1149                                                  <&qos_isp0_m1>;
 1150                                         #power-domain-cells = <0>;
 1151                                 };
 1152                                 power-domain@RK3399_PD_ISP1 {
 1153                                         reg = <RK3399_PD_ISP1>;
 1154                                         clocks = <&cru ACLK_ISP1>,
 1155                                                  <&cru HCLK_ISP1>;
 1156                                         pm_qos = <&qos_isp1_m0>,
 1157                                                  <&qos_isp1_m1>;
 1158                                         #power-domain-cells = <0>;
 1159                                 };
 1160                                 power-domain@RK3399_PD_VO {
 1161                                         reg = <RK3399_PD_VO>;
 1162                                         #power-domain-cells = <1>;
 1163                                         #address-cells = <1>;
 1164                                         #size-cells = <0>;
 1165 
 1166                                         power-domain@RK3399_PD_VOPB {
 1167                                                 reg = <RK3399_PD_VOPB>;
 1168                                                 clocks = <&cru ACLK_VOP0>,
 1169                                                          <&cru HCLK_VOP0>;
 1170                                                 pm_qos = <&qos_vop_big_r>,
 1171                                                          <&qos_vop_big_w>;
 1172                                                 #power-domain-cells = <0>;
 1173                                         };
 1174                                         power-domain@RK3399_PD_VOPL {
 1175                                                 reg = <RK3399_PD_VOPL>;
 1176                                                 clocks = <&cru ACLK_VOP1>,
 1177                                                          <&cru HCLK_VOP1>;
 1178                                                 pm_qos = <&qos_vop_little>;
 1179                                                 #power-domain-cells = <0>;
 1180                                         };
 1181                                 };
 1182                         };
 1183                 };
 1184         };
 1185 
 1186         pmugrf: syscon@ff320000 {
 1187                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 1188                 reg = <0x0 0xff320000 0x0 0x1000>;
 1189 
 1190                 pmu_io_domains: io-domains {
 1191                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 1192                         status = "disabled";
 1193                 };
 1194         };
 1195 
 1196         spi3: spi@ff350000 {
 1197                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 1198                 reg = <0x0 0xff350000 0x0 0x1000>;
 1199                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 1200                 clock-names = "spiclk", "apb_pclk";
 1201                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
 1202                 pinctrl-names = "default";
 1203                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 1204                 #address-cells = <1>;
 1205                 #size-cells = <0>;
 1206                 status = "disabled";
 1207         };
 1208 
 1209         uart4: serial@ff370000 {
 1210                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 1211                 reg = <0x0 0xff370000 0x0 0x100>;
 1212                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 1213                 clock-names = "baudclk", "apb_pclk";
 1214                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
 1215                 reg-shift = <2>;
 1216                 reg-io-width = <4>;
 1217                 pinctrl-names = "default";
 1218                 pinctrl-0 = <&uart4_xfer>;
 1219                 status = "disabled";
 1220         };
 1221 
 1222         i2c0: i2c@ff3c0000 {
 1223                 compatible = "rockchip,rk3399-i2c";
 1224                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 1225                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 1226                 assigned-clock-rates = <200000000>;
 1227                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 1228                 clock-names = "i2c", "pclk";
 1229                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 1230                 pinctrl-names = "default";
 1231                 pinctrl-0 = <&i2c0_xfer>;
 1232                 #address-cells = <1>;
 1233                 #size-cells = <0>;
 1234                 status = "disabled";
 1235         };
 1236 
 1237         i2c4: i2c@ff3d0000 {
 1238                 compatible = "rockchip,rk3399-i2c";
 1239                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 1240                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 1241                 assigned-clock-rates = <200000000>;
 1242                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 1243                 clock-names = "i2c", "pclk";
 1244                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
 1245                 pinctrl-names = "default";
 1246                 pinctrl-0 = <&i2c4_xfer>;
 1247                 #address-cells = <1>;
 1248                 #size-cells = <0>;
 1249                 status = "disabled";
 1250         };
 1251 
 1252         i2c8: i2c@ff3e0000 {
 1253                 compatible = "rockchip,rk3399-i2c";
 1254                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 1255                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 1256                 assigned-clock-rates = <200000000>;
 1257                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 1258                 clock-names = "i2c", "pclk";
 1259                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 1260                 pinctrl-names = "default";
 1261                 pinctrl-0 = <&i2c8_xfer>;
 1262                 #address-cells = <1>;
 1263                 #size-cells = <0>;
 1264                 status = "disabled";
 1265         };
 1266 
 1267         pwm0: pwm@ff420000 {
 1268                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 1269                 reg = <0x0 0xff420000 0x0 0x10>;
 1270                 #pwm-cells = <3>;
 1271                 pinctrl-names = "default";
 1272                 pinctrl-0 = <&pwm0_pin>;
 1273                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 1274                 status = "disabled";
 1275         };
 1276 
 1277         pwm1: pwm@ff420010 {
 1278                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 1279                 reg = <0x0 0xff420010 0x0 0x10>;
 1280                 #pwm-cells = <3>;
 1281                 pinctrl-names = "default";
 1282                 pinctrl-0 = <&pwm1_pin>;
 1283                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 1284                 status = "disabled";
 1285         };
 1286 
 1287         pwm2: pwm@ff420020 {
 1288                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 1289                 reg = <0x0 0xff420020 0x0 0x10>;
 1290                 #pwm-cells = <3>;
 1291                 pinctrl-names = "default";
 1292                 pinctrl-0 = <&pwm2_pin>;
 1293                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 1294                 status = "disabled";
 1295         };
 1296 
 1297         pwm3: pwm@ff420030 {
 1298                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 1299                 reg = <0x0 0xff420030 0x0 0x10>;
 1300                 #pwm-cells = <3>;
 1301                 pinctrl-names = "default";
 1302                 pinctrl-0 = <&pwm3a_pin>;
 1303                 clocks = <&pmucru PCLK_RKPWM_PMU>;
 1304                 status = "disabled";
 1305         };
 1306 
 1307         dfi: dfi@ff630000 {
 1308                 reg = <0x00 0xff630000 0x00 0x4000>;
 1309                 compatible = "rockchip,rk3399-dfi";
 1310                 rockchip,pmu = <&pmugrf>;
 1311                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
 1312                 clocks = <&cru PCLK_DDR_MON>;
 1313                 clock-names = "pclk_ddr_mon";
 1314                 status = "disabled";
 1315         };
 1316 
 1317         vpu: video-codec@ff650000 {
 1318                 compatible = "rockchip,rk3399-vpu";
 1319                 reg = <0x0 0xff650000 0x0 0x800>;
 1320                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
 1321                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
 1322                 interrupt-names = "vepu", "vdpu";
 1323                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 1324                 clock-names = "aclk", "hclk";
 1325                 iommus = <&vpu_mmu>;
 1326                 power-domains = <&power RK3399_PD_VCODEC>;
 1327         };
 1328 
 1329         vpu_mmu: iommu@ff650800 {
 1330                 compatible = "rockchip,iommu";
 1331                 reg = <0x0 0xff650800 0x0 0x40>;
 1332                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 1333                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 1334                 clock-names = "aclk", "iface";
 1335                 #iommu-cells = <0>;
 1336                 power-domains = <&power RK3399_PD_VCODEC>;
 1337         };
 1338 
 1339         vdec: video-codec@ff660000 {
 1340                 compatible = "rockchip,rk3399-vdec";
 1341                 reg = <0x0 0xff660000 0x0 0x400>;
 1342                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 1343                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
 1344                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
 1345                 clock-names = "axi", "ahb", "cabac", "core";
 1346                 iommus = <&vdec_mmu>;
 1347                 power-domains = <&power RK3399_PD_VDU>;
 1348         };
 1349 
 1350         vdec_mmu: iommu@ff660480 {
 1351                 compatible = "rockchip,iommu";
 1352                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
 1353                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 1354                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
 1355                 clock-names = "aclk", "iface";
 1356                 power-domains = <&power RK3399_PD_VDU>;
 1357                 #iommu-cells = <0>;
 1358         };
 1359 
 1360         iep_mmu: iommu@ff670800 {
 1361                 compatible = "rockchip,iommu";
 1362                 reg = <0x0 0xff670800 0x0 0x40>;
 1363                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
 1364                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 1365                 clock-names = "aclk", "iface";
 1366                 #iommu-cells = <0>;
 1367                 status = "disabled";
 1368         };
 1369 
 1370         rga: rga@ff680000 {
 1371                 compatible = "rockchip,rk3399-rga";
 1372                 reg = <0x0 0xff680000 0x0 0x10000>;
 1373                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
 1374                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 1375                 clock-names = "aclk", "hclk", "sclk";
 1376                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
 1377                 reset-names = "core", "axi", "ahb";
 1378                 power-domains = <&power RK3399_PD_RGA>;
 1379         };
 1380 
 1381         efuse0: efuse@ff690000 {
 1382                 compatible = "rockchip,rk3399-efuse";
 1383                 reg = <0x0 0xff690000 0x0 0x80>;
 1384                 #address-cells = <1>;
 1385                 #size-cells = <1>;
 1386                 clocks = <&cru PCLK_EFUSE1024NS>;
 1387                 clock-names = "pclk_efuse";
 1388 
 1389                 /* Data cells */
 1390                 cpu_id: cpu-id@7 {
 1391                         reg = <0x07 0x10>;
 1392                 };
 1393                 cpub_leakage: cpu-leakage@17 {
 1394                         reg = <0x17 0x1>;
 1395                 };
 1396                 gpu_leakage: gpu-leakage@18 {
 1397                         reg = <0x18 0x1>;
 1398                 };
 1399                 center_leakage: center-leakage@19 {
 1400                         reg = <0x19 0x1>;
 1401                 };
 1402                 cpul_leakage: cpu-leakage@1a {
 1403                         reg = <0x1a 0x1>;
 1404                 };
 1405                 logic_leakage: logic-leakage@1b {
 1406                         reg = <0x1b 0x1>;
 1407                 };
 1408                 wafer_info: wafer-info@1c {
 1409                         reg = <0x1c 0x1>;
 1410                 };
 1411         };
 1412 
 1413         dmac_bus: dma-controller@ff6d0000 {
 1414                 compatible = "arm,pl330", "arm,primecell";
 1415                 reg = <0x0 0xff6d0000 0x0 0x4000>;
 1416                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 1417                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 1418                 #dma-cells = <1>;
 1419                 arm,pl330-periph-burst;
 1420                 clocks = <&cru ACLK_DMAC0_PERILP>;
 1421                 clock-names = "apb_pclk";
 1422         };
 1423 
 1424         dmac_peri: dma-controller@ff6e0000 {
 1425                 compatible = "arm,pl330", "arm,primecell";
 1426                 reg = <0x0 0xff6e0000 0x0 0x4000>;
 1427                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 1428                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 1429                 #dma-cells = <1>;
 1430                 arm,pl330-periph-burst;
 1431                 clocks = <&cru ACLK_DMAC1_PERILP>;
 1432                 clock-names = "apb_pclk";
 1433         };
 1434 
 1435         pmucru: clock-controller@ff750000 {
 1436                 compatible = "rockchip,rk3399-pmucru";
 1437                 reg = <0x0 0xff750000 0x0 0x1000>;
 1438                 clocks = <&xin24m>;
 1439                 clock-names = "xin24m";
 1440                 rockchip,grf = <&pmugrf>;
 1441                 #clock-cells = <1>;
 1442                 #reset-cells = <1>;
 1443                 assigned-clocks = <&pmucru PLL_PPLL>;
 1444                 assigned-clock-rates = <676000000>;
 1445         };
 1446 
 1447         cru: clock-controller@ff760000 {
 1448                 compatible = "rockchip,rk3399-cru";
 1449                 reg = <0x0 0xff760000 0x0 0x1000>;
 1450                 clocks = <&xin24m>;
 1451                 clock-names = "xin24m";
 1452                 rockchip,grf = <&grf>;
 1453                 #clock-cells = <1>;
 1454                 #reset-cells = <1>;
 1455                 assigned-clocks =
 1456                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 1457                         <&cru PLL_NPLL>,
 1458                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
 1459                         <&cru PCLK_PERIHP>,
 1460                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 1461                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
 1462                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
 1463                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
 1464                         <&cru ACLK_GIC_PRE>,
 1465                         <&cru PCLK_DDR>,
 1466                         <&cru ACLK_VDU>;
 1467                 assigned-clock-rates =
 1468                          <594000000>,  <800000000>,
 1469                         <1000000000>,
 1470                          <150000000>,   <75000000>,
 1471                           <37500000>,
 1472                          <100000000>,  <100000000>,
 1473                           <50000000>, <600000000>,
 1474                          <100000000>,   <50000000>,
 1475                          <400000000>, <400000000>,
 1476                          <200000000>,
 1477                          <200000000>,
 1478                          <400000000>;
 1479         };
 1480 
 1481         grf: syscon@ff770000 {
 1482                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
 1483                 reg = <0x0 0xff770000 0x0 0x10000>;
 1484                 #address-cells = <1>;
 1485                 #size-cells = <1>;
 1486 
 1487                 io_domains: io-domains {
 1488                         compatible = "rockchip,rk3399-io-voltage-domain";
 1489                         status = "disabled";
 1490                 };
 1491 
 1492                 mipi_dphy_rx0: mipi-dphy-rx0 {
 1493                         compatible = "rockchip,rk3399-mipi-dphy-rx0";
 1494                         clocks = <&cru SCLK_MIPIDPHY_REF>,
 1495                                  <&cru SCLK_DPHY_RX0_CFG>,
 1496                                  <&cru PCLK_VIO_GRF>;
 1497                         clock-names = "dphy-ref", "dphy-cfg", "grf";
 1498                         power-domains = <&power RK3399_PD_VIO>;
 1499                         #phy-cells = <0>;
 1500                         status = "disabled";
 1501                 };
 1502 
 1503                 u2phy0: usb2phy@e450 {
 1504                         compatible = "rockchip,rk3399-usb2phy";
 1505                         reg = <0xe450 0x10>;
 1506                         clocks = <&cru SCLK_USB2PHY0_REF>;
 1507                         clock-names = "phyclk";
 1508                         #clock-cells = <0>;
 1509                         clock-output-names = "clk_usbphy0_480m";
 1510                         status = "disabled";
 1511 
 1512                         u2phy0_host: host-port {
 1513                                 #phy-cells = <0>;
 1514                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
 1515                                 interrupt-names = "linestate";
 1516                                 status = "disabled";
 1517                         };
 1518 
 1519                         u2phy0_otg: otg-port {
 1520                                 #phy-cells = <0>;
 1521                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
 1522                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
 1523                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
 1524                                 interrupt-names = "otg-bvalid", "otg-id",
 1525                                                   "linestate";
 1526                                 status = "disabled";
 1527                         };
 1528                 };
 1529 
 1530                 u2phy1: usb2phy@e460 {
 1531                         compatible = "rockchip,rk3399-usb2phy";
 1532                         reg = <0xe460 0x10>;
 1533                         clocks = <&cru SCLK_USB2PHY1_REF>;
 1534                         clock-names = "phyclk";
 1535                         #clock-cells = <0>;
 1536                         clock-output-names = "clk_usbphy1_480m";
 1537                         status = "disabled";
 1538 
 1539                         u2phy1_host: host-port {
 1540                                 #phy-cells = <0>;
 1541                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
 1542                                 interrupt-names = "linestate";
 1543                                 status = "disabled";
 1544                         };
 1545 
 1546                         u2phy1_otg: otg-port {
 1547                                 #phy-cells = <0>;
 1548                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
 1549                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
 1550                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
 1551                                 interrupt-names = "otg-bvalid", "otg-id",
 1552                                                   "linestate";
 1553                                 status = "disabled";
 1554                         };
 1555                 };
 1556 
 1557                 emmc_phy: phy@f780 {
 1558                         compatible = "rockchip,rk3399-emmc-phy";
 1559                         reg = <0xf780 0x24>;
 1560                         clocks = <&sdhci>;
 1561                         clock-names = "emmcclk";
 1562                         drive-impedance-ohm = <50>;
 1563                         #phy-cells = <0>;
 1564                         status = "disabled";
 1565                 };
 1566 
 1567                 pcie_phy: pcie-phy {
 1568                         compatible = "rockchip,rk3399-pcie-phy";
 1569                         clocks = <&cru SCLK_PCIEPHY_REF>;
 1570                         clock-names = "refclk";
 1571                         #phy-cells = <1>;
 1572                         resets = <&cru SRST_PCIEPHY>;
 1573                         reset-names = "phy";
 1574                         status = "disabled";
 1575                 };
 1576         };
 1577 
 1578         tcphy0: phy@ff7c0000 {
 1579                 compatible = "rockchip,rk3399-typec-phy";
 1580                 reg = <0x0 0xff7c0000 0x0 0x40000>;
 1581                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 1582                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
 1583                 clock-names = "tcpdcore", "tcpdphy-ref";
 1584                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
 1585                 assigned-clock-rates = <50000000>;
 1586                 power-domains = <&power RK3399_PD_TCPD0>;
 1587                 resets = <&cru SRST_UPHY0>,
 1588                          <&cru SRST_UPHY0_PIPE_L00>,
 1589                          <&cru SRST_P_UPHY0_TCPHY>;
 1590                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
 1591                 rockchip,grf = <&grf>;
 1592                 status = "disabled";
 1593 
 1594                 tcphy0_dp: dp-port {
 1595                         #phy-cells = <0>;
 1596                 };
 1597 
 1598                 tcphy0_usb3: usb3-port {
 1599                         #phy-cells = <0>;
 1600                 };
 1601         };
 1602 
 1603         tcphy1: phy@ff800000 {
 1604                 compatible = "rockchip,rk3399-typec-phy";
 1605                 reg = <0x0 0xff800000 0x0 0x40000>;
 1606                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 1607                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
 1608                 clock-names = "tcpdcore", "tcpdphy-ref";
 1609                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
 1610                 assigned-clock-rates = <50000000>;
 1611                 power-domains = <&power RK3399_PD_TCPD1>;
 1612                 resets = <&cru SRST_UPHY1>,
 1613                          <&cru SRST_UPHY1_PIPE_L00>,
 1614                          <&cru SRST_P_UPHY1_TCPHY>;
 1615                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
 1616                 rockchip,grf = <&grf>;
 1617                 status = "disabled";
 1618 
 1619                 tcphy1_dp: dp-port {
 1620                         #phy-cells = <0>;
 1621                 };
 1622 
 1623                 tcphy1_usb3: usb3-port {
 1624                         #phy-cells = <0>;
 1625                 };
 1626         };
 1627 
 1628         watchdog@ff848000 {
 1629                 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt";
 1630                 reg = <0x0 0xff848000 0x0 0x100>;
 1631                 clocks = <&cru PCLK_WDT>;
 1632                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
 1633         };
 1634 
 1635         rktimer: rktimer@ff850000 {
 1636                 compatible = "rockchip,rk3399-timer";
 1637                 reg = <0x0 0xff850000 0x0 0x1000>;
 1638                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
 1639                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
 1640                 clock-names = "pclk", "timer";
 1641         };
 1642 
 1643         spdif: spdif@ff870000 {
 1644                 compatible = "rockchip,rk3399-spdif";
 1645                 reg = <0x0 0xff870000 0x0 0x1000>;
 1646                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
 1647                 dmas = <&dmac_bus 7>;
 1648                 dma-names = "tx";
 1649                 clock-names = "mclk", "hclk";
 1650                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 1651                 pinctrl-names = "default";
 1652                 pinctrl-0 = <&spdif_bus>;
 1653                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 1654                 #sound-dai-cells = <0>;
 1655                 status = "disabled";
 1656         };
 1657 
 1658         i2s0: i2s@ff880000 {
 1659                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 1660                 reg = <0x0 0xff880000 0x0 0x1000>;
 1661                 rockchip,grf = <&grf>;
 1662                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
 1663                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 1664                 dma-names = "tx", "rx";
 1665                 clock-names = "i2s_clk", "i2s_hclk";
 1666                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
 1667                 pinctrl-names = "default";
 1668                 pinctrl-0 = <&i2s0_8ch_bus>;
 1669                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 1670                 #sound-dai-cells = <0>;
 1671                 status = "disabled";
 1672         };
 1673 
 1674         i2s1: i2s@ff890000 {
 1675                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 1676                 reg = <0x0 0xff890000 0x0 0x1000>;
 1677                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
 1678                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 1679                 dma-names = "tx", "rx";
 1680                 clock-names = "i2s_clk", "i2s_hclk";
 1681                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
 1682                 pinctrl-names = "default";
 1683                 pinctrl-0 = <&i2s1_2ch_bus>;
 1684                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 1685                 #sound-dai-cells = <0>;
 1686                 status = "disabled";
 1687         };
 1688 
 1689         i2s2: i2s@ff8a0000 {
 1690                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 1691                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 1692                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
 1693                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 1694                 dma-names = "tx", "rx";
 1695                 clock-names = "i2s_clk", "i2s_hclk";
 1696                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
 1697                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 1698                 #sound-dai-cells = <0>;
 1699                 status = "disabled";
 1700         };
 1701 
 1702         vopl: vop@ff8f0000 {
 1703                 compatible = "rockchip,rk3399-vop-lit";
 1704                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
 1705                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 1706                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
 1707                 assigned-clock-rates = <400000000>, <100000000>;
 1708                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 1709                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 1710                 iommus = <&vopl_mmu>;
 1711                 power-domains = <&power RK3399_PD_VOPL>;
 1712                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
 1713                 reset-names = "axi", "ahb", "dclk";
 1714                 status = "disabled";
 1715 
 1716                 vopl_out: port {
 1717                         #address-cells = <1>;
 1718                         #size-cells = <0>;
 1719 
 1720                         vopl_out_mipi: endpoint@0 {
 1721                                 reg = <0>;
 1722                                 remote-endpoint = <&mipi_in_vopl>;
 1723                         };
 1724 
 1725                         vopl_out_edp: endpoint@1 {
 1726                                 reg = <1>;
 1727                                 remote-endpoint = <&edp_in_vopl>;
 1728                         };
 1729 
 1730                         vopl_out_hdmi: endpoint@2 {
 1731                                 reg = <2>;
 1732                                 remote-endpoint = <&hdmi_in_vopl>;
 1733                         };
 1734 
 1735                         vopl_out_mipi1: endpoint@3 {
 1736                                 reg = <3>;
 1737                                 remote-endpoint = <&mipi1_in_vopl>;
 1738                         };
 1739 
 1740                         vopl_out_dp: endpoint@4 {
 1741                                 reg = <4>;
 1742                                 remote-endpoint = <&dp_in_vopl>;
 1743                         };
 1744                 };
 1745         };
 1746 
 1747         vopl_mmu: iommu@ff8f3f00 {
 1748                 compatible = "rockchip,iommu";
 1749                 reg = <0x0 0xff8f3f00 0x0 0x100>;
 1750                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
 1751                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
 1752                 clock-names = "aclk", "iface";
 1753                 power-domains = <&power RK3399_PD_VOPL>;
 1754                 #iommu-cells = <0>;
 1755                 status = "disabled";
 1756         };
 1757 
 1758         vopb: vop@ff900000 {
 1759                 compatible = "rockchip,rk3399-vop-big";
 1760                 reg = <0x0 0xff900000 0x0 0x3efc>;
 1761                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
 1762                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
 1763                 assigned-clock-rates = <400000000>, <100000000>;
 1764                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 1765                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 1766                 iommus = <&vopb_mmu>;
 1767                 power-domains = <&power RK3399_PD_VOPB>;
 1768                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
 1769                 reset-names = "axi", "ahb", "dclk";
 1770                 status = "disabled";
 1771 
 1772                 vopb_out: port {
 1773                         #address-cells = <1>;
 1774                         #size-cells = <0>;
 1775 
 1776                         vopb_out_edp: endpoint@0 {
 1777                                 reg = <0>;
 1778                                 remote-endpoint = <&edp_in_vopb>;
 1779                         };
 1780 
 1781                         vopb_out_mipi: endpoint@1 {
 1782                                 reg = <1>;
 1783                                 remote-endpoint = <&mipi_in_vopb>;
 1784                         };
 1785 
 1786                         vopb_out_hdmi: endpoint@2 {
 1787                                 reg = <2>;
 1788                                 remote-endpoint = <&hdmi_in_vopb>;
 1789                         };
 1790 
 1791                         vopb_out_mipi1: endpoint@3 {
 1792                                 reg = <3>;
 1793                                 remote-endpoint = <&mipi1_in_vopb>;
 1794                         };
 1795 
 1796                         vopb_out_dp: endpoint@4 {
 1797                                 reg = <4>;
 1798                                 remote-endpoint = <&dp_in_vopb>;
 1799                         };
 1800                 };
 1801         };
 1802 
 1803         vopb_mmu: iommu@ff903f00 {
 1804                 compatible = "rockchip,iommu";
 1805                 reg = <0x0 0xff903f00 0x0 0x100>;
 1806                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
 1807                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
 1808                 clock-names = "aclk", "iface";
 1809                 power-domains = <&power RK3399_PD_VOPB>;
 1810                 #iommu-cells = <0>;
 1811                 status = "disabled";
 1812         };
 1813 
 1814         isp0: isp0@ff910000 {
 1815                 compatible = "rockchip,rk3399-cif-isp";
 1816                 reg = <0x0 0xff910000 0x0 0x4000>;
 1817                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 1818                 clocks = <&cru SCLK_ISP0>,
 1819                          <&cru ACLK_ISP0_WRAPPER>,
 1820                          <&cru HCLK_ISP0_WRAPPER>;
 1821                 clock-names = "isp", "aclk", "hclk";
 1822                 iommus = <&isp0_mmu>;
 1823                 phys = <&mipi_dphy_rx0>;
 1824                 phy-names = "dphy";
 1825                 power-domains = <&power RK3399_PD_ISP0>;
 1826                 status = "disabled";
 1827 
 1828                 ports {
 1829                         #address-cells = <1>;
 1830                         #size-cells = <0>;
 1831 
 1832                         port@0 {
 1833                                 reg = <0>;
 1834                                 #address-cells = <1>;
 1835                                 #size-cells = <0>;
 1836                         };
 1837                 };
 1838         };
 1839 
 1840         isp0_mmu: iommu@ff914000 {
 1841                 compatible = "rockchip,iommu";
 1842                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
 1843                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 1844                 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
 1845                 clock-names = "aclk", "iface";
 1846                 #iommu-cells = <0>;
 1847                 power-domains = <&power RK3399_PD_ISP0>;
 1848                 rockchip,disable-mmu-reset;
 1849         };
 1850 
 1851         isp1: isp1@ff920000 {
 1852                 compatible = "rockchip,rk3399-cif-isp";
 1853                 reg = <0x0 0xff920000 0x0 0x4000>;
 1854                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 1855                 clocks = <&cru SCLK_ISP1>,
 1856                          <&cru ACLK_ISP1_WRAPPER>,
 1857                          <&cru HCLK_ISP1_WRAPPER>;
 1858                 clock-names = "isp", "aclk", "hclk";
 1859                 iommus = <&isp1_mmu>;
 1860                 phys = <&mipi_dsi1>;
 1861                 phy-names = "dphy";
 1862                 power-domains = <&power RK3399_PD_ISP1>;
 1863                 status = "disabled";
 1864 
 1865                 ports {
 1866                         #address-cells = <1>;
 1867                         #size-cells = <0>;
 1868 
 1869                         port@0 {
 1870                                 reg = <0>;
 1871                                 #address-cells = <1>;
 1872                                 #size-cells = <0>;
 1873                         };
 1874                 };
 1875         };
 1876 
 1877         isp1_mmu: iommu@ff924000 {
 1878                 compatible = "rockchip,iommu";
 1879                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
 1880                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 1881                 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
 1882                 clock-names = "aclk", "iface";
 1883                 #iommu-cells = <0>;
 1884                 power-domains = <&power RK3399_PD_ISP1>;
 1885                 rockchip,disable-mmu-reset;
 1886         };
 1887 
 1888         hdmi_sound: hdmi-sound {
 1889                 compatible = "simple-audio-card";
 1890                 simple-audio-card,format = "i2s";
 1891                 simple-audio-card,mclk-fs = <256>;
 1892                 simple-audio-card,name = "hdmi-sound";
 1893                 status = "disabled";
 1894 
 1895                 simple-audio-card,cpu {
 1896                         sound-dai = <&i2s2>;
 1897                 };
 1898                 simple-audio-card,codec {
 1899                         sound-dai = <&hdmi>;
 1900                 };
 1901         };
 1902 
 1903         hdmi: hdmi@ff940000 {
 1904                 compatible = "rockchip,rk3399-dw-hdmi";
 1905                 reg = <0x0 0xff940000 0x0 0x20000>;
 1906                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
 1907                 clocks = <&cru PCLK_HDMI_CTRL>,
 1908                          <&cru SCLK_HDMI_SFR>,
 1909                          <&cru SCLK_HDMI_CEC>,
 1910                          <&cru PCLK_VIO_GRF>,
 1911                          <&cru PLL_VPLL>;
 1912                 clock-names = "iahb", "isfr", "cec", "grf", "ref";
 1913                 power-domains = <&power RK3399_PD_HDCP>;
 1914                 reg-io-width = <4>;
 1915                 rockchip,grf = <&grf>;
 1916                 #sound-dai-cells = <0>;
 1917                 status = "disabled";
 1918 
 1919                 ports {
 1920                         hdmi_in: port {
 1921                                 #address-cells = <1>;
 1922                                 #size-cells = <0>;
 1923 
 1924                                 hdmi_in_vopb: endpoint@0 {
 1925                                         reg = <0>;
 1926                                         remote-endpoint = <&vopb_out_hdmi>;
 1927                                 };
 1928                                 hdmi_in_vopl: endpoint@1 {
 1929                                         reg = <1>;
 1930                                         remote-endpoint = <&vopl_out_hdmi>;
 1931                                 };
 1932                         };
 1933                 };
 1934         };
 1935 
 1936         mipi_dsi: mipi@ff960000 {
 1937                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
 1938                 reg = <0x0 0xff960000 0x0 0x8000>;
 1939                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
 1940                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
 1941                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
 1942                 clock-names = "ref", "pclk", "phy_cfg", "grf";
 1943                 power-domains = <&power RK3399_PD_VIO>;
 1944                 resets = <&cru SRST_P_MIPI_DSI0>;
 1945                 reset-names = "apb";
 1946                 rockchip,grf = <&grf>;
 1947                 #address-cells = <1>;
 1948                 #size-cells = <0>;
 1949                 status = "disabled";
 1950 
 1951                 ports {
 1952                         #address-cells = <1>;
 1953                         #size-cells = <0>;
 1954 
 1955                         mipi_in: port@0 {
 1956                                 reg = <0>;
 1957                                 #address-cells = <1>;
 1958                                 #size-cells = <0>;
 1959 
 1960                                 mipi_in_vopb: endpoint@0 {
 1961                                         reg = <0>;
 1962                                         remote-endpoint = <&vopb_out_mipi>;
 1963                                 };
 1964                                 mipi_in_vopl: endpoint@1 {
 1965                                         reg = <1>;
 1966                                         remote-endpoint = <&vopl_out_mipi>;
 1967                                 };
 1968                         };
 1969                 };
 1970         };
 1971 
 1972         mipi_dsi1: mipi@ff968000 {
 1973                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
 1974                 reg = <0x0 0xff968000 0x0 0x8000>;
 1975                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
 1976                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
 1977                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
 1978                 clock-names = "ref", "pclk", "phy_cfg", "grf";
 1979                 power-domains = <&power RK3399_PD_VIO>;
 1980                 resets = <&cru SRST_P_MIPI_DSI1>;
 1981                 reset-names = "apb";
 1982                 rockchip,grf = <&grf>;
 1983                 #address-cells = <1>;
 1984                 #size-cells = <0>;
 1985                 #phy-cells = <0>;
 1986                 status = "disabled";
 1987 
 1988                 ports {
 1989                         #address-cells = <1>;
 1990                         #size-cells = <0>;
 1991 
 1992                         mipi1_in: port@0 {
 1993                                 reg = <0>;
 1994                                 #address-cells = <1>;
 1995                                 #size-cells = <0>;
 1996 
 1997                                 mipi1_in_vopb: endpoint@0 {
 1998                                         reg = <0>;
 1999                                         remote-endpoint = <&vopb_out_mipi1>;
 2000                                 };
 2001 
 2002                                 mipi1_in_vopl: endpoint@1 {
 2003                                         reg = <1>;
 2004                                         remote-endpoint = <&vopl_out_mipi1>;
 2005                                 };
 2006                         };
 2007                 };
 2008         };
 2009 
 2010         edp: edp@ff970000 {
 2011                 compatible = "rockchip,rk3399-edp";
 2012                 reg = <0x0 0xff970000 0x0 0x8000>;
 2013                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
 2014                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
 2015                 clock-names = "dp", "pclk", "grf";
 2016                 pinctrl-names = "default";
 2017                 pinctrl-0 = <&edp_hpd>;
 2018                 power-domains = <&power RK3399_PD_EDP>;
 2019                 resets = <&cru SRST_P_EDP_CTRL>;
 2020                 reset-names = "dp";
 2021                 rockchip,grf = <&grf>;
 2022                 status = "disabled";
 2023 
 2024                 ports {
 2025                         #address-cells = <1>;
 2026                         #size-cells = <0>;
 2027                         edp_in: port@0 {
 2028                                 reg = <0>;
 2029                                 #address-cells = <1>;
 2030                                 #size-cells = <0>;
 2031 
 2032                                 edp_in_vopb: endpoint@0 {
 2033                                         reg = <0>;
 2034                                         remote-endpoint = <&vopb_out_edp>;
 2035                                 };
 2036 
 2037                                 edp_in_vopl: endpoint@1 {
 2038                                         reg = <1>;
 2039                                         remote-endpoint = <&vopl_out_edp>;
 2040                                 };
 2041                         };
 2042                 };
 2043         };
 2044 
 2045         gpu: gpu@ff9a0000 {
 2046                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
 2047                 reg = <0x0 0xff9a0000 0x0 0x10000>;
 2048                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
 2049                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
 2050                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
 2051                 interrupt-names = "job", "mmu", "gpu";
 2052                 clocks = <&cru ACLK_GPU>;
 2053                 #cooling-cells = <2>;
 2054                 power-domains = <&power RK3399_PD_GPU>;
 2055                 status = "disabled";
 2056         };
 2057 
 2058         pinctrl: pinctrl {
 2059                 compatible = "rockchip,rk3399-pinctrl";
 2060                 rockchip,grf = <&grf>;
 2061                 rockchip,pmu = <&pmugrf>;
 2062                 #address-cells = <2>;
 2063                 #size-cells = <2>;
 2064                 ranges;
 2065 
 2066                 gpio0: gpio@ff720000 {
 2067                         compatible = "rockchip,gpio-bank";
 2068                         reg = <0x0 0xff720000 0x0 0x100>;
 2069                         clocks = <&pmucru PCLK_GPIO0_PMU>;
 2070                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
 2071 
 2072                         gpio-controller;
 2073                         #gpio-cells = <0x2>;
 2074 
 2075                         interrupt-controller;
 2076                         #interrupt-cells = <0x2>;
 2077                 };
 2078 
 2079                 gpio1: gpio@ff730000 {
 2080                         compatible = "rockchip,gpio-bank";
 2081                         reg = <0x0 0xff730000 0x0 0x100>;
 2082                         clocks = <&pmucru PCLK_GPIO1_PMU>;
 2083                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
 2084 
 2085                         gpio-controller;
 2086                         #gpio-cells = <0x2>;
 2087 
 2088                         interrupt-controller;
 2089                         #interrupt-cells = <0x2>;
 2090                 };
 2091 
 2092                 gpio2: gpio@ff780000 {
 2093                         compatible = "rockchip,gpio-bank";
 2094                         reg = <0x0 0xff780000 0x0 0x100>;
 2095                         clocks = <&cru PCLK_GPIO2>;
 2096                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
 2097 
 2098                         gpio-controller;
 2099                         #gpio-cells = <0x2>;
 2100 
 2101                         interrupt-controller;
 2102                         #interrupt-cells = <0x2>;
 2103                 };
 2104 
 2105                 gpio3: gpio@ff788000 {
 2106                         compatible = "rockchip,gpio-bank";
 2107                         reg = <0x0 0xff788000 0x0 0x100>;
 2108                         clocks = <&cru PCLK_GPIO3>;
 2109                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
 2110 
 2111                         gpio-controller;
 2112                         #gpio-cells = <0x2>;
 2113 
 2114                         interrupt-controller;
 2115                         #interrupt-cells = <0x2>;
 2116                 };
 2117 
 2118                 gpio4: gpio@ff790000 {
 2119                         compatible = "rockchip,gpio-bank";
 2120                         reg = <0x0 0xff790000 0x0 0x100>;
 2121                         clocks = <&cru PCLK_GPIO4>;
 2122                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
 2123 
 2124                         gpio-controller;
 2125                         #gpio-cells = <0x2>;
 2126 
 2127                         interrupt-controller;
 2128                         #interrupt-cells = <0x2>;
 2129                 };
 2130 
 2131                 pcfg_pull_up: pcfg-pull-up {
 2132                         bias-pull-up;
 2133                 };
 2134 
 2135                 pcfg_pull_down: pcfg-pull-down {
 2136                         bias-pull-down;
 2137                 };
 2138 
 2139                 pcfg_pull_none: pcfg-pull-none {
 2140                         bias-disable;
 2141                 };
 2142 
 2143                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 2144                         bias-disable;
 2145                         drive-strength = <12>;
 2146                 };
 2147 
 2148                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
 2149                         bias-disable;
 2150                         drive-strength = <13>;
 2151                 };
 2152 
 2153                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
 2154                         bias-disable;
 2155                         drive-strength = <18>;
 2156                 };
 2157 
 2158                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
 2159                         bias-disable;
 2160                         drive-strength = <20>;
 2161                 };
 2162 
 2163                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 2164                         bias-pull-up;
 2165                         drive-strength = <2>;
 2166                 };
 2167 
 2168                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 2169                         bias-pull-up;
 2170                         drive-strength = <8>;
 2171                 };
 2172 
 2173                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
 2174                         bias-pull-up;
 2175                         drive-strength = <18>;
 2176                 };
 2177 
 2178                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
 2179                         bias-pull-up;
 2180                         drive-strength = <20>;
 2181                 };
 2182 
 2183                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 2184                         bias-pull-down;
 2185                         drive-strength = <4>;
 2186                 };
 2187 
 2188                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
 2189                         bias-pull-down;
 2190                         drive-strength = <8>;
 2191                 };
 2192 
 2193                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 2194                         bias-pull-down;
 2195                         drive-strength = <12>;
 2196                 };
 2197 
 2198                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
 2199                         bias-pull-down;
 2200                         drive-strength = <18>;
 2201                 };
 2202 
 2203                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
 2204                         bias-pull-down;
 2205                         drive-strength = <20>;
 2206                 };
 2207 
 2208                 pcfg_output_high: pcfg-output-high {
 2209                         output-high;
 2210                 };
 2211 
 2212                 pcfg_output_low: pcfg-output-low {
 2213                         output-low;
 2214                 };
 2215 
 2216                 pcfg_input_enable: pcfg-input-enable {
 2217                         input-enable;
 2218                 };
 2219 
 2220                 pcfg_input_pull_up: pcfg-input-pull-up {
 2221                         input-enable;
 2222                         bias-pull-up;
 2223                         drive-strength = <2>;
 2224                 };
 2225 
 2226                 pcfg_input_pull_down: pcfg-input-pull-down {
 2227                         input-enable;
 2228                         bias-pull-down;
 2229                         drive-strength = <2>;
 2230                 };
 2231 
 2232                 clock {
 2233                         clk_32k: clk-32k {
 2234                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
 2235                         };
 2236                 };
 2237 
 2238                 cif {
 2239                         cif_clkin: cif-clkin {
 2240                                 rockchip,pins =
 2241                                         <2 RK_PB2 3 &pcfg_pull_none>;
 2242                         };
 2243 
 2244                         cif_clkouta: cif-clkouta {
 2245                                 rockchip,pins =
 2246                                         <2 RK_PB3 3 &pcfg_pull_none>;
 2247                         };
 2248                 };
 2249 
 2250                 edp {
 2251                         edp_hpd: edp-hpd {
 2252                                 rockchip,pins =
 2253                                         <4 RK_PC7 2 &pcfg_pull_none>;
 2254                         };
 2255                 };
 2256 
 2257                 gmac {
 2258                         rgmii_pins: rgmii-pins {
 2259                                 rockchip,pins =
 2260                                         /* mac_txclk */
 2261                                         <3 RK_PC1 1 &pcfg_pull_none_13ma>,
 2262                                         /* mac_rxclk */
 2263                                         <3 RK_PB6 1 &pcfg_pull_none>,
 2264                                         /* mac_mdio */
 2265                                         <3 RK_PB5 1 &pcfg_pull_none>,
 2266                                         /* mac_txen */
 2267                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
 2268                                         /* mac_clk */
 2269                                         <3 RK_PB3 1 &pcfg_pull_none>,
 2270                                         /* mac_rxdv */
 2271                                         <3 RK_PB1 1 &pcfg_pull_none>,
 2272                                         /* mac_mdc */
 2273                                         <3 RK_PB0 1 &pcfg_pull_none>,
 2274                                         /* mac_rxd1 */
 2275                                         <3 RK_PA7 1 &pcfg_pull_none>,
 2276                                         /* mac_rxd0 */
 2277                                         <3 RK_PA6 1 &pcfg_pull_none>,
 2278                                         /* mac_txd1 */
 2279                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
 2280                                         /* mac_txd0 */
 2281                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>,
 2282                                         /* mac_rxd3 */
 2283                                         <3 RK_PA3 1 &pcfg_pull_none>,
 2284                                         /* mac_rxd2 */
 2285                                         <3 RK_PA2 1 &pcfg_pull_none>,
 2286                                         /* mac_txd3 */
 2287                                         <3 RK_PA1 1 &pcfg_pull_none_13ma>,
 2288                                         /* mac_txd2 */
 2289                                         <3 RK_PA0 1 &pcfg_pull_none_13ma>;
 2290                         };
 2291 
 2292                         rmii_pins: rmii-pins {
 2293                                 rockchip,pins =
 2294                                         /* mac_mdio */
 2295                                         <3 RK_PB5 1 &pcfg_pull_none>,
 2296                                         /* mac_txen */
 2297                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
 2298                                         /* mac_clk */
 2299                                         <3 RK_PB3 1 &pcfg_pull_none>,
 2300                                         /* mac_rxer */
 2301                                         <3 RK_PB2 1 &pcfg_pull_none>,
 2302                                         /* mac_rxdv */
 2303                                         <3 RK_PB1 1 &pcfg_pull_none>,
 2304                                         /* mac_mdc */
 2305                                         <3 RK_PB0 1 &pcfg_pull_none>,
 2306                                         /* mac_rxd1 */
 2307                                         <3 RK_PA7 1 &pcfg_pull_none>,
 2308                                         /* mac_rxd0 */
 2309                                         <3 RK_PA6 1 &pcfg_pull_none>,
 2310                                         /* mac_txd1 */
 2311                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
 2312                                         /* mac_txd0 */
 2313                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>;
 2314                         };
 2315                 };
 2316 
 2317                 i2c0 {
 2318                         i2c0_xfer: i2c0-xfer {
 2319                                 rockchip,pins =
 2320                                         <1 RK_PB7 2 &pcfg_pull_none>,
 2321                                         <1 RK_PC0 2 &pcfg_pull_none>;
 2322                         };
 2323                 };
 2324 
 2325                 i2c1 {
 2326                         i2c1_xfer: i2c1-xfer {
 2327                                 rockchip,pins =
 2328                                         <4 RK_PA2 1 &pcfg_pull_none>,
 2329                                         <4 RK_PA1 1 &pcfg_pull_none>;
 2330                         };
 2331                 };
 2332 
 2333                 i2c2 {
 2334                         i2c2_xfer: i2c2-xfer {
 2335                                 rockchip,pins =
 2336                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>,
 2337                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>;
 2338                         };
 2339                 };
 2340 
 2341                 i2c3 {
 2342                         i2c3_xfer: i2c3-xfer {
 2343                                 rockchip,pins =
 2344                                         <4 RK_PC1 1 &pcfg_pull_none>,
 2345                                         <4 RK_PC0 1 &pcfg_pull_none>;
 2346                         };
 2347                 };
 2348 
 2349                 i2c4 {
 2350                         i2c4_xfer: i2c4-xfer {
 2351                                 rockchip,pins =
 2352                                         <1 RK_PB4 1 &pcfg_pull_none>,
 2353                                         <1 RK_PB3 1 &pcfg_pull_none>;
 2354                         };
 2355                 };
 2356 
 2357                 i2c5 {
 2358                         i2c5_xfer: i2c5-xfer {
 2359                                 rockchip,pins =
 2360                                         <3 RK_PB3 2 &pcfg_pull_none>,
 2361                                         <3 RK_PB2 2 &pcfg_pull_none>;
 2362                         };
 2363                 };
 2364 
 2365                 i2c6 {
 2366                         i2c6_xfer: i2c6-xfer {
 2367                                 rockchip,pins =
 2368                                         <2 RK_PB2 2 &pcfg_pull_none>,
 2369                                         <2 RK_PB1 2 &pcfg_pull_none>;
 2370                         };
 2371                 };
 2372 
 2373                 i2c7 {
 2374                         i2c7_xfer: i2c7-xfer {
 2375                                 rockchip,pins =
 2376                                         <2 RK_PB0 2 &pcfg_pull_none>,
 2377                                         <2 RK_PA7 2 &pcfg_pull_none>;
 2378                         };
 2379                 };
 2380 
 2381                 i2c8 {
 2382                         i2c8_xfer: i2c8-xfer {
 2383                                 rockchip,pins =
 2384                                         <1 RK_PC5 1 &pcfg_pull_none>,
 2385                                         <1 RK_PC4 1 &pcfg_pull_none>;
 2386                         };
 2387                 };
 2388 
 2389                 i2s0 {
 2390                         i2s0_2ch_bus: i2s0-2ch-bus {
 2391                                 rockchip,pins =
 2392                                         <3 RK_PD0 1 &pcfg_pull_none>,
 2393                                         <3 RK_PD1 1 &pcfg_pull_none>,
 2394                                         <3 RK_PD2 1 &pcfg_pull_none>,
 2395                                         <3 RK_PD3 1 &pcfg_pull_none>,
 2396                                         <3 RK_PD7 1 &pcfg_pull_none>,
 2397                                         <4 RK_PA0 1 &pcfg_pull_none>;
 2398                         };
 2399 
 2400                         i2s0_8ch_bus: i2s0-8ch-bus {
 2401                                 rockchip,pins =
 2402                                         <3 RK_PD0 1 &pcfg_pull_none>,
 2403                                         <3 RK_PD1 1 &pcfg_pull_none>,
 2404                                         <3 RK_PD2 1 &pcfg_pull_none>,
 2405                                         <3 RK_PD3 1 &pcfg_pull_none>,
 2406                                         <3 RK_PD4 1 &pcfg_pull_none>,
 2407                                         <3 RK_PD5 1 &pcfg_pull_none>,
 2408                                         <3 RK_PD6 1 &pcfg_pull_none>,
 2409                                         <3 RK_PD7 1 &pcfg_pull_none>,
 2410                                         <4 RK_PA0 1 &pcfg_pull_none>;
 2411                         };
 2412                 };
 2413 
 2414                 i2s1 {
 2415                         i2s1_2ch_bus: i2s1-2ch-bus {
 2416                                 rockchip,pins =
 2417                                         <4 RK_PA3 1 &pcfg_pull_none>,
 2418                                         <4 RK_PA4 1 &pcfg_pull_none>,
 2419                                         <4 RK_PA5 1 &pcfg_pull_none>,
 2420                                         <4 RK_PA6 1 &pcfg_pull_none>,
 2421                                         <4 RK_PA7 1 &pcfg_pull_none>;
 2422                         };
 2423                 };
 2424 
 2425                 sdio0 {
 2426                         sdio0_bus1: sdio0-bus1 {
 2427                                 rockchip,pins =
 2428                                         <2 RK_PC4 1 &pcfg_pull_up>;
 2429                         };
 2430 
 2431                         sdio0_bus4: sdio0-bus4 {
 2432                                 rockchip,pins =
 2433                                         <2 RK_PC4 1 &pcfg_pull_up>,
 2434                                         <2 RK_PC5 1 &pcfg_pull_up>,
 2435                                         <2 RK_PC6 1 &pcfg_pull_up>,
 2436                                         <2 RK_PC7 1 &pcfg_pull_up>;
 2437                         };
 2438 
 2439                         sdio0_cmd: sdio0-cmd {
 2440                                 rockchip,pins =
 2441                                         <2 RK_PD0 1 &pcfg_pull_up>;
 2442                         };
 2443 
 2444                         sdio0_clk: sdio0-clk {
 2445                                 rockchip,pins =
 2446                                         <2 RK_PD1 1 &pcfg_pull_none>;
 2447                         };
 2448 
 2449                         sdio0_cd: sdio0-cd {
 2450                                 rockchip,pins =
 2451                                         <2 RK_PD2 1 &pcfg_pull_up>;
 2452                         };
 2453 
 2454                         sdio0_pwr: sdio0-pwr {
 2455                                 rockchip,pins =
 2456                                         <2 RK_PD3 1 &pcfg_pull_up>;
 2457                         };
 2458 
 2459                         sdio0_bkpwr: sdio0-bkpwr {
 2460                                 rockchip,pins =
 2461                                         <2 RK_PD4 1 &pcfg_pull_up>;
 2462                         };
 2463 
 2464                         sdio0_wp: sdio0-wp {
 2465                                 rockchip,pins =
 2466                                         <0 RK_PA3 1 &pcfg_pull_up>;
 2467                         };
 2468 
 2469                         sdio0_int: sdio0-int {
 2470                                 rockchip,pins =
 2471                                         <0 RK_PA4 1 &pcfg_pull_up>;
 2472                         };
 2473                 };
 2474 
 2475                 sdmmc {
 2476                         sdmmc_bus1: sdmmc-bus1 {
 2477                                 rockchip,pins =
 2478                                         <4 RK_PB0 1 &pcfg_pull_up>;
 2479                         };
 2480 
 2481                         sdmmc_bus4: sdmmc-bus4 {
 2482                                 rockchip,pins =
 2483                                         <4 RK_PB0 1 &pcfg_pull_up>,
 2484                                         <4 RK_PB1 1 &pcfg_pull_up>,
 2485                                         <4 RK_PB2 1 &pcfg_pull_up>,
 2486                                         <4 RK_PB3 1 &pcfg_pull_up>;
 2487                         };
 2488 
 2489                         sdmmc_clk: sdmmc-clk {
 2490                                 rockchip,pins =
 2491                                         <4 RK_PB4 1 &pcfg_pull_none>;
 2492                         };
 2493 
 2494                         sdmmc_cmd: sdmmc-cmd {
 2495                                 rockchip,pins =
 2496                                         <4 RK_PB5 1 &pcfg_pull_up>;
 2497                         };
 2498 
 2499                         sdmmc_cd: sdmmc-cd {
 2500                                 rockchip,pins =
 2501                                         <0 RK_PA7 1 &pcfg_pull_up>;
 2502                         };
 2503 
 2504                         sdmmc_wp: sdmmc-wp {
 2505                                 rockchip,pins =
 2506                                         <0 RK_PB0 1 &pcfg_pull_up>;
 2507                         };
 2508                 };
 2509 
 2510                 suspend {
 2511                         ap_pwroff: ap-pwroff {
 2512                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
 2513                         };
 2514 
 2515                         ddrio_pwroff: ddrio-pwroff {
 2516                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
 2517                         };
 2518                 };
 2519 
 2520                 spdif {
 2521                         spdif_bus: spdif-bus {
 2522                                 rockchip,pins =
 2523                                         <4 RK_PC5 1 &pcfg_pull_none>;
 2524                         };
 2525 
 2526                         spdif_bus_1: spdif-bus-1 {
 2527                                 rockchip,pins =
 2528                                         <3 RK_PC0 3 &pcfg_pull_none>;
 2529                         };
 2530                 };
 2531 
 2532                 spi0 {
 2533                         spi0_clk: spi0-clk {
 2534                                 rockchip,pins =
 2535                                         <3 RK_PA6 2 &pcfg_pull_up>;
 2536                         };
 2537                         spi0_cs0: spi0-cs0 {
 2538                                 rockchip,pins =
 2539                                         <3 RK_PA7 2 &pcfg_pull_up>;
 2540                         };
 2541                         spi0_cs1: spi0-cs1 {
 2542                                 rockchip,pins =
 2543                                         <3 RK_PB0 2 &pcfg_pull_up>;
 2544                         };
 2545                         spi0_tx: spi0-tx {
 2546                                 rockchip,pins =
 2547                                         <3 RK_PA5 2 &pcfg_pull_up>;
 2548                         };
 2549                         spi0_rx: spi0-rx {
 2550                                 rockchip,pins =
 2551                                         <3 RK_PA4 2 &pcfg_pull_up>;
 2552                         };
 2553                 };
 2554 
 2555                 spi1 {
 2556                         spi1_clk: spi1-clk {
 2557                                 rockchip,pins =
 2558                                         <1 RK_PB1 2 &pcfg_pull_up>;
 2559                         };
 2560                         spi1_cs0: spi1-cs0 {
 2561                                 rockchip,pins =
 2562                                         <1 RK_PB2 2 &pcfg_pull_up>;
 2563                         };
 2564                         spi1_rx: spi1-rx {
 2565                                 rockchip,pins =
 2566                                         <1 RK_PA7 2 &pcfg_pull_up>;
 2567                         };
 2568                         spi1_tx: spi1-tx {
 2569                                 rockchip,pins =
 2570                                         <1 RK_PB0 2 &pcfg_pull_up>;
 2571                         };
 2572                 };
 2573 
 2574                 spi2 {
 2575                         spi2_clk: spi2-clk {
 2576                                 rockchip,pins =
 2577                                         <2 RK_PB3 1 &pcfg_pull_up>;
 2578                         };
 2579                         spi2_cs0: spi2-cs0 {
 2580                                 rockchip,pins =
 2581                                         <2 RK_PB4 1 &pcfg_pull_up>;
 2582                         };
 2583                         spi2_rx: spi2-rx {
 2584                                 rockchip,pins =
 2585                                         <2 RK_PB1 1 &pcfg_pull_up>;
 2586                         };
 2587                         spi2_tx: spi2-tx {
 2588                                 rockchip,pins =
 2589                                         <2 RK_PB2 1 &pcfg_pull_up>;
 2590                         };
 2591                 };
 2592 
 2593                 spi3 {
 2594                         spi3_clk: spi3-clk {
 2595                                 rockchip,pins =
 2596                                         <1 RK_PC1 1 &pcfg_pull_up>;
 2597                         };
 2598                         spi3_cs0: spi3-cs0 {
 2599                                 rockchip,pins =
 2600                                         <1 RK_PC2 1 &pcfg_pull_up>;
 2601                         };
 2602                         spi3_rx: spi3-rx {
 2603                                 rockchip,pins =
 2604                                         <1 RK_PB7 1 &pcfg_pull_up>;
 2605                         };
 2606                         spi3_tx: spi3-tx {
 2607                                 rockchip,pins =
 2608                                         <1 RK_PC0 1 &pcfg_pull_up>;
 2609                         };
 2610                 };
 2611 
 2612                 spi4 {
 2613                         spi4_clk: spi4-clk {
 2614                                 rockchip,pins =
 2615                                         <3 RK_PA2 2 &pcfg_pull_up>;
 2616                         };
 2617                         spi4_cs0: spi4-cs0 {
 2618                                 rockchip,pins =
 2619                                         <3 RK_PA3 2 &pcfg_pull_up>;
 2620                         };
 2621                         spi4_rx: spi4-rx {
 2622                                 rockchip,pins =
 2623                                         <3 RK_PA0 2 &pcfg_pull_up>;
 2624                         };
 2625                         spi4_tx: spi4-tx {
 2626                                 rockchip,pins =
 2627                                         <3 RK_PA1 2 &pcfg_pull_up>;
 2628                         };
 2629                 };
 2630 
 2631                 spi5 {
 2632                         spi5_clk: spi5-clk {
 2633                                 rockchip,pins =
 2634                                         <2 RK_PC6 2 &pcfg_pull_up>;
 2635                         };
 2636                         spi5_cs0: spi5-cs0 {
 2637                                 rockchip,pins =
 2638                                         <2 RK_PC7 2 &pcfg_pull_up>;
 2639                         };
 2640                         spi5_rx: spi5-rx {
 2641                                 rockchip,pins =
 2642                                         <2 RK_PC4 2 &pcfg_pull_up>;
 2643                         };
 2644                         spi5_tx: spi5-tx {
 2645                                 rockchip,pins =
 2646                                         <2 RK_PC5 2 &pcfg_pull_up>;
 2647                         };
 2648                 };
 2649 
 2650                 testclk {
 2651                         test_clkout0: test-clkout0 {
 2652                                 rockchip,pins =
 2653                                         <0 RK_PA0 1 &pcfg_pull_none>;
 2654                         };
 2655 
 2656                         test_clkout1: test-clkout1 {
 2657                                 rockchip,pins =
 2658                                         <2 RK_PD1 2 &pcfg_pull_none>;
 2659                         };
 2660 
 2661                         test_clkout2: test-clkout2 {
 2662                                 rockchip,pins =
 2663                                         <0 RK_PB0 3 &pcfg_pull_none>;
 2664                         };
 2665                 };
 2666 
 2667                 tsadc {
 2668                         otp_pin: otp-pin {
 2669                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 2670                         };
 2671 
 2672                         otp_out: otp-out {
 2673                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
 2674                         };
 2675                 };
 2676 
 2677                 uart0 {
 2678                         uart0_xfer: uart0-xfer {
 2679                                 rockchip,pins =
 2680                                         <2 RK_PC0 1 &pcfg_pull_up>,
 2681                                         <2 RK_PC1 1 &pcfg_pull_none>;
 2682                         };
 2683 
 2684                         uart0_cts: uart0-cts {
 2685                                 rockchip,pins =
 2686                                         <2 RK_PC2 1 &pcfg_pull_none>;
 2687                         };
 2688 
 2689                         uart0_rts: uart0-rts {
 2690                                 rockchip,pins =
 2691                                         <2 RK_PC3 1 &pcfg_pull_none>;
 2692                         };
 2693                 };
 2694 
 2695                 uart1 {
 2696                         uart1_xfer: uart1-xfer {
 2697                                 rockchip,pins =
 2698                                         <3 RK_PB4 2 &pcfg_pull_up>,
 2699                                         <3 RK_PB5 2 &pcfg_pull_none>;
 2700                         };
 2701                 };
 2702 
 2703                 uart2a {
 2704                         uart2a_xfer: uart2a-xfer {
 2705                                 rockchip,pins =
 2706                                         <4 RK_PB0 2 &pcfg_pull_up>,
 2707                                         <4 RK_PB1 2 &pcfg_pull_none>;
 2708                         };
 2709                 };
 2710 
 2711                 uart2b {
 2712                         uart2b_xfer: uart2b-xfer {
 2713                                 rockchip,pins =
 2714                                         <4 RK_PC0 2 &pcfg_pull_up>,
 2715                                         <4 RK_PC1 2 &pcfg_pull_none>;
 2716                         };
 2717                 };
 2718 
 2719                 uart2c {
 2720                         uart2c_xfer: uart2c-xfer {
 2721                                 rockchip,pins =
 2722                                         <4 RK_PC3 1 &pcfg_pull_up>,
 2723                                         <4 RK_PC4 1 &pcfg_pull_none>;
 2724                         };
 2725                 };
 2726 
 2727                 uart3 {
 2728                         uart3_xfer: uart3-xfer {
 2729                                 rockchip,pins =
 2730                                         <3 RK_PB6 2 &pcfg_pull_up>,
 2731                                         <3 RK_PB7 2 &pcfg_pull_none>;
 2732                         };
 2733 
 2734                         uart3_cts: uart3-cts {
 2735                                 rockchip,pins =
 2736                                         <3 RK_PC0 2 &pcfg_pull_none>;
 2737                         };
 2738 
 2739                         uart3_rts: uart3-rts {
 2740                                 rockchip,pins =
 2741                                         <3 RK_PC1 2 &pcfg_pull_none>;
 2742                         };
 2743                 };
 2744 
 2745                 uart4 {
 2746                         uart4_xfer: uart4-xfer {
 2747                                 rockchip,pins =
 2748                                         <1 RK_PA7 1 &pcfg_pull_up>,
 2749                                         <1 RK_PB0 1 &pcfg_pull_none>;
 2750                         };
 2751                 };
 2752 
 2753                 uarthdcp {
 2754                         uarthdcp_xfer: uarthdcp-xfer {
 2755                                 rockchip,pins =
 2756                                         <4 RK_PC5 2 &pcfg_pull_up>,
 2757                                         <4 RK_PC6 2 &pcfg_pull_none>;
 2758                         };
 2759                 };
 2760 
 2761                 pwm0 {
 2762                         pwm0_pin: pwm0-pin {
 2763                                 rockchip,pins =
 2764                                         <4 RK_PC2 1 &pcfg_pull_none>;
 2765                         };
 2766 
 2767                         pwm0_pin_pull_down: pwm0-pin-pull-down {
 2768                                 rockchip,pins =
 2769                                         <4 RK_PC2 1 &pcfg_pull_down>;
 2770                         };
 2771 
 2772                         vop0_pwm_pin: vop0-pwm-pin {
 2773                                 rockchip,pins =
 2774                                         <4 RK_PC2 2 &pcfg_pull_none>;
 2775                         };
 2776 
 2777                         vop1_pwm_pin: vop1-pwm-pin {
 2778                                 rockchip,pins =
 2779                                         <4 RK_PC2 3 &pcfg_pull_none>;
 2780                         };
 2781                 };
 2782 
 2783                 pwm1 {
 2784                         pwm1_pin: pwm1-pin {
 2785                                 rockchip,pins =
 2786                                         <4 RK_PC6 1 &pcfg_pull_none>;
 2787                         };
 2788 
 2789                         pwm1_pin_pull_down: pwm1-pin-pull-down {
 2790                                 rockchip,pins =
 2791                                         <4 RK_PC6 1 &pcfg_pull_down>;
 2792                         };
 2793                 };
 2794 
 2795                 pwm2 {
 2796                         pwm2_pin: pwm2-pin {
 2797                                 rockchip,pins =
 2798                                         <1 RK_PC3 1 &pcfg_pull_none>;
 2799                         };
 2800 
 2801                         pwm2_pin_pull_down: pwm2-pin-pull-down {
 2802                                 rockchip,pins =
 2803                                         <1 RK_PC3 1 &pcfg_pull_down>;
 2804                         };
 2805                 };
 2806 
 2807                 pwm3a {
 2808                         pwm3a_pin: pwm3a-pin {
 2809                                 rockchip,pins =
 2810                                         <0 RK_PA6 1 &pcfg_pull_none>;
 2811                         };
 2812                 };
 2813 
 2814                 pwm3b {
 2815                         pwm3b_pin: pwm3b-pin {
 2816                                 rockchip,pins =
 2817                                         <1 RK_PB6 1 &pcfg_pull_none>;
 2818                         };
 2819                 };
 2820 
 2821                 hdmi {
 2822                         hdmi_i2c_xfer: hdmi-i2c-xfer {
 2823                                 rockchip,pins =
 2824                                         <4 RK_PC1 3 &pcfg_pull_none>,
 2825                                         <4 RK_PC0 3 &pcfg_pull_none>;
 2826                         };
 2827 
 2828                         hdmi_cec: hdmi-cec {
 2829                                 rockchip,pins =
 2830                                         <4 RK_PC7 1 &pcfg_pull_none>;
 2831                         };
 2832                 };
 2833 
 2834                 pcie {
 2835                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
 2836                                 rockchip,pins =
 2837                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
 2838                         };
 2839 
 2840                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
 2841                                 rockchip,pins =
 2842                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 2843                         };
 2844                 };
 2845 
 2846         };
 2847 };
Cache object: 88c5af2730c7e85561e422eb7dd07b72
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/rockchip/rk3399.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/rockchip/rk3399.dtsi
