rk3568.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
    4  */
    5 
    6 #include "rk356x.dtsi"
    7 
    8 / {
    9         compatible = "rockchip,rk3568";
   10 
   11         sata0: sata@fc000000 {
   12                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
   13                 reg = <0 0xfc000000 0 0x1000>;
   14                 clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
   15                          <&cru CLK_SATA0_RXOOB>;
   16                 clock-names = "sata", "pmalive", "rxoob";
   17                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
   18                 phys = <&combphy0 PHY_TYPE_SATA>;
   19                 phy-names = "sata-phy";
   20                 ports-implemented = <0x1>;
   21                 power-domains = <&power RK3568_PD_PIPE>;
   22                 status = "disabled";
   23         };
   24 
   25         pipe_phy_grf0: syscon@fdc70000 {
   26                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
   27                 reg = <0x0 0xfdc70000 0x0 0x1000>;
   28         };
   29 
   30         qos_pcie3x1: qos@fe190080 {
   31                 compatible = "rockchip,rk3568-qos", "syscon";
   32                 reg = <0x0 0xfe190080 0x0 0x20>;
   33         };
   34 
   35         qos_pcie3x2: qos@fe190100 {
   36                 compatible = "rockchip,rk3568-qos", "syscon";
   37                 reg = <0x0 0xfe190100 0x0 0x20>;
   38         };
   39 
   40         qos_sata0: qos@fe190200 {
   41                 compatible = "rockchip,rk3568-qos", "syscon";
   42                 reg = <0x0 0xfe190200 0x0 0x20>;
   43         };
   44 
   45         gmac0: ethernet@fe2a0000 {
   46                 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
   47                 reg = <0x0 0xfe2a0000 0x0 0x10000>;
   48                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
   49                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
   50                 interrupt-names = "macirq", "eth_wake_irq";
   51                 clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
   52                          <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
   53                          <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
   54                          <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
   55                 clock-names = "stmmaceth", "mac_clk_rx",
   56                               "mac_clk_tx", "clk_mac_refout",
   57                               "aclk_mac", "pclk_mac",
   58                               "clk_mac_speed", "ptp_ref";
   59                 resets = <&cru SRST_A_GMAC0>;
   60                 reset-names = "stmmaceth";
   61                 rockchip,grf = <&grf>;
   62                 snps,axi-config = <&gmac0_stmmac_axi_setup>;
   63                 snps,mixed-burst;
   64                 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
   65                 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
   66                 snps,tso;
   67                 status = "disabled";
   68 
   69                 mdio0: mdio {
   70                         compatible = "snps,dwmac-mdio";
   71                         #address-cells = <0x1>;
   72                         #size-cells = <0x0>;
   73                 };
   74 
   75                 gmac0_stmmac_axi_setup: stmmac-axi-config {
   76                         snps,blen = <0 0 0 0 16 8 4>;
   77                         snps,rd_osr_lmt = <8>;
   78                         snps,wr_osr_lmt = <4>;
   79                 };
   80 
   81                 gmac0_mtl_rx_setup: rx-queues-config {
   82                         snps,rx-queues-to-use = <1>;
   83                         queue0 {};
   84                 };
   85 
   86                 gmac0_mtl_tx_setup: tx-queues-config {
   87                         snps,tx-queues-to-use = <1>;
   88                         queue0 {};
   89                 };
   90         };
   91 
   92         combphy0: phy@fe820000 {
   93                 compatible = "rockchip,rk3568-naneng-combphy";
   94                 reg = <0x0 0xfe820000 0x0 0x100>;
   95                 clocks = <&pmucru CLK_PCIEPHY0_REF>,
   96                          <&cru PCLK_PIPEPHY0>,
   97                          <&cru PCLK_PIPE>;
   98                 clock-names = "ref", "apb", "pipe";
   99                 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
  100                 assigned-clock-rates = <100000000>;
  101                 resets = <&cru SRST_PIPEPHY0>;
  102                 rockchip,pipe-grf = <&pipegrf>;
  103                 rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
  104                 #phy-cells = <1>;
  105                 status = "disabled";
  106         };
  107 };
  108 
  109 &cpu0_opp_table {
  110         opp-1992000000 {
  111                 opp-hz = /bits/ 64 <1992000000>;
  112                 opp-microvolt = <1150000 1150000 1150000>;
  113         };
  114 };
  115 
  116 &pipegrf {
  117         compatible = "rockchip,rk3568-pipe-grf", "syscon";
  118 };
  119 
  120 &power {
  121         power-domain@RK3568_PD_PIPE {
  122                 reg = <RK3568_PD_PIPE>;
  123                 clocks = <&cru PCLK_PIPE>;
  124                 pm_qos = <&qos_pcie2x1>,
  125                          <&qos_pcie3x1>,
  126                          <&qos_pcie3x2>,
  127                          <&qos_sata0>,
  128                          <&qos_sata1>,
  129                          <&qos_sata2>,
  130                          <&qos_usb3_0>,
  131                          <&qos_usb3_1>;
  132                 #power-domain-cells = <0>;
  133         };
  134 };
  135 
  136 &usb_host0_xhci {
  137         phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
  138         phy-names = "usb2-phy", "usb3-phy";
  139 };
  140 
  141 &vop {
  142         compatible = "rockchip,rk3568-vop";
  143 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi

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sys/contrib/device-tree/src/arm64/rockchip/rk3568.dtsi