rk356x.dtsi

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    1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
    2 /*
    3  * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
    4  */
    5 
    6 #include <dt-bindings/clock/rk3568-cru.h>
    7 #include <dt-bindings/interrupt-controller/arm-gic.h>
    8 #include <dt-bindings/interrupt-controller/irq.h>
    9 #include <dt-bindings/phy/phy.h>
   10 #include <dt-bindings/pinctrl/rockchip.h>
   11 #include <dt-bindings/power/rk3568-power.h>
   12 #include <dt-bindings/soc/rockchip,boot-mode.h>
   13 #include <dt-bindings/thermal/thermal.h>
   14 
   15 / {
   16         interrupt-parent = <&gic>;
   17         #address-cells = <2>;
   18         #size-cells = <2>;
   19 
   20         aliases {
   21                 gpio0 = &gpio0;
   22                 gpio1 = &gpio1;
   23                 gpio2 = &gpio2;
   24                 gpio3 = &gpio3;
   25                 gpio4 = &gpio4;
   26                 i2c0 = &i2c0;
   27                 i2c1 = &i2c1;
   28                 i2c2 = &i2c2;
   29                 i2c3 = &i2c3;
   30                 i2c4 = &i2c4;
   31                 i2c5 = &i2c5;
   32                 serial0 = &uart0;
   33                 serial1 = &uart1;
   34                 serial2 = &uart2;
   35                 serial3 = &uart3;
   36                 serial4 = &uart4;
   37                 serial5 = &uart5;
   38                 serial6 = &uart6;
   39                 serial7 = &uart7;
   40                 serial8 = &uart8;
   41                 serial9 = &uart9;
   42                 spi0 = &spi0;
   43                 spi1 = &spi1;
   44                 spi2 = &spi2;
   45                 spi3 = &spi3;
   46         };
   47 
   48         cpus {
   49                 #address-cells = <2>;
   50                 #size-cells = <0>;
   51 
   52                 cpu0: cpu@0 {
   53                         device_type = "cpu";
   54                         compatible = "arm,cortex-a55";
   55                         reg = <0x0 0x0>;
   56                         clocks = <&scmi_clk 0>;
   57                         #cooling-cells = <2>;
   58                         enable-method = "psci";
   59                         operating-points-v2 = <&cpu0_opp_table>;
   60                 };
   61 
   62                 cpu1: cpu@100 {
   63                         device_type = "cpu";
   64                         compatible = "arm,cortex-a55";
   65                         reg = <0x0 0x100>;
   66                         #cooling-cells = <2>;
   67                         enable-method = "psci";
   68                         operating-points-v2 = <&cpu0_opp_table>;
   69                 };
   70 
   71                 cpu2: cpu@200 {
   72                         device_type = "cpu";
   73                         compatible = "arm,cortex-a55";
   74                         reg = <0x0 0x200>;
   75                         #cooling-cells = <2>;
   76                         enable-method = "psci";
   77                         operating-points-v2 = <&cpu0_opp_table>;
   78                 };
   79 
   80                 cpu3: cpu@300 {
   81                         device_type = "cpu";
   82                         compatible = "arm,cortex-a55";
   83                         reg = <0x0 0x300>;
   84                         #cooling-cells = <2>;
   85                         enable-method = "psci";
   86                         operating-points-v2 = <&cpu0_opp_table>;
   87                 };
   88         };
   89 
   90         cpu0_opp_table: opp-table-0 {
   91                 compatible = "operating-points-v2";
   92                 opp-shared;
   93 
   94                 opp-408000000 {
   95                         opp-hz = /bits/ 64 <408000000>;
   96                         opp-microvolt = <900000 900000 1150000>;
   97                         clock-latency-ns = <40000>;
   98                 };
   99 
  100                 opp-600000000 {
  101                         opp-hz = /bits/ 64 <600000000>;
  102                         opp-microvolt = <900000 900000 1150000>;
  103                 };
  104 
  105                 opp-816000000 {
  106                         opp-hz = /bits/ 64 <816000000>;
  107                         opp-microvolt = <900000 900000 1150000>;
  108                         opp-suspend;
  109                 };
  110 
  111                 opp-1104000000 {
  112                         opp-hz = /bits/ 64 <1104000000>;
  113                         opp-microvolt = <900000 900000 1150000>;
  114                 };
  115 
  116                 opp-1416000000 {
  117                         opp-hz = /bits/ 64 <1416000000>;
  118                         opp-microvolt = <900000 900000 1150000>;
  119                 };
  120 
  121                 opp-1608000000 {
  122                         opp-hz = /bits/ 64 <1608000000>;
  123                         opp-microvolt = <975000 975000 1150000>;
  124                 };
  125 
  126                 opp-1800000000 {
  127                         opp-hz = /bits/ 64 <1800000000>;
  128                         opp-microvolt = <1050000 1050000 1150000>;
  129                 };
  130         };
  131 
  132         display_subsystem: display-subsystem {
  133                 compatible = "rockchip,display-subsystem";
  134                 ports = <&vop_out>;
  135         };
  136 
  137         firmware {
  138                 scmi: scmi {
  139                         compatible = "arm,scmi-smc";
  140                         arm,smc-id = <0x82000010>;
  141                         shmem = <&scmi_shmem>;
  142                         #address-cells = <1>;
  143                         #size-cells = <0>;
  144 
  145                         scmi_clk: protocol@14 {
  146                                 reg = <0x14>;
  147                                 #clock-cells = <1>;
  148                         };
  149                 };
  150         };
  151 
  152         gpu_opp_table: opp-table-1 {
  153                 compatible = "operating-points-v2";
  154 
  155                 opp-200000000 {
  156                         opp-hz = /bits/ 64 <200000000>;
  157                         opp-microvolt = <825000>;
  158                 };
  159 
  160                 opp-300000000 {
  161                         opp-hz = /bits/ 64 <300000000>;
  162                         opp-microvolt = <825000>;
  163                 };
  164 
  165                 opp-400000000 {
  166                         opp-hz = /bits/ 64 <400000000>;
  167                         opp-microvolt = <825000>;
  168                 };
  169 
  170                 opp-600000000 {
  171                         opp-hz = /bits/ 64 <600000000>;
  172                         opp-microvolt = <825000>;
  173                 };
  174 
  175                 opp-700000000 {
  176                         opp-hz = /bits/ 64 <700000000>;
  177                         opp-microvolt = <900000>;
  178                 };
  179 
  180                 opp-800000000 {
  181                         opp-hz = /bits/ 64 <800000000>;
  182                         opp-microvolt = <1000000>;
  183                 };
  184         };
  185 
  186         hdmi_sound: hdmi-sound {
  187                 compatible = "simple-audio-card";
  188                 simple-audio-card,name = "HDMI";
  189                 simple-audio-card,format = "i2s";
  190                 simple-audio-card,mclk-fs = <256>;
  191                 status = "disabled";
  192 
  193                 simple-audio-card,codec {
  194                         sound-dai = <&hdmi>;
  195                 };
  196 
  197                 simple-audio-card,cpu {
  198                         sound-dai = <&i2s0_8ch>;
  199                 };
  200         };
  201 
  202         pmu {
  203                 compatible = "arm,cortex-a55-pmu";
  204                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
  205                              <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
  206                              <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
  207                              <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
  208                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  209         };
  210 
  211         psci {
  212                 compatible = "arm,psci-1.0";
  213                 method = "smc";
  214         };
  215 
  216         timer {
  217                 compatible = "arm,armv8-timer";
  218                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
  219                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
  220                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
  221                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
  222                 arm,no-tick-in-suspend;
  223         };
  224 
  225         xin24m: xin24m {
  226                 compatible = "fixed-clock";
  227                 clock-frequency = <24000000>;
  228                 clock-output-names = "xin24m";
  229                 #clock-cells = <0>;
  230         };
  231 
  232         xin32k: xin32k {
  233                 compatible = "fixed-clock";
  234                 clock-frequency = <32768>;
  235                 clock-output-names = "xin32k";
  236                 pinctrl-0 = <&clk32k_out0>;
  237                 pinctrl-names = "default";
  238                 #clock-cells = <0>;
  239         };
  240 
  241         sram@10f000 {
  242                 compatible = "mmio-sram";
  243                 reg = <0x0 0x0010f000 0x0 0x100>;
  244                 #address-cells = <1>;
  245                 #size-cells = <1>;
  246                 ranges = <0 0x0 0x0010f000 0x100>;
  247 
  248                 scmi_shmem: sram@0 {
  249                         compatible = "arm,scmi-shmem";
  250                         reg = <0x0 0x100>;
  251                 };
  252         };
  253 
  254         sata1: sata@fc400000 {
  255                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
  256                 reg = <0 0xfc400000 0 0x1000>;
  257                 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
  258                          <&cru CLK_SATA1_RXOOB>;
  259                 clock-names = "sata", "pmalive", "rxoob";
  260                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
  261                 phys = <&combphy1 PHY_TYPE_SATA>;
  262                 phy-names = "sata-phy";
  263                 ports-implemented = <0x1>;
  264                 power-domains = <&power RK3568_PD_PIPE>;
  265                 status = "disabled";
  266         };
  267 
  268         sata2: sata@fc800000 {
  269                 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
  270                 reg = <0 0xfc800000 0 0x1000>;
  271                 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
  272                          <&cru CLK_SATA2_RXOOB>;
  273                 clock-names = "sata", "pmalive", "rxoob";
  274                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  275                 phys = <&combphy2 PHY_TYPE_SATA>;
  276                 phy-names = "sata-phy";
  277                 ports-implemented = <0x1>;
  278                 power-domains = <&power RK3568_PD_PIPE>;
  279                 status = "disabled";
  280         };
  281 
  282         usb_host0_xhci: usb@fcc00000 {
  283                 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
  284                 reg = <0x0 0xfcc00000 0x0 0x400000>;
  285                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
  286                 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
  287                          <&cru ACLK_USB3OTG0>;
  288                 clock-names = "ref_clk", "suspend_clk",
  289                               "bus_clk";
  290                 dr_mode = "otg";
  291                 phy_type = "utmi_wide";
  292                 power-domains = <&power RK3568_PD_PIPE>;
  293                 resets = <&cru SRST_USB3OTG0>;
  294                 snps,dis_u2_susphy_quirk;
  295                 status = "disabled";
  296         };
  297 
  298         usb_host1_xhci: usb@fd000000 {
  299                 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
  300                 reg = <0x0 0xfd000000 0x0 0x400000>;
  301                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
  302                 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
  303                          <&cru ACLK_USB3OTG1>;
  304                 clock-names = "ref_clk", "suspend_clk",
  305                               "bus_clk";
  306                 dr_mode = "host";
  307                 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
  308                 phy-names = "usb2-phy", "usb3-phy";
  309                 phy_type = "utmi_wide";
  310                 power-domains = <&power RK3568_PD_PIPE>;
  311                 resets = <&cru SRST_USB3OTG1>;
  312                 snps,dis_u2_susphy_quirk;
  313                 status = "disabled";
  314         };
  315 
  316         gic: interrupt-controller@fd400000 {
  317                 compatible = "arm,gic-v3";
  318                 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
  319                       <0x0 0xfd460000 0 0x80000>; /* GICR */
  320                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
  321                 interrupt-controller;
  322                 #interrupt-cells = <3>;
  323                 mbi-alias = <0x0 0xfd410000>;
  324                 mbi-ranges = <296 24>;
  325                 msi-controller;
  326         };
  327 
  328         usb_host0_ehci: usb@fd800000 {
  329                 compatible = "generic-ehci";
  330                 reg = <0x0 0xfd800000 0x0 0x40000>;
  331                 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
  332                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
  333                          <&cru PCLK_USB>;
  334                 phys = <&usb2phy1_otg>;
  335                 phy-names = "usb";
  336                 status = "disabled";
  337         };
  338 
  339         usb_host0_ohci: usb@fd840000 {
  340                 compatible = "generic-ohci";
  341                 reg = <0x0 0xfd840000 0x0 0x40000>;
  342                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
  343                 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
  344                          <&cru PCLK_USB>;
  345                 phys = <&usb2phy1_otg>;
  346                 phy-names = "usb";
  347                 status = "disabled";
  348         };
  349 
  350         usb_host1_ehci: usb@fd880000 {
  351                 compatible = "generic-ehci";
  352                 reg = <0x0 0xfd880000 0x0 0x40000>;
  353                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  354                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
  355                          <&cru PCLK_USB>;
  356                 phys = <&usb2phy1_host>;
  357                 phy-names = "usb";
  358                 status = "disabled";
  359         };
  360 
  361         usb_host1_ohci: usb@fd8c0000 {
  362                 compatible = "generic-ohci";
  363                 reg = <0x0 0xfd8c0000 0x0 0x40000>;
  364                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
  365                 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
  366                          <&cru PCLK_USB>;
  367                 phys = <&usb2phy1_host>;
  368                 phy-names = "usb";
  369                 status = "disabled";
  370         };
  371 
  372         pmugrf: syscon@fdc20000 {
  373                 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
  374                 reg = <0x0 0xfdc20000 0x0 0x10000>;
  375 
  376                 pmu_io_domains: io-domains {
  377                         compatible = "rockchip,rk3568-pmu-io-voltage-domain";
  378                         status = "disabled";
  379                 };
  380         };
  381 
  382         pipegrf: syscon@fdc50000 {
  383                 reg = <0x0 0xfdc50000 0x0 0x1000>;
  384         };
  385 
  386         grf: syscon@fdc60000 {
  387                 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
  388                 reg = <0x0 0xfdc60000 0x0 0x10000>;
  389         };
  390 
  391         pipe_phy_grf1: syscon@fdc80000 {
  392                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
  393                 reg = <0x0 0xfdc80000 0x0 0x1000>;
  394         };
  395 
  396         pipe_phy_grf2: syscon@fdc90000 {
  397                 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
  398                 reg = <0x0 0xfdc90000 0x0 0x1000>;
  399         };
  400 
  401         usb2phy0_grf: syscon@fdca0000 {
  402                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
  403                 reg = <0x0 0xfdca0000 0x0 0x8000>;
  404         };
  405 
  406         usb2phy1_grf: syscon@fdca8000 {
  407                 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
  408                 reg = <0x0 0xfdca8000 0x0 0x8000>;
  409         };
  410 
  411         pmucru: clock-controller@fdd00000 {
  412                 compatible = "rockchip,rk3568-pmucru";
  413                 reg = <0x0 0xfdd00000 0x0 0x1000>;
  414                 #clock-cells = <1>;
  415                 #reset-cells = <1>;
  416         };
  417 
  418         cru: clock-controller@fdd20000 {
  419                 compatible = "rockchip,rk3568-cru";
  420                 reg = <0x0 0xfdd20000 0x0 0x1000>;
  421                 clocks = <&xin24m>;
  422                 clock-names = "xin24m";
  423                 #clock-cells = <1>;
  424                 #reset-cells = <1>;
  425                 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
  426                 assigned-clock-rates = <1200000000>, <200000000>;
  427                 rockchip,grf = <&grf>;
  428         };
  429 
  430         i2c0: i2c@fdd40000 {
  431                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
  432                 reg = <0x0 0xfdd40000 0x0 0x1000>;
  433                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  434                 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
  435                 clock-names = "i2c", "pclk";
  436                 pinctrl-0 = <&i2c0_xfer>;
  437                 pinctrl-names = "default";
  438                 #address-cells = <1>;
  439                 #size-cells = <0>;
  440                 status = "disabled";
  441         };
  442 
  443         uart0: serial@fdd50000 {
  444                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
  445                 reg = <0x0 0xfdd50000 0x0 0x100>;
  446                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
  447                 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
  448                 clock-names = "baudclk", "apb_pclk";
  449                 dmas = <&dmac0 0>, <&dmac0 1>;
  450                 pinctrl-0 = <&uart0_xfer>;
  451                 pinctrl-names = "default";
  452                 reg-io-width = <4>;
  453                 reg-shift = <2>;
  454                 status = "disabled";
  455         };
  456 
  457         pwm0: pwm@fdd70000 {
  458                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  459                 reg = <0x0 0xfdd70000 0x0 0x10>;
  460                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
  461                 clock-names = "pwm", "pclk";
  462                 pinctrl-0 = <&pwm0m0_pins>;
  463                 pinctrl-names = "default";
  464                 #pwm-cells = <3>;
  465                 status = "disabled";
  466         };
  467 
  468         pwm1: pwm@fdd70010 {
  469                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  470                 reg = <0x0 0xfdd70010 0x0 0x10>;
  471                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
  472                 clock-names = "pwm", "pclk";
  473                 pinctrl-0 = <&pwm1m0_pins>;
  474                 pinctrl-names = "default";
  475                 #pwm-cells = <3>;
  476                 status = "disabled";
  477         };
  478 
  479         pwm2: pwm@fdd70020 {
  480                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  481                 reg = <0x0 0xfdd70020 0x0 0x10>;
  482                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
  483                 clock-names = "pwm", "pclk";
  484                 pinctrl-0 = <&pwm2m0_pins>;
  485                 pinctrl-names = "default";
  486                 #pwm-cells = <3>;
  487                 status = "disabled";
  488         };
  489 
  490         pwm3: pwm@fdd70030 {
  491                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
  492                 reg = <0x0 0xfdd70030 0x0 0x10>;
  493                 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
  494                 clock-names = "pwm", "pclk";
  495                 pinctrl-0 = <&pwm3_pins>;
  496                 pinctrl-names = "default";
  497                 #pwm-cells = <3>;
  498                 status = "disabled";
  499         };
  500 
  501         pmu: power-management@fdd90000 {
  502                 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
  503                 reg = <0x0 0xfdd90000 0x0 0x1000>;
  504 
  505                 power: power-controller {
  506                         compatible = "rockchip,rk3568-power-controller";
  507                         #power-domain-cells = <1>;
  508                         #address-cells = <1>;
  509                         #size-cells = <0>;
  510 
  511                         /* These power domains are grouped by VD_GPU */
  512                         power-domain@RK3568_PD_GPU {
  513                                 reg = <RK3568_PD_GPU>;
  514                                 clocks = <&cru ACLK_GPU_PRE>,
  515                                          <&cru PCLK_GPU_PRE>;
  516                                 pm_qos = <&qos_gpu>;
  517                                 #power-domain-cells = <0>;
  518                         };
  519 
  520                         /* These power domains are grouped by VD_LOGIC */
  521                         power-domain@RK3568_PD_VI {
  522                                 reg = <RK3568_PD_VI>;
  523                                 clocks = <&cru HCLK_VI>,
  524                                          <&cru PCLK_VI>;
  525                                 pm_qos = <&qos_isp>,
  526                                          <&qos_vicap0>,
  527                                          <&qos_vicap1>;
  528                                 #power-domain-cells = <0>;
  529                         };
  530 
  531                         power-domain@RK3568_PD_VO {
  532                                 reg = <RK3568_PD_VO>;
  533                                 clocks = <&cru HCLK_VO>,
  534                                          <&cru PCLK_VO>,
  535                                          <&cru ACLK_VOP_PRE>;
  536                                 pm_qos = <&qos_hdcp>,
  537                                          <&qos_vop_m0>,
  538                                          <&qos_vop_m1>;
  539                                 #power-domain-cells = <0>;
  540                         };
  541 
  542                         power-domain@RK3568_PD_RGA {
  543                                 reg = <RK3568_PD_RGA>;
  544                                 clocks = <&cru HCLK_RGA_PRE>,
  545                                          <&cru PCLK_RGA_PRE>;
  546                                 pm_qos = <&qos_ebc>,
  547                                          <&qos_iep>,
  548                                          <&qos_jpeg_dec>,
  549                                          <&qos_jpeg_enc>,
  550                                          <&qos_rga_rd>,
  551                                          <&qos_rga_wr>;
  552                                 #power-domain-cells = <0>;
  553                         };
  554 
  555                         power-domain@RK3568_PD_VPU {
  556                                 reg = <RK3568_PD_VPU>;
  557                                 clocks = <&cru HCLK_VPU_PRE>;
  558                                 pm_qos = <&qos_vpu>;
  559                                 #power-domain-cells = <0>;
  560                         };
  561 
  562                         power-domain@RK3568_PD_RKVDEC {
  563                                 clocks = <&cru HCLK_RKVDEC_PRE>;
  564                                 reg = <RK3568_PD_RKVDEC>;
  565                                 pm_qos = <&qos_rkvdec>;
  566                                 #power-domain-cells = <0>;
  567                         };
  568 
  569                         power-domain@RK3568_PD_RKVENC {
  570                                 reg = <RK3568_PD_RKVENC>;
  571                                 clocks = <&cru HCLK_RKVENC_PRE>;
  572                                 pm_qos = <&qos_rkvenc_rd_m0>,
  573                                          <&qos_rkvenc_rd_m1>,
  574                                          <&qos_rkvenc_wr_m0>;
  575                                 #power-domain-cells = <0>;
  576                         };
  577                 };
  578         };
  579 
  580         gpu: gpu@fde60000 {
  581                 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
  582                 reg = <0x0 0xfde60000 0x0 0x4000>;
  583                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  584                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  585                              <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  586                 interrupt-names = "job", "mmu", "gpu";
  587                 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
  588                 clock-names = "gpu", "bus";
  589                 #cooling-cells = <2>;
  590                 operating-points-v2 = <&gpu_opp_table>;
  591                 power-domains = <&power RK3568_PD_GPU>;
  592                 status = "disabled";
  593         };
  594 
  595         sdmmc2: mmc@fe000000 {
  596                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
  597                 reg = <0x0 0xfe000000 0x0 0x4000>;
  598                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
  599                 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
  600                          <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
  601                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  602                 fifo-depth = <0x100>;
  603                 max-frequency = <150000000>;
  604                 resets = <&cru SRST_SDMMC2>;
  605                 reset-names = "reset";
  606                 status = "disabled";
  607         };
  608 
  609         gmac1: ethernet@fe010000 {
  610                 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
  611                 reg = <0x0 0xfe010000 0x0 0x10000>;
  612                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  613                              <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
  614                 interrupt-names = "macirq", "eth_wake_irq";
  615                 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
  616                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
  617                          <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
  618                          <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
  619                 clock-names = "stmmaceth", "mac_clk_rx",
  620                               "mac_clk_tx", "clk_mac_refout",
  621                               "aclk_mac", "pclk_mac",
  622                               "clk_mac_speed", "ptp_ref";
  623                 resets = <&cru SRST_A_GMAC1>;
  624                 reset-names = "stmmaceth";
  625                 rockchip,grf = <&grf>;
  626                 snps,axi-config = <&gmac1_stmmac_axi_setup>;
  627                 snps,mixed-burst;
  628                 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
  629                 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
  630                 snps,tso;
  631                 status = "disabled";
  632 
  633                 mdio1: mdio {
  634                         compatible = "snps,dwmac-mdio";
  635                         #address-cells = <0x1>;
  636                         #size-cells = <0x0>;
  637                 };
  638 
  639                 gmac1_stmmac_axi_setup: stmmac-axi-config {
  640                         snps,blen = <0 0 0 0 16 8 4>;
  641                         snps,rd_osr_lmt = <8>;
  642                         snps,wr_osr_lmt = <4>;
  643                 };
  644 
  645                 gmac1_mtl_rx_setup: rx-queues-config {
  646                         snps,rx-queues-to-use = <1>;
  647                         queue0 {};
  648                 };
  649 
  650                 gmac1_mtl_tx_setup: tx-queues-config {
  651                         snps,tx-queues-to-use = <1>;
  652                         queue0 {};
  653                 };
  654         };
  655 
  656         vop: vop@fe040000 {
  657                 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
  658                 reg-names = "vop", "gamma-lut";
  659                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  660                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
  661                          <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
  662                 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
  663                 iommus = <&vop_mmu>;
  664                 power-domains = <&power RK3568_PD_VO>;
  665                 rockchip,grf = <&grf>;
  666                 status = "disabled";
  667 
  668                 vop_out: ports {
  669                         #address-cells = <1>;
  670                         #size-cells = <0>;
  671 
  672                         vp0: port@0 {
  673                                 reg = <0>;
  674                                 #address-cells = <1>;
  675                                 #size-cells = <0>;
  676                         };
  677 
  678                         vp1: port@1 {
  679                                 reg = <1>;
  680                                 #address-cells = <1>;
  681                                 #size-cells = <0>;
  682                         };
  683 
  684                         vp2: port@2 {
  685                                 reg = <2>;
  686                                 #address-cells = <1>;
  687                                 #size-cells = <0>;
  688                         };
  689                 };
  690         };
  691 
  692         vop_mmu: iommu@fe043e00 {
  693                 compatible = "rockchip,rk3568-iommu";
  694                 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
  695                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
  696                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
  697                 clock-names = "aclk", "iface";
  698                 #iommu-cells = <0>;
  699                 status = "disabled";
  700         };
  701 
  702         hdmi: hdmi@fe0a0000 {
  703                 compatible = "rockchip,rk3568-dw-hdmi";
  704                 reg = <0x0 0xfe0a0000 0x0 0x20000>;
  705                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  706                 clocks = <&cru PCLK_HDMI_HOST>,
  707                          <&cru CLK_HDMI_SFR>,
  708                          <&cru CLK_HDMI_CEC>,
  709                          <&pmucru CLK_HDMI_REF>,
  710                          <&cru HCLK_VO>;
  711                 clock-names = "iahb", "isfr", "cec", "ref";
  712                 pinctrl-names = "default";
  713                 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
  714                 power-domains = <&power RK3568_PD_VO>;
  715                 reg-io-width = <4>;
  716                 rockchip,grf = <&grf>;
  717                 #sound-dai-cells = <0>;
  718                 status = "disabled";
  719 
  720                 ports {
  721                         #address-cells = <1>;
  722                         #size-cells = <0>;
  723 
  724                         hdmi_in: port@0 {
  725                                 reg = <0>;
  726                         };
  727 
  728                         hdmi_out: port@1 {
  729                                 reg = <1>;
  730                         };
  731                 };
  732         };
  733 
  734         qos_gpu: qos@fe128000 {
  735                 compatible = "rockchip,rk3568-qos", "syscon";
  736                 reg = <0x0 0xfe128000 0x0 0x20>;
  737         };
  738 
  739         qos_rkvenc_rd_m0: qos@fe138080 {
  740                 compatible = "rockchip,rk3568-qos", "syscon";
  741                 reg = <0x0 0xfe138080 0x0 0x20>;
  742         };
  743 
  744         qos_rkvenc_rd_m1: qos@fe138100 {
  745                 compatible = "rockchip,rk3568-qos", "syscon";
  746                 reg = <0x0 0xfe138100 0x0 0x20>;
  747         };
  748 
  749         qos_rkvenc_wr_m0: qos@fe138180 {
  750                 compatible = "rockchip,rk3568-qos", "syscon";
  751                 reg = <0x0 0xfe138180 0x0 0x20>;
  752         };
  753 
  754         qos_isp: qos@fe148000 {
  755                 compatible = "rockchip,rk3568-qos", "syscon";
  756                 reg = <0x0 0xfe148000 0x0 0x20>;
  757         };
  758 
  759         qos_vicap0: qos@fe148080 {
  760                 compatible = "rockchip,rk3568-qos", "syscon";
  761                 reg = <0x0 0xfe148080 0x0 0x20>;
  762         };
  763 
  764         qos_vicap1: qos@fe148100 {
  765                 compatible = "rockchip,rk3568-qos", "syscon";
  766                 reg = <0x0 0xfe148100 0x0 0x20>;
  767         };
  768 
  769         qos_vpu: qos@fe150000 {
  770                 compatible = "rockchip,rk3568-qos", "syscon";
  771                 reg = <0x0 0xfe150000 0x0 0x20>;
  772         };
  773 
  774         qos_ebc: qos@fe158000 {
  775                 compatible = "rockchip,rk3568-qos", "syscon";
  776                 reg = <0x0 0xfe158000 0x0 0x20>;
  777         };
  778 
  779         qos_iep: qos@fe158100 {
  780                 compatible = "rockchip,rk3568-qos", "syscon";
  781                 reg = <0x0 0xfe158100 0x0 0x20>;
  782         };
  783 
  784         qos_jpeg_dec: qos@fe158180 {
  785                 compatible = "rockchip,rk3568-qos", "syscon";
  786                 reg = <0x0 0xfe158180 0x0 0x20>;
  787         };
  788 
  789         qos_jpeg_enc: qos@fe158200 {
  790                 compatible = "rockchip,rk3568-qos", "syscon";
  791                 reg = <0x0 0xfe158200 0x0 0x20>;
  792         };
  793 
  794         qos_rga_rd: qos@fe158280 {
  795                 compatible = "rockchip,rk3568-qos", "syscon";
  796                 reg = <0x0 0xfe158280 0x0 0x20>;
  797         };
  798 
  799         qos_rga_wr: qos@fe158300 {
  800                 compatible = "rockchip,rk3568-qos", "syscon";
  801                 reg = <0x0 0xfe158300 0x0 0x20>;
  802         };
  803 
  804         qos_npu: qos@fe180000 {
  805                 compatible = "rockchip,rk3568-qos", "syscon";
  806                 reg = <0x0 0xfe180000 0x0 0x20>;
  807         };
  808 
  809         qos_pcie2x1: qos@fe190000 {
  810                 compatible = "rockchip,rk3568-qos", "syscon";
  811                 reg = <0x0 0xfe190000 0x0 0x20>;
  812         };
  813 
  814         qos_sata1: qos@fe190280 {
  815                 compatible = "rockchip,rk3568-qos", "syscon";
  816                 reg = <0x0 0xfe190280 0x0 0x20>;
  817         };
  818 
  819         qos_sata2: qos@fe190300 {
  820                 compatible = "rockchip,rk3568-qos", "syscon";
  821                 reg = <0x0 0xfe190300 0x0 0x20>;
  822         };
  823 
  824         qos_usb3_0: qos@fe190380 {
  825                 compatible = "rockchip,rk3568-qos", "syscon";
  826                 reg = <0x0 0xfe190380 0x0 0x20>;
  827         };
  828 
  829         qos_usb3_1: qos@fe190400 {
  830                 compatible = "rockchip,rk3568-qos", "syscon";
  831                 reg = <0x0 0xfe190400 0x0 0x20>;
  832         };
  833 
  834         qos_rkvdec: qos@fe198000 {
  835                 compatible = "rockchip,rk3568-qos", "syscon";
  836                 reg = <0x0 0xfe198000 0x0 0x20>;
  837         };
  838 
  839         qos_hdcp: qos@fe1a8000 {
  840                 compatible = "rockchip,rk3568-qos", "syscon";
  841                 reg = <0x0 0xfe1a8000 0x0 0x20>;
  842         };
  843 
  844         qos_vop_m0: qos@fe1a8080 {
  845                 compatible = "rockchip,rk3568-qos", "syscon";
  846                 reg = <0x0 0xfe1a8080 0x0 0x20>;
  847         };
  848 
  849         qos_vop_m1: qos@fe1a8100 {
  850                 compatible = "rockchip,rk3568-qos", "syscon";
  851                 reg = <0x0 0xfe1a8100 0x0 0x20>;
  852         };
  853 
  854         pcie2x1: pcie@fe260000 {
  855                 compatible = "rockchip,rk3568-pcie";
  856                 reg = <0x3 0xc0000000 0x0 0x00400000>,
  857                       <0x0 0xfe260000 0x0 0x00010000>,
  858                       <0x3 0x3f000000 0x0 0x01000000>;
  859                 reg-names = "dbi", "apb", "config";
  860                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
  861                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
  862                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
  863                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
  864                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  865                 interrupt-names = "sys", "pmc", "msi", "legacy", "err";
  866                 bus-range = <0x0 0xf>;
  867                 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
  868                          <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
  869                          <&cru CLK_PCIE20_AUX_NDFT>;
  870                 clock-names = "aclk_mst", "aclk_slv",
  871                               "aclk_dbi", "pclk", "aux";
  872                 device_type = "pci";
  873                 interrupt-map-mask = <0 0 0 7>;
  874                 interrupt-map = <0 0 0 1 &pcie_intc 0>,
  875                                 <0 0 0 2 &pcie_intc 1>,
  876                                 <0 0 0 3 &pcie_intc 2>,
  877                                 <0 0 0 4 &pcie_intc 3>;
  878                 linux,pci-domain = <0>;
  879                 num-ib-windows = <6>;
  880                 num-ob-windows = <2>;
  881                 max-link-speed = <2>;
  882                 msi-map = <0x0 &gic 0x0 0x1000>;
  883                 num-lanes = <1>;
  884                 phys = <&combphy2 PHY_TYPE_PCIE>;
  885                 phy-names = "pcie-phy";
  886                 power-domains = <&power RK3568_PD_PIPE>;
  887                 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
  888                           0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
  889                 resets = <&cru SRST_PCIE20_POWERUP>;
  890                 reset-names = "pipe";
  891                 #address-cells = <3>;
  892                 #size-cells = <2>;
  893                 status = "disabled";
  894 
  895                 pcie_intc: legacy-interrupt-controller {
  896                         #address-cells = <0>;
  897                         #interrupt-cells = <1>;
  898                         interrupt-controller;
  899                         interrupt-parent = <&gic>;
  900                         interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
  901                 };
  902         };
  903 
  904         sdmmc0: mmc@fe2b0000 {
  905                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
  906                 reg = <0x0 0xfe2b0000 0x0 0x4000>;
  907                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  908                 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
  909                          <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
  910                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  911                 fifo-depth = <0x100>;
  912                 max-frequency = <150000000>;
  913                 resets = <&cru SRST_SDMMC0>;
  914                 reset-names = "reset";
  915                 status = "disabled";
  916         };
  917 
  918         sdmmc1: mmc@fe2c0000 {
  919                 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
  920                 reg = <0x0 0xfe2c0000 0x0 0x4000>;
  921                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
  922                 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
  923                          <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
  924                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  925                 fifo-depth = <0x100>;
  926                 max-frequency = <150000000>;
  927                 resets = <&cru SRST_SDMMC1>;
  928                 reset-names = "reset";
  929                 status = "disabled";
  930         };
  931 
  932         sfc: spi@fe300000 {
  933                 compatible = "rockchip,sfc";
  934                 reg = <0x0 0xfe300000 0x0 0x4000>;
  935                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
  936                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
  937                 clock-names = "clk_sfc", "hclk_sfc";
  938                 pinctrl-0 = <&fspi_pins>;
  939                 pinctrl-names = "default";
  940                 status = "disabled";
  941         };
  942 
  943         sdhci: mmc@fe310000 {
  944                 compatible = "rockchip,rk3568-dwcmshc";
  945                 reg = <0x0 0xfe310000 0x0 0x10000>;
  946                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  947                 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
  948                 assigned-clock-rates = <200000000>, <24000000>;
  949                 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
  950                          <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
  951                          <&cru TCLK_EMMC>;
  952                 clock-names = "core", "bus", "axi", "block", "timer";
  953                 status = "disabled";
  954         };
  955 
  956         spdif: spdif@fe460000 {
  957                 compatible = "rockchip,rk3568-spdif";
  958                 reg = <0x0 0xfe460000 0x0 0x1000>;
  959                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
  960                 clock-names = "mclk", "hclk";
  961                 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
  962                 dmas = <&dmac1 1>;
  963                 dma-names = "tx";
  964                 pinctrl-names = "default";
  965                 pinctrl-0 = <&spdifm0_tx>;
  966                 #sound-dai-cells = <0>;
  967                 status = "disabled";
  968         };
  969 
  970         i2s0_8ch: i2s@fe400000 {
  971                 compatible = "rockchip,rk3568-i2s-tdm";
  972                 reg = <0x0 0xfe400000 0x0 0x1000>;
  973                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
  974                 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
  975                 assigned-clock-rates = <1188000000>, <1188000000>;
  976                 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
  977                 clock-names = "mclk_tx", "mclk_rx", "hclk";
  978                 dmas = <&dmac1 0>;
  979                 dma-names = "tx";
  980                 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
  981                 reset-names = "tx-m", "rx-m";
  982                 rockchip,grf = <&grf>;
  983                 #sound-dai-cells = <0>;
  984                 status = "disabled";
  985         };
  986 
  987         i2s1_8ch: i2s@fe410000 {
  988                 compatible = "rockchip,rk3568-i2s-tdm";
  989                 reg = <0x0 0xfe410000 0x0 0x1000>;
  990                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
  991                 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
  992                 assigned-clock-rates = <1188000000>, <1188000000>;
  993                 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
  994                          <&cru HCLK_I2S1_8CH>;
  995                 clock-names = "mclk_tx", "mclk_rx", "hclk";
  996                 dmas = <&dmac1 3>, <&dmac1 2>;
  997                 dma-names = "rx", "tx";
  998                 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
  999                 reset-names = "tx-m", "rx-m";
 1000                 rockchip,grf = <&grf>;
 1001                 pinctrl-names = "default";
 1002                 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
 1003                              &i2s1m0_lrcktx &i2s1m0_lrckrx
 1004                              &i2s1m0_sdi0   &i2s1m0_sdi1
 1005                              &i2s1m0_sdi2   &i2s1m0_sdi3
 1006                              &i2s1m0_sdo0   &i2s1m0_sdo1
 1007                              &i2s1m0_sdo2   &i2s1m0_sdo3>;
 1008                 #sound-dai-cells = <0>;
 1009                 status = "disabled";
 1010         };
 1011 
 1012         i2s3_2ch: i2s@fe430000 {
 1013                 compatible = "rockchip,rk3568-i2s-tdm";
 1014                 reg = <0x0 0xfe430000 0x0 0x1000>;
 1015                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 1016                 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
 1017                          <&cru HCLK_I2S3_2CH>;
 1018                 clock-names = "mclk_tx", "mclk_rx", "hclk";
 1019                 dmas = <&dmac1 6>, <&dmac1 7>;
 1020                 dma-names = "tx", "rx";
 1021                 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
 1022                 reset-names = "tx-m", "rx-m";
 1023                 rockchip,grf = <&grf>;
 1024                 #sound-dai-cells = <0>;
 1025                 status = "disabled";
 1026         };
 1027 
 1028         pdm: pdm@fe440000 {
 1029                 compatible = "rockchip,rk3568-pdm";
 1030                 reg = <0x0 0xfe440000 0x0 0x1000>;
 1031                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 1032                 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
 1033                 clock-names = "pdm_clk", "pdm_hclk";
 1034                 dmas = <&dmac1 9>;
 1035                 dma-names = "rx";
 1036                 pinctrl-0 = <&pdmm0_clk
 1037                              &pdmm0_clk1
 1038                              &pdmm0_sdi0
 1039                              &pdmm0_sdi1
 1040                              &pdmm0_sdi2
 1041                              &pdmm0_sdi3>;
 1042                 pinctrl-names = "default";
 1043                 resets = <&cru SRST_M_PDM>;
 1044                 reset-names = "pdm-m";
 1045                 #sound-dai-cells = <0>;
 1046                 status = "disabled";
 1047         };
 1048 
 1049         dmac0: dma-controller@fe530000 {
 1050                 compatible = "arm,pl330", "arm,primecell";
 1051                 reg = <0x0 0xfe530000 0x0 0x4000>;
 1052                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 1053                              <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 1054                 arm,pl330-periph-burst;
 1055                 clocks = <&cru ACLK_BUS>;
 1056                 clock-names = "apb_pclk";
 1057                 #dma-cells = <1>;
 1058         };
 1059 
 1060         dmac1: dma-controller@fe550000 {
 1061                 compatible = "arm,pl330", "arm,primecell";
 1062                 reg = <0x0 0xfe550000 0x0 0x4000>;
 1063                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 1064                              <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 1065                 arm,pl330-periph-burst;
 1066                 clocks = <&cru ACLK_BUS>;
 1067                 clock-names = "apb_pclk";
 1068                 #dma-cells = <1>;
 1069         };
 1070 
 1071         i2c1: i2c@fe5a0000 {
 1072                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 1073                 reg = <0x0 0xfe5a0000 0x0 0x1000>;
 1074                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 1075                 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
 1076                 clock-names = "i2c", "pclk";
 1077                 pinctrl-0 = <&i2c1_xfer>;
 1078                 pinctrl-names = "default";
 1079                 #address-cells = <1>;
 1080                 #size-cells = <0>;
 1081                 status = "disabled";
 1082         };
 1083 
 1084         i2c2: i2c@fe5b0000 {
 1085                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 1086                 reg = <0x0 0xfe5b0000 0x0 0x1000>;
 1087                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 1088                 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
 1089                 clock-names = "i2c", "pclk";
 1090                 pinctrl-0 = <&i2c2m0_xfer>;
 1091                 pinctrl-names = "default";
 1092                 #address-cells = <1>;
 1093                 #size-cells = <0>;
 1094                 status = "disabled";
 1095         };
 1096 
 1097         i2c3: i2c@fe5c0000 {
 1098                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 1099                 reg = <0x0 0xfe5c0000 0x0 0x1000>;
 1100                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 1101                 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
 1102                 clock-names = "i2c", "pclk";
 1103                 pinctrl-0 = <&i2c3m0_xfer>;
 1104                 pinctrl-names = "default";
 1105                 #address-cells = <1>;
 1106                 #size-cells = <0>;
 1107                 status = "disabled";
 1108         };
 1109 
 1110         i2c4: i2c@fe5d0000 {
 1111                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 1112                 reg = <0x0 0xfe5d0000 0x0 0x1000>;
 1113                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 1114                 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
 1115                 clock-names = "i2c", "pclk";
 1116                 pinctrl-0 = <&i2c4m0_xfer>;
 1117                 pinctrl-names = "default";
 1118                 #address-cells = <1>;
 1119                 #size-cells = <0>;
 1120                 status = "disabled";
 1121         };
 1122 
 1123         i2c5: i2c@fe5e0000 {
 1124                 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
 1125                 reg = <0x0 0xfe5e0000 0x0 0x1000>;
 1126                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 1127                 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
 1128                 clock-names = "i2c", "pclk";
 1129                 pinctrl-0 = <&i2c5m0_xfer>;
 1130                 pinctrl-names = "default";
 1131                 #address-cells = <1>;
 1132                 #size-cells = <0>;
 1133                 status = "disabled";
 1134         };
 1135 
 1136         wdt: watchdog@fe600000 {
 1137                 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
 1138                 reg = <0x0 0xfe600000 0x0 0x100>;
 1139                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 1140                 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
 1141                 clock-names = "tclk", "pclk";
 1142         };
 1143 
 1144         spi0: spi@fe610000 {
 1145                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 1146                 reg = <0x0 0xfe610000 0x0 0x1000>;
 1147                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 1148                 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
 1149                 clock-names = "spiclk", "apb_pclk";
 1150                 dmas = <&dmac0 20>, <&dmac0 21>;
 1151                 dma-names = "tx", "rx";
 1152                 pinctrl-names = "default";
 1153                 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
 1154                 #address-cells = <1>;
 1155                 #size-cells = <0>;
 1156                 status = "disabled";
 1157         };
 1158 
 1159         spi1: spi@fe620000 {
 1160                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 1161                 reg = <0x0 0xfe620000 0x0 0x1000>;
 1162                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 1163                 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
 1164                 clock-names = "spiclk", "apb_pclk";
 1165                 dmas = <&dmac0 22>, <&dmac0 23>;
 1166                 dma-names = "tx", "rx";
 1167                 pinctrl-names = "default";
 1168                 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
 1169                 #address-cells = <1>;
 1170                 #size-cells = <0>;
 1171                 status = "disabled";
 1172         };
 1173 
 1174         spi2: spi@fe630000 {
 1175                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 1176                 reg = <0x0 0xfe630000 0x0 0x1000>;
 1177                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 1178                 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
 1179                 clock-names = "spiclk", "apb_pclk";
 1180                 dmas = <&dmac0 24>, <&dmac0 25>;
 1181                 dma-names = "tx", "rx";
 1182                 pinctrl-names = "default";
 1183                 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
 1184                 #address-cells = <1>;
 1185                 #size-cells = <0>;
 1186                 status = "disabled";
 1187         };
 1188 
 1189         spi3: spi@fe640000 {
 1190                 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
 1191                 reg = <0x0 0xfe640000 0x0 0x1000>;
 1192                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 1193                 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
 1194                 clock-names = "spiclk", "apb_pclk";
 1195                 dmas = <&dmac0 26>, <&dmac0 27>;
 1196                 dma-names = "tx", "rx";
 1197                 pinctrl-names = "default";
 1198                 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
 1199                 #address-cells = <1>;
 1200                 #size-cells = <0>;
 1201                 status = "disabled";
 1202         };
 1203 
 1204         uart1: serial@fe650000 {
 1205                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1206                 reg = <0x0 0xfe650000 0x0 0x100>;
 1207                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 1208                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 1209                 clock-names = "baudclk", "apb_pclk";
 1210                 dmas = <&dmac0 2>, <&dmac0 3>;
 1211                 pinctrl-0 = <&uart1m0_xfer>;
 1212                 pinctrl-names = "default";
 1213                 reg-io-width = <4>;
 1214                 reg-shift = <2>;
 1215                 status = "disabled";
 1216         };
 1217 
 1218         uart2: serial@fe660000 {
 1219                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1220                 reg = <0x0 0xfe660000 0x0 0x100>;
 1221                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 1222                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 1223                 clock-names = "baudclk", "apb_pclk";
 1224                 dmas = <&dmac0 4>, <&dmac0 5>;
 1225                 pinctrl-0 = <&uart2m0_xfer>;
 1226                 pinctrl-names = "default";
 1227                 reg-io-width = <4>;
 1228                 reg-shift = <2>;
 1229                 status = "disabled";
 1230         };
 1231 
 1232         uart3: serial@fe670000 {
 1233                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1234                 reg = <0x0 0xfe670000 0x0 0x100>;
 1235                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 1236                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 1237                 clock-names = "baudclk", "apb_pclk";
 1238                 dmas = <&dmac0 6>, <&dmac0 7>;
 1239                 pinctrl-0 = <&uart3m0_xfer>;
 1240                 pinctrl-names = "default";
 1241                 reg-io-width = <4>;
 1242                 reg-shift = <2>;
 1243                 status = "disabled";
 1244         };
 1245 
 1246         uart4: serial@fe680000 {
 1247                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1248                 reg = <0x0 0xfe680000 0x0 0x100>;
 1249                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 1250                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 1251                 clock-names = "baudclk", "apb_pclk";
 1252                 dmas = <&dmac0 8>, <&dmac0 9>;
 1253                 pinctrl-0 = <&uart4m0_xfer>;
 1254                 pinctrl-names = "default";
 1255                 reg-io-width = <4>;
 1256                 reg-shift = <2>;
 1257                 status = "disabled";
 1258         };
 1259 
 1260         uart5: serial@fe690000 {
 1261                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1262                 reg = <0x0 0xfe690000 0x0 0x100>;
 1263                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 1264                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
 1265                 clock-names = "baudclk", "apb_pclk";
 1266                 dmas = <&dmac0 10>, <&dmac0 11>;
 1267                 pinctrl-0 = <&uart5m0_xfer>;
 1268                 pinctrl-names = "default";
 1269                 reg-io-width = <4>;
 1270                 reg-shift = <2>;
 1271                 status = "disabled";
 1272         };
 1273 
 1274         uart6: serial@fe6a0000 {
 1275                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1276                 reg = <0x0 0xfe6a0000 0x0 0x100>;
 1277                 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 1278                 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
 1279                 clock-names = "baudclk", "apb_pclk";
 1280                 dmas = <&dmac0 12>, <&dmac0 13>;
 1281                 pinctrl-0 = <&uart6m0_xfer>;
 1282                 pinctrl-names = "default";
 1283                 reg-io-width = <4>;
 1284                 reg-shift = <2>;
 1285                 status = "disabled";
 1286         };
 1287 
 1288         uart7: serial@fe6b0000 {
 1289                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1290                 reg = <0x0 0xfe6b0000 0x0 0x100>;
 1291                 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 1292                 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
 1293                 clock-names = "baudclk", "apb_pclk";
 1294                 dmas = <&dmac0 14>, <&dmac0 15>;
 1295                 pinctrl-0 = <&uart7m0_xfer>;
 1296                 pinctrl-names = "default";
 1297                 reg-io-width = <4>;
 1298                 reg-shift = <2>;
 1299                 status = "disabled";
 1300         };
 1301 
 1302         uart8: serial@fe6c0000 {
 1303                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1304                 reg = <0x0 0xfe6c0000 0x0 0x100>;
 1305                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 1306                 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
 1307                 clock-names = "baudclk", "apb_pclk";
 1308                 dmas = <&dmac0 16>, <&dmac0 17>;
 1309                 pinctrl-0 = <&uart8m0_xfer>;
 1310                 pinctrl-names = "default";
 1311                 reg-io-width = <4>;
 1312                 reg-shift = <2>;
 1313                 status = "disabled";
 1314         };
 1315 
 1316         uart9: serial@fe6d0000 {
 1317                 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
 1318                 reg = <0x0 0xfe6d0000 0x0 0x100>;
 1319                 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 1320                 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
 1321                 clock-names = "baudclk", "apb_pclk";
 1322                 dmas = <&dmac0 18>, <&dmac0 19>;
 1323                 pinctrl-0 = <&uart9m0_xfer>;
 1324                 pinctrl-names = "default";
 1325                 reg-io-width = <4>;
 1326                 reg-shift = <2>;
 1327                 status = "disabled";
 1328         };
 1329 
 1330         thermal_zones: thermal-zones {
 1331                 cpu_thermal: cpu-thermal {
 1332                         polling-delay-passive = <100>;
 1333                         polling-delay = <1000>;
 1334 
 1335                         thermal-sensors = <&tsadc 0>;
 1336 
 1337                         trips {
 1338                                 cpu_alert0: cpu_alert0 {
 1339                                         temperature = <70000>;
 1340                                         hysteresis = <2000>;
 1341                                         type = "passive";
 1342                                 };
 1343                                 cpu_alert1: cpu_alert1 {
 1344                                         temperature = <75000>;
 1345                                         hysteresis = <2000>;
 1346                                         type = "passive";
 1347                                 };
 1348                                 cpu_crit: cpu_crit {
 1349                                         temperature = <95000>;
 1350                                         hysteresis = <2000>;
 1351                                         type = "critical";
 1352                                 };
 1353                         };
 1354 
 1355                         cooling-maps {
 1356                                 map0 {
 1357                                         trip = <&cpu_alert0>;
 1358                                         cooling-device =
 1359                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1360                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1361                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 1362                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1363                                 };
 1364                         };
 1365                 };
 1366 
 1367                 gpu_thermal: gpu-thermal {
 1368                         polling-delay-passive = <20>; /* milliseconds */
 1369                         polling-delay = <1000>; /* milliseconds */
 1370 
 1371                         thermal-sensors = <&tsadc 1>;
 1372 
 1373                         trips {
 1374                                 gpu_threshold: gpu-threshold {
 1375                                         temperature = <70000>;
 1376                                         hysteresis = <2000>;
 1377                                         type = "passive";
 1378                                 };
 1379                                 gpu_target: gpu-target {
 1380                                         temperature = <75000>;
 1381                                         hysteresis = <2000>;
 1382                                         type = "passive";
 1383                                 };
 1384                                 gpu_crit: gpu-crit {
 1385                                         temperature = <95000>;
 1386                                         hysteresis = <2000>;
 1387                                         type = "critical";
 1388                                 };
 1389                         };
 1390 
 1391                         cooling-maps {
 1392                                 map0 {
 1393                                         trip = <&gpu_target>;
 1394                                         cooling-device =
 1395                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 1396                                 };
 1397                         };
 1398                 };
 1399         };
 1400 
 1401         tsadc: tsadc@fe710000 {
 1402                 compatible = "rockchip,rk3568-tsadc";
 1403                 reg = <0x0 0xfe710000 0x0 0x100>;
 1404                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 1405                 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
 1406                 assigned-clock-rates = <17000000>, <700000>;
 1407                 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
 1408                 clock-names = "tsadc", "apb_pclk";
 1409                 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
 1410                          <&cru SRST_TSADCPHY>;
 1411                 rockchip,grf = <&grf>;
 1412                 rockchip,hw-tshut-temp = <95000>;
 1413                 pinctrl-names = "init", "default", "sleep";
 1414                 pinctrl-0 = <&tsadc_pin>;
 1415                 pinctrl-1 = <&tsadc_shutorg>;
 1416                 pinctrl-2 = <&tsadc_pin>;
 1417                 #thermal-sensor-cells = <1>;
 1418                 status = "disabled";
 1419         };
 1420 
 1421         saradc: saradc@fe720000 {
 1422                 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
 1423                 reg = <0x0 0xfe720000 0x0 0x100>;
 1424                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 1425                 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
 1426                 clock-names = "saradc", "apb_pclk";
 1427                 resets = <&cru SRST_P_SARADC>;
 1428                 reset-names = "saradc-apb";
 1429                 #io-channel-cells = <1>;
 1430                 status = "disabled";
 1431         };
 1432 
 1433         pwm4: pwm@fe6e0000 {
 1434                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1435                 reg = <0x0 0xfe6e0000 0x0 0x10>;
 1436                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
 1437                 clock-names = "pwm", "pclk";
 1438                 pinctrl-0 = <&pwm4_pins>;
 1439                 pinctrl-names = "default";
 1440                 #pwm-cells = <3>;
 1441                 status = "disabled";
 1442         };
 1443 
 1444         pwm5: pwm@fe6e0010 {
 1445                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1446                 reg = <0x0 0xfe6e0010 0x0 0x10>;
 1447                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
 1448                 clock-names = "pwm", "pclk";
 1449                 pinctrl-0 = <&pwm5_pins>;
 1450                 pinctrl-names = "default";
 1451                 #pwm-cells = <3>;
 1452                 status = "disabled";
 1453         };
 1454 
 1455         pwm6: pwm@fe6e0020 {
 1456                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1457                 reg = <0x0 0xfe6e0020 0x0 0x10>;
 1458                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
 1459                 clock-names = "pwm", "pclk";
 1460                 pinctrl-0 = <&pwm6_pins>;
 1461                 pinctrl-names = "default";
 1462                 #pwm-cells = <3>;
 1463                 status = "disabled";
 1464         };
 1465 
 1466         pwm7: pwm@fe6e0030 {
 1467                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1468                 reg = <0x0 0xfe6e0030 0x0 0x10>;
 1469                 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
 1470                 clock-names = "pwm", "pclk";
 1471                 pinctrl-0 = <&pwm7_pins>;
 1472                 pinctrl-names = "default";
 1473                 #pwm-cells = <3>;
 1474                 status = "disabled";
 1475         };
 1476 
 1477         pwm8: pwm@fe6f0000 {
 1478                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1479                 reg = <0x0 0xfe6f0000 0x0 0x10>;
 1480                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
 1481                 clock-names = "pwm", "pclk";
 1482                 pinctrl-0 = <&pwm8m0_pins>;
 1483                 pinctrl-names = "default";
 1484                 #pwm-cells = <3>;
 1485                 status = "disabled";
 1486         };
 1487 
 1488         pwm9: pwm@fe6f0010 {
 1489                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1490                 reg = <0x0 0xfe6f0010 0x0 0x10>;
 1491                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
 1492                 clock-names = "pwm", "pclk";
 1493                 pinctrl-0 = <&pwm9m0_pins>;
 1494                 pinctrl-names = "default";
 1495                 #pwm-cells = <3>;
 1496                 status = "disabled";
 1497         };
 1498 
 1499         pwm10: pwm@fe6f0020 {
 1500                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1501                 reg = <0x0 0xfe6f0020 0x0 0x10>;
 1502                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
 1503                 clock-names = "pwm", "pclk";
 1504                 pinctrl-0 = <&pwm10m0_pins>;
 1505                 pinctrl-names = "default";
 1506                 #pwm-cells = <3>;
 1507                 status = "disabled";
 1508         };
 1509 
 1510         pwm11: pwm@fe6f0030 {
 1511                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1512                 reg = <0x0 0xfe6f0030 0x0 0x10>;
 1513                 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
 1514                 clock-names = "pwm", "pclk";
 1515                 pinctrl-0 = <&pwm11m0_pins>;
 1516                 pinctrl-names = "default";
 1517                 #pwm-cells = <3>;
 1518                 status = "disabled";
 1519         };
 1520 
 1521         pwm12: pwm@fe700000 {
 1522                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1523                 reg = <0x0 0xfe700000 0x0 0x10>;
 1524                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
 1525                 clock-names = "pwm", "pclk";
 1526                 pinctrl-0 = <&pwm12m0_pins>;
 1527                 pinctrl-names = "default";
 1528                 #pwm-cells = <3>;
 1529                 status = "disabled";
 1530         };
 1531 
 1532         pwm13: pwm@fe700010 {
 1533                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1534                 reg = <0x0 0xfe700010 0x0 0x10>;
 1535                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
 1536                 clock-names = "pwm", "pclk";
 1537                 pinctrl-0 = <&pwm13m0_pins>;
 1538                 pinctrl-names = "default";
 1539                 #pwm-cells = <3>;
 1540                 status = "disabled";
 1541         };
 1542 
 1543         pwm14: pwm@fe700020 {
 1544                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1545                 reg = <0x0 0xfe700020 0x0 0x10>;
 1546                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
 1547                 clock-names = "pwm", "pclk";
 1548                 pinctrl-0 = <&pwm14m0_pins>;
 1549                 pinctrl-names = "default";
 1550                 #pwm-cells = <3>;
 1551                 status = "disabled";
 1552         };
 1553 
 1554         pwm15: pwm@fe700030 {
 1555                 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
 1556                 reg = <0x0 0xfe700030 0x0 0x10>;
 1557                 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
 1558                 clock-names = "pwm", "pclk";
 1559                 pinctrl-0 = <&pwm15m0_pins>;
 1560                 pinctrl-names = "default";
 1561                 #pwm-cells = <3>;
 1562                 status = "disabled";
 1563         };
 1564 
 1565         combphy1: phy@fe830000 {
 1566                 compatible = "rockchip,rk3568-naneng-combphy";
 1567                 reg = <0x0 0xfe830000 0x0 0x100>;
 1568                 clocks = <&pmucru CLK_PCIEPHY1_REF>,
 1569                          <&cru PCLK_PIPEPHY1>,
 1570                          <&cru PCLK_PIPE>;
 1571                 clock-names = "ref", "apb", "pipe";
 1572                 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
 1573                 assigned-clock-rates = <100000000>;
 1574                 resets = <&cru SRST_PIPEPHY1>;
 1575                 rockchip,pipe-grf = <&pipegrf>;
 1576                 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
 1577                 #phy-cells = <1>;
 1578                 status = "disabled";
 1579         };
 1580 
 1581         combphy2: phy@fe840000 {
 1582                 compatible = "rockchip,rk3568-naneng-combphy";
 1583                 reg = <0x0 0xfe840000 0x0 0x100>;
 1584                 clocks = <&pmucru CLK_PCIEPHY2_REF>,
 1585                          <&cru PCLK_PIPEPHY2>,
 1586                          <&cru PCLK_PIPE>;
 1587                 clock-names = "ref", "apb", "pipe";
 1588                 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
 1589                 assigned-clock-rates = <100000000>;
 1590                 resets = <&cru SRST_PIPEPHY2>;
 1591                 rockchip,pipe-grf = <&pipegrf>;
 1592                 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
 1593                 #phy-cells = <1>;
 1594                 status = "disabled";
 1595         };
 1596 
 1597         usb2phy0: usb2phy@fe8a0000 {
 1598                 compatible = "rockchip,rk3568-usb2phy";
 1599                 reg = <0x0 0xfe8a0000 0x0 0x10000>;
 1600                 clocks = <&pmucru CLK_USBPHY0_REF>;
 1601                 clock-names = "phyclk";
 1602                 clock-output-names = "clk_usbphy0_480m";
 1603                 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 1604                 rockchip,usbgrf = <&usb2phy0_grf>;
 1605                 #clock-cells = <0>;
 1606                 status = "disabled";
 1607 
 1608                 usb2phy0_host: host-port {
 1609                         #phy-cells = <0>;
 1610                         status = "disabled";
 1611                 };
 1612 
 1613                 usb2phy0_otg: otg-port {
 1614                         #phy-cells = <0>;
 1615                         status = "disabled";
 1616                 };
 1617         };
 1618 
 1619         usb2phy1: usb2phy@fe8b0000 {
 1620                 compatible = "rockchip,rk3568-usb2phy";
 1621                 reg = <0x0 0xfe8b0000 0x0 0x10000>;
 1622                 clocks = <&pmucru CLK_USBPHY1_REF>;
 1623                 clock-names = "phyclk";
 1624                 clock-output-names = "clk_usbphy1_480m";
 1625                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 1626                 rockchip,usbgrf = <&usb2phy1_grf>;
 1627                 #clock-cells = <0>;
 1628                 status = "disabled";
 1629 
 1630                 usb2phy1_host: host-port {
 1631                         #phy-cells = <0>;
 1632                         status = "disabled";
 1633                 };
 1634 
 1635                 usb2phy1_otg: otg-port {
 1636                         #phy-cells = <0>;
 1637                         status = "disabled";
 1638                 };
 1639         };
 1640 
 1641         pinctrl: pinctrl {
 1642                 compatible = "rockchip,rk3568-pinctrl";
 1643                 rockchip,grf = <&grf>;
 1644                 rockchip,pmu = <&pmugrf>;
 1645                 #address-cells = <2>;
 1646                 #size-cells = <2>;
 1647                 ranges;
 1648 
 1649                 gpio0: gpio@fdd60000 {
 1650                         compatible = "rockchip,gpio-bank";
 1651                         reg = <0x0 0xfdd60000 0x0 0x100>;
 1652                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 1653                         clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
 1654                         gpio-controller;
 1655                         #gpio-cells = <2>;
 1656                         interrupt-controller;
 1657                         #interrupt-cells = <2>;
 1658                 };
 1659 
 1660                 gpio1: gpio@fe740000 {
 1661                         compatible = "rockchip,gpio-bank";
 1662                         reg = <0x0 0xfe740000 0x0 0x100>;
 1663                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 1664                         clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
 1665                         gpio-controller;
 1666                         #gpio-cells = <2>;
 1667                         interrupt-controller;
 1668                         #interrupt-cells = <2>;
 1669                 };
 1670 
 1671                 gpio2: gpio@fe750000 {
 1672                         compatible = "rockchip,gpio-bank";
 1673                         reg = <0x0 0xfe750000 0x0 0x100>;
 1674                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 1675                         clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
 1676                         gpio-controller;
 1677                         #gpio-cells = <2>;
 1678                         interrupt-controller;
 1679                         #interrupt-cells = <2>;
 1680                 };
 1681 
 1682                 gpio3: gpio@fe760000 {
 1683                         compatible = "rockchip,gpio-bank";
 1684                         reg = <0x0 0xfe760000 0x0 0x100>;
 1685                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 1686                         clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
 1687                         gpio-controller;
 1688                         #gpio-cells = <2>;
 1689                         interrupt-controller;
 1690                         #interrupt-cells = <2>;
 1691                 };
 1692 
 1693                 gpio4: gpio@fe770000 {
 1694                         compatible = "rockchip,gpio-bank";
 1695                         reg = <0x0 0xfe770000 0x0 0x100>;
 1696                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 1697                         clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
 1698                         gpio-controller;
 1699                         #gpio-cells = <2>;
 1700                         interrupt-controller;
 1701                         #interrupt-cells = <2>;
 1702                 };
 1703         };
 1704 };
 1705 
 1706 #include "rk3568-pinctrl.dtsi"
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/rockchip/rk356x.dtsi
