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sys/contrib/device-tree/src/arm64/ti/k3-am64-main.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8 #include <dt-bindings/phy/phy-cadence.h> 9 #include <dt-bindings/phy/phy-ti.h> 10 11 / { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17 }; 18 19 &cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 42 reg = <0x0 0x43000000 0x0 0x20000>; 43 #address-cells = <1>; 44 #size-cells = <1>; 45 ranges = <0x0 0x0 0x43000000 0x20000>; 46 47 serdes_ln_ctrl: mux-controller { 48 compatible = "mmio-mux"; 49 #mux-control-cells = <1>; 50 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 51 }; 52 }; 53 54 gic500: interrupt-controller@1800000 { 55 compatible = "arm,gic-v3"; 56 #address-cells = <2>; 57 #size-cells = <2>; 58 ranges; 59 #interrupt-cells = <3>; 60 interrupt-controller; 61 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 62 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 63 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 64 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 65 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 66 /* 67 * vcpumntirq: 68 * virtual CPU interface maintenance interrupt 69 */ 70 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 71 72 gic_its: msi-controller@1820000 { 73 compatible = "arm,gic-v3-its"; 74 reg = <0x00 0x01820000 0x00 0x10000>; 75 socionext,synquacer-pre-its = <0x1000000 0x400000>; 76 msi-controller; 77 #msi-cells = <1>; 78 }; 79 }; 80 81 dmss: bus@48000000 { 82 compatible = "simple-mfd"; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 dma-ranges; 86 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 87 88 ti,sci-dev-id = <25>; 89 90 secure_proxy_main: mailbox@4d000000 { 91 compatible = "ti,am654-secure-proxy"; 92 #mbox-cells = <1>; 93 reg-names = "target_data", "rt", "scfg"; 94 reg = <0x00 0x4d000000 0x00 0x80000>, 95 <0x00 0x4a600000 0x00 0x80000>, 96 <0x00 0x4a400000 0x00 0x80000>; 97 interrupt-names = "rx_012"; 98 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 99 }; 100 101 inta_main_dmss: interrupt-controller@48000000 { 102 compatible = "ti,sci-inta"; 103 reg = <0x00 0x48000000 0x00 0x100000>; 104 #interrupt-cells = <0>; 105 interrupt-controller; 106 interrupt-parent = <&gic500>; 107 msi-controller; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <28>; 110 ti,interrupt-ranges = <4 68 36>; 111 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 112 }; 113 114 main_bcdma: dma-controller@485c0100 { 115 compatible = "ti,am64-dmss-bcdma"; 116 reg = <0x00 0x485c0100 0x00 0x100>, 117 <0x00 0x4c000000 0x00 0x20000>, 118 <0x00 0x4a820000 0x00 0x20000>, 119 <0x00 0x4aa40000 0x00 0x20000>, 120 <0x00 0x4bc00000 0x00 0x100000>; 121 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 122 msi-parent = <&inta_main_dmss>; 123 #dma-cells = <3>; 124 125 ti,sci = <&dmsc>; 126 ti,sci-dev-id = <26>; 127 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 128 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 129 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 130 }; 131 132 main_pktdma: dma-controller@485c0000 { 133 compatible = "ti,am64-dmss-pktdma"; 134 reg = <0x00 0x485c0000 0x00 0x100>, 135 <0x00 0x4a800000 0x00 0x20000>, 136 <0x00 0x4aa00000 0x00 0x40000>, 137 <0x00 0x4b800000 0x00 0x400000>; 138 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 139 msi-parent = <&inta_main_dmss>; 140 #dma-cells = <2>; 141 142 ti,sci = <&dmsc>; 143 ti,sci-dev-id = <30>; 144 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 145 <0x24>, /* CPSW_TX_CHAN */ 146 <0x25>, /* SAUL_TX_0_CHAN */ 147 <0x26>, /* SAUL_TX_1_CHAN */ 148 <0x27>, /* ICSSG_0_TX_CHAN */ 149 <0x28>; /* ICSSG_1_TX_CHAN */ 150 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 151 <0x11>, /* RING_CPSW_TX_CHAN */ 152 <0x12>, /* RING_SAUL_TX_0_CHAN */ 153 <0x13>, /* RING_SAUL_TX_1_CHAN */ 154 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 155 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 156 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 157 <0x2b>, /* CPSW_RX_CHAN */ 158 <0x2d>, /* SAUL_RX_0_CHAN */ 159 <0x2f>, /* SAUL_RX_1_CHAN */ 160 <0x31>, /* SAUL_RX_2_CHAN */ 161 <0x33>, /* SAUL_RX_3_CHAN */ 162 <0x35>, /* ICSSG_0_RX_CHAN */ 163 <0x37>; /* ICSSG_1_RX_CHAN */ 164 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 165 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 166 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 167 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 168 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 169 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 170 }; 171 }; 172 173 dmsc: system-controller@44043000 { 174 compatible = "ti,k2g-sci"; 175 ti,host-id = <12>; 176 mbox-names = "rx", "tx"; 177 mboxes = <&secure_proxy_main 12>, 178 <&secure_proxy_main 13>; 179 reg-names = "debug_messages"; 180 reg = <0x00 0x44043000 0x00 0xfe0>; 181 182 k3_pds: power-controller { 183 compatible = "ti,sci-pm-domain"; 184 #power-domain-cells = <2>; 185 }; 186 187 k3_clks: clock-controller { 188 compatible = "ti,k2g-sci-clk"; 189 #clock-cells = <2>; 190 }; 191 192 k3_reset: reset-controller { 193 compatible = "ti,sci-reset"; 194 #reset-cells = <2>; 195 }; 196 }; 197 198 main_pmx0: pinctrl@f4000 { 199 compatible = "pinctrl-single"; 200 reg = <0x00 0xf4000 0x00 0x2d0>; 201 #pinctrl-cells = <1>; 202 pinctrl-single,register-width = <32>; 203 pinctrl-single,function-mask = <0xffffffff>; 204 }; 205 206 main_conf: syscon@43000000 { 207 compatible = "syscon", "simple-mfd"; 208 reg = <0x00 0x43000000 0x00 0x20000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0x00 0x00 0x43000000 0x20000>; 212 213 chipid@14 { 214 compatible = "ti,am654-chipid"; 215 reg = <0x00000014 0x4>; 216 }; 217 218 phy_gmii_sel: phy@4044 { 219 compatible = "ti,am654-phy-gmii-sel"; 220 reg = <0x4044 0x8>; 221 #phy-cells = <1>; 222 }; 223 224 epwm_tbclk: clock@4140 { 225 compatible = "ti,am64-epwm-tbclk", "syscon"; 226 reg = <0x4130 0x4>; 227 #clock-cells = <1>; 228 }; 229 }; 230 231 main_uart0: serial@2800000 { 232 compatible = "ti,am64-uart", "ti,am654-uart"; 233 reg = <0x00 0x02800000 0x00 0x100>; 234 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 235 clock-frequency = <48000000>; 236 current-speed = <115200>; 237 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 238 clocks = <&k3_clks 146 0>; 239 clock-names = "fclk"; 240 }; 241 242 main_uart1: serial@2810000 { 243 compatible = "ti,am64-uart", "ti,am654-uart"; 244 reg = <0x00 0x02810000 0x00 0x100>; 245 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 246 clock-frequency = <48000000>; 247 current-speed = <115200>; 248 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 249 clocks = <&k3_clks 152 0>; 250 clock-names = "fclk"; 251 }; 252 253 main_uart2: serial@2820000 { 254 compatible = "ti,am64-uart", "ti,am654-uart"; 255 reg = <0x00 0x02820000 0x00 0x100>; 256 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 257 clock-frequency = <48000000>; 258 current-speed = <115200>; 259 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 260 clocks = <&k3_clks 153 0>; 261 clock-names = "fclk"; 262 }; 263 264 main_uart3: serial@2830000 { 265 compatible = "ti,am64-uart", "ti,am654-uart"; 266 reg = <0x00 0x02830000 0x00 0x100>; 267 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 268 clock-frequency = <48000000>; 269 current-speed = <115200>; 270 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 271 clocks = <&k3_clks 154 0>; 272 clock-names = "fclk"; 273 }; 274 275 main_uart4: serial@2840000 { 276 compatible = "ti,am64-uart", "ti,am654-uart"; 277 reg = <0x00 0x02840000 0x00 0x100>; 278 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 279 clock-frequency = <48000000>; 280 current-speed = <115200>; 281 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 282 clocks = <&k3_clks 155 0>; 283 clock-names = "fclk"; 284 }; 285 286 main_uart5: serial@2850000 { 287 compatible = "ti,am64-uart", "ti,am654-uart"; 288 reg = <0x00 0x02850000 0x00 0x100>; 289 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 290 clock-frequency = <48000000>; 291 current-speed = <115200>; 292 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 293 clocks = <&k3_clks 156 0>; 294 clock-names = "fclk"; 295 }; 296 297 main_uart6: serial@2860000 { 298 compatible = "ti,am64-uart", "ti,am654-uart"; 299 reg = <0x00 0x02860000 0x00 0x100>; 300 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 301 clock-frequency = <48000000>; 302 current-speed = <115200>; 303 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 304 clocks = <&k3_clks 158 0>; 305 clock-names = "fclk"; 306 }; 307 308 main_i2c0: i2c@20000000 { 309 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 310 reg = <0x00 0x20000000 0x00 0x100>; 311 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 315 clocks = <&k3_clks 102 2>; 316 clock-names = "fck"; 317 }; 318 319 main_i2c1: i2c@20010000 { 320 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 321 reg = <0x00 0x20010000 0x00 0x100>; 322 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 326 clocks = <&k3_clks 103 2>; 327 clock-names = "fck"; 328 }; 329 330 main_i2c2: i2c@20020000 { 331 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 332 reg = <0x00 0x20020000 0x00 0x100>; 333 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 337 clocks = <&k3_clks 104 2>; 338 clock-names = "fck"; 339 }; 340 341 main_i2c3: i2c@20030000 { 342 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 343 reg = <0x00 0x20030000 0x00 0x100>; 344 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 348 clocks = <&k3_clks 105 2>; 349 clock-names = "fck"; 350 }; 351 352 main_spi0: spi@20100000 { 353 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 354 reg = <0x00 0x20100000 0x00 0x400>; 355 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 359 clocks = <&k3_clks 141 0>; 360 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 361 dma-names = "tx0", "rx0"; 362 }; 363 364 main_spi1: spi@20110000 { 365 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 366 reg = <0x00 0x20110000 0x00 0x400>; 367 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 371 clocks = <&k3_clks 142 0>; 372 }; 373 374 main_spi2: spi@20120000 { 375 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 376 reg = <0x00 0x20120000 0x00 0x400>; 377 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 378 #address-cells = <1>; 379 #size-cells = <0>; 380 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 381 clocks = <&k3_clks 143 0>; 382 }; 383 384 main_spi3: spi@20130000 { 385 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 386 reg = <0x00 0x20130000 0x00 0x400>; 387 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 391 clocks = <&k3_clks 144 0>; 392 }; 393 394 main_spi4: spi@20140000 { 395 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 396 reg = <0x00 0x20140000 0x00 0x400>; 397 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 145 0>; 402 }; 403 404 main_gpio_intr: interrupt-controller@a00000 { 405 compatible = "ti,sci-intr"; 406 reg = <0x00 0x00a00000 0x00 0x800>; 407 ti,intr-trigger-type = <1>; 408 interrupt-controller; 409 interrupt-parent = <&gic500>; 410 #interrupt-cells = <1>; 411 ti,sci = <&dmsc>; 412 ti,sci-dev-id = <3>; 413 ti,interrupt-ranges = <0 32 16>; 414 }; 415 416 main_gpio0: gpio@600000 { 417 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 418 reg = <0x0 0x00600000 0x0 0x100>; 419 gpio-controller; 420 #gpio-cells = <2>; 421 interrupt-parent = <&main_gpio_intr>; 422 interrupts = <190>, <191>, <192>, 423 <193>, <194>, <195>; 424 interrupt-controller; 425 #interrupt-cells = <2>; 426 ti,ngpio = <87>; 427 ti,davinci-gpio-unbanked = <0>; 428 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 77 0>; 430 clock-names = "gpio"; 431 }; 432 433 main_gpio1: gpio@601000 { 434 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 435 reg = <0x0 0x00601000 0x0 0x100>; 436 gpio-controller; 437 #gpio-cells = <2>; 438 interrupt-parent = <&main_gpio_intr>; 439 interrupts = <180>, <181>, <182>, 440 <183>, <184>, <185>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 ti,ngpio = <88>; 444 ti,davinci-gpio-unbanked = <0>; 445 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 446 clocks = <&k3_clks 78 0>; 447 clock-names = "gpio"; 448 }; 449 450 sdhci0: mmc@fa10000 { 451 compatible = "ti,am64-sdhci-8bit"; 452 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 453 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 454 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 455 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 456 clock-names = "clk_ahb", "clk_xin"; 457 mmc-ddr-1_8v; 458 mmc-hs200-1_8v; 459 ti,trm-icp = <0x2>; 460 ti,otap-del-sel-legacy = <0x0>; 461 ti,otap-del-sel-mmc-hs = <0x0>; 462 ti,otap-del-sel-ddr52 = <0x6>; 463 ti,otap-del-sel-hs200 = <0x7>; 464 }; 465 466 sdhci1: mmc@fa00000 { 467 compatible = "ti,am64-sdhci-4bit"; 468 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 469 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 470 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 471 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 472 clock-names = "clk_ahb", "clk_xin"; 473 ti,trm-icp = <0x2>; 474 ti,otap-del-sel-legacy = <0x0>; 475 ti,otap-del-sel-sd-hs = <0xf>; 476 ti,otap-del-sel-sdr12 = <0xf>; 477 ti,otap-del-sel-sdr25 = <0xf>; 478 ti,otap-del-sel-sdr50 = <0xc>; 479 ti,otap-del-sel-sdr104 = <0x6>; 480 ti,otap-del-sel-ddr50 = <0x9>; 481 ti,clkbuf-sel = <0x7>; 482 }; 483 484 cpsw3g: ethernet@8000000 { 485 compatible = "ti,am642-cpsw-nuss"; 486 #address-cells = <2>; 487 #size-cells = <2>; 488 reg = <0x0 0x8000000 0x0 0x200000>; 489 reg-names = "cpsw_nuss"; 490 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 491 clocks = <&k3_clks 13 0>; 492 assigned-clocks = <&k3_clks 13 1>; 493 assigned-clock-parents = <&k3_clks 13 9>; 494 clock-names = "fck"; 495 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 496 497 dmas = <&main_pktdma 0xC500 15>, 498 <&main_pktdma 0xC501 15>, 499 <&main_pktdma 0xC502 15>, 500 <&main_pktdma 0xC503 15>, 501 <&main_pktdma 0xC504 15>, 502 <&main_pktdma 0xC505 15>, 503 <&main_pktdma 0xC506 15>, 504 <&main_pktdma 0xC507 15>, 505 <&main_pktdma 0x4500 15>; 506 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 507 "tx7", "rx"; 508 509 ethernet-ports { 510 #address-cells = <1>; 511 #size-cells = <0>; 512 513 cpsw_port1: port@1 { 514 reg = <1>; 515 ti,mac-only; 516 label = "port1"; 517 phys = <&phy_gmii_sel 1>; 518 mac-address = [00 00 00 00 00 00]; 519 ti,syscon-efuse = <&main_conf 0x200>; 520 }; 521 522 cpsw_port2: port@2 { 523 reg = <2>; 524 ti,mac-only; 525 label = "port2"; 526 phys = <&phy_gmii_sel 2>; 527 mac-address = [00 00 00 00 00 00]; 528 }; 529 }; 530 531 cpsw3g_mdio: mdio@f00 { 532 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 533 reg = <0x0 0xf00 0x0 0x100>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&k3_clks 13 0>; 537 clock-names = "fck"; 538 bus_freq = <1000000>; 539 }; 540 541 cpts@3d000 { 542 compatible = "ti,j721e-cpts"; 543 reg = <0x0 0x3d000 0x0 0x400>; 544 clocks = <&k3_clks 13 1>; 545 clock-names = "cpts"; 546 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "cpts"; 548 ti,cpts-ext-ts-inputs = <4>; 549 ti,cpts-periodic-outputs = <2>; 550 }; 551 }; 552 553 cpts@39000000 { 554 compatible = "ti,j721e-cpts"; 555 reg = <0x0 0x39000000 0x0 0x400>; 556 reg-names = "cpts"; 557 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 558 clocks = <&k3_clks 84 0>; 559 clock-names = "cpts"; 560 assigned-clocks = <&k3_clks 84 0>; 561 assigned-clock-parents = <&k3_clks 84 8>; 562 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 563 interrupt-names = "cpts"; 564 ti,cpts-periodic-outputs = <6>; 565 ti,cpts-ext-ts-inputs = <8>; 566 }; 567 568 timesync_router: pinctrl@a40000 { 569 compatible = "pinctrl-single"; 570 reg = <0x0 0xa40000 0x0 0x800>; 571 #pinctrl-cells = <1>; 572 pinctrl-single,register-width = <32>; 573 pinctrl-single,function-mask = <0x000107ff>; 574 }; 575 576 usbss0: cdns-usb@f900000{ 577 compatible = "ti,am64-usb"; 578 reg = <0x00 0xf900000 0x00 0x100>; 579 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 580 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 581 clock-names = "ref", "lpm"; 582 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 583 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 584 #address-cells = <2>; 585 #size-cells = <2>; 586 ranges; 587 usb0: usb@f400000{ 588 compatible = "cdns,usb3"; 589 reg = <0x00 0xf400000 0x00 0x10000>, 590 <0x00 0xf410000 0x00 0x10000>, 591 <0x00 0xf420000 0x00 0x10000>; 592 reg-names = "otg", 593 "xhci", 594 "dev"; 595 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 596 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 597 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 598 interrupt-names = "host", 599 "peripheral", 600 "otg"; 601 maximum-speed = "super-speed"; 602 dr_mode = "otg"; 603 }; 604 }; 605 606 tscadc0: tscadc@28001000 { 607 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 608 reg = <0x00 0x28001000 0x00 0x1000>; 609 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 610 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 611 clocks = <&k3_clks 0 0>; 612 assigned-clocks = <&k3_clks 0 0>; 613 assigned-clock-parents = <&k3_clks 0 3>; 614 assigned-clock-rates = <60000000>; 615 clock-names = "adc_tsc_fck"; 616 617 adc { 618 #io-channel-cells = <1>; 619 compatible = "ti,am654-adc", "ti,am3359-adc"; 620 }; 621 }; 622 623 fss: bus@fc00000 { 624 compatible = "simple-bus"; 625 reg = <0x00 0x0fc00000 0x00 0x70000>; 626 #address-cells = <2>; 627 #size-cells = <2>; 628 ranges; 629 630 ospi0: spi@fc40000 { 631 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 632 reg = <0x00 0x0fc40000 0x00 0x100>, 633 <0x05 0x00000000 0x01 0x00000000>; 634 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 635 cdns,fifo-depth = <256>; 636 cdns,fifo-width = <4>; 637 cdns,trigger-address = <0x0>; 638 #address-cells = <0x1>; 639 #size-cells = <0x0>; 640 clocks = <&k3_clks 75 6>; 641 assigned-clocks = <&k3_clks 75 6>; 642 assigned-clock-parents = <&k3_clks 75 7>; 643 assigned-clock-rates = <166666666>; 644 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 645 }; 646 }; 647 648 hwspinlock: spinlock@2a000000 { 649 compatible = "ti,am64-hwspinlock"; 650 reg = <0x00 0x2a000000 0x00 0x1000>; 651 #hwlock-cells = <1>; 652 }; 653 654 mailbox0_cluster2: mailbox@29020000 { 655 compatible = "ti,am64-mailbox"; 656 reg = <0x00 0x29020000 0x00 0x200>; 657 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 659 #mbox-cells = <1>; 660 ti,mbox-num-users = <4>; 661 ti,mbox-num-fifos = <16>; 662 }; 663 664 mailbox0_cluster3: mailbox@29030000 { 665 compatible = "ti,am64-mailbox"; 666 reg = <0x00 0x29030000 0x00 0x200>; 667 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 669 #mbox-cells = <1>; 670 ti,mbox-num-users = <4>; 671 ti,mbox-num-fifos = <16>; 672 }; 673 674 mailbox0_cluster4: mailbox@29040000 { 675 compatible = "ti,am64-mailbox"; 676 reg = <0x00 0x29040000 0x00 0x200>; 677 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 679 #mbox-cells = <1>; 680 ti,mbox-num-users = <4>; 681 ti,mbox-num-fifos = <16>; 682 }; 683 684 mailbox0_cluster5: mailbox@29050000 { 685 compatible = "ti,am64-mailbox"; 686 reg = <0x00 0x29050000 0x00 0x200>; 687 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 689 #mbox-cells = <1>; 690 ti,mbox-num-users = <4>; 691 ti,mbox-num-fifos = <16>; 692 }; 693 694 mailbox0_cluster6: mailbox@29060000 { 695 compatible = "ti,am64-mailbox"; 696 reg = <0x00 0x29060000 0x00 0x200>; 697 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 698 #mbox-cells = <1>; 699 ti,mbox-num-users = <4>; 700 ti,mbox-num-fifos = <16>; 701 }; 702 703 mailbox0_cluster7: mailbox@29070000 { 704 compatible = "ti,am64-mailbox"; 705 reg = <0x00 0x29070000 0x00 0x200>; 706 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 707 #mbox-cells = <1>; 708 ti,mbox-num-users = <4>; 709 ti,mbox-num-fifos = <16>; 710 }; 711 712 main_r5fss0: r5fss@78000000 { 713 compatible = "ti,am64-r5fss"; 714 ti,cluster-mode = <0>; 715 #address-cells = <1>; 716 #size-cells = <1>; 717 ranges = <0x78000000 0x00 0x78000000 0x10000>, 718 <0x78100000 0x00 0x78100000 0x10000>, 719 <0x78200000 0x00 0x78200000 0x08000>, 720 <0x78300000 0x00 0x78300000 0x08000>; 721 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 722 723 main_r5fss0_core0: r5f@78000000 { 724 compatible = "ti,am64-r5f"; 725 reg = <0x78000000 0x00010000>, 726 <0x78100000 0x00010000>; 727 reg-names = "atcm", "btcm"; 728 ti,sci = <&dmsc>; 729 ti,sci-dev-id = <121>; 730 ti,sci-proc-ids = <0x01 0xff>; 731 resets = <&k3_reset 121 1>; 732 firmware-name = "am64-main-r5f0_0-fw"; 733 ti,atcm-enable = <1>; 734 ti,btcm-enable = <1>; 735 ti,loczrama = <1>; 736 }; 737 738 main_r5fss0_core1: r5f@78200000 { 739 compatible = "ti,am64-r5f"; 740 reg = <0x78200000 0x00008000>, 741 <0x78300000 0x00008000>; 742 reg-names = "atcm", "btcm"; 743 ti,sci = <&dmsc>; 744 ti,sci-dev-id = <122>; 745 ti,sci-proc-ids = <0x02 0xff>; 746 resets = <&k3_reset 122 1>; 747 firmware-name = "am64-main-r5f0_1-fw"; 748 ti,atcm-enable = <1>; 749 ti,btcm-enable = <1>; 750 ti,loczrama = <1>; 751 }; 752 }; 753 754 main_r5fss1: r5fss@78400000 { 755 compatible = "ti,am64-r5fss"; 756 ti,cluster-mode = <0>; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 ranges = <0x78400000 0x00 0x78400000 0x10000>, 760 <0x78500000 0x00 0x78500000 0x10000>, 761 <0x78600000 0x00 0x78600000 0x08000>, 762 <0x78700000 0x00 0x78700000 0x08000>; 763 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 764 765 main_r5fss1_core0: r5f@78400000 { 766 compatible = "ti,am64-r5f"; 767 reg = <0x78400000 0x00010000>, 768 <0x78500000 0x00010000>; 769 reg-names = "atcm", "btcm"; 770 ti,sci = <&dmsc>; 771 ti,sci-dev-id = <123>; 772 ti,sci-proc-ids = <0x06 0xff>; 773 resets = <&k3_reset 123 1>; 774 firmware-name = "am64-main-r5f1_0-fw"; 775 ti,atcm-enable = <1>; 776 ti,btcm-enable = <1>; 777 ti,loczrama = <1>; 778 }; 779 780 main_r5fss1_core1: r5f@78600000 { 781 compatible = "ti,am64-r5f"; 782 reg = <0x78600000 0x00008000>, 783 <0x78700000 0x00008000>; 784 reg-names = "atcm", "btcm"; 785 ti,sci = <&dmsc>; 786 ti,sci-dev-id = <124>; 787 ti,sci-proc-ids = <0x07 0xff>; 788 resets = <&k3_reset 124 1>; 789 firmware-name = "am64-main-r5f1_1-fw"; 790 ti,atcm-enable = <1>; 791 ti,btcm-enable = <1>; 792 ti,loczrama = <1>; 793 }; 794 }; 795 796 serdes_wiz0: wiz@f000000 { 797 compatible = "ti,am64-wiz-10g"; 798 #address-cells = <1>; 799 #size-cells = <1>; 800 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 801 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 802 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 803 num-lanes = <1>; 804 #reset-cells = <1>; 805 #clock-cells = <1>; 806 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 807 808 assigned-clocks = <&k3_clks 162 1>; 809 assigned-clock-parents = <&k3_clks 162 5>; 810 811 serdes0: serdes@f000000 { 812 compatible = "ti,j721e-serdes-10g"; 813 reg = <0x0f000000 0x00010000>; 814 reg-names = "torrent_phy"; 815 resets = <&serdes_wiz0 0>; 816 reset-names = "torrent_reset"; 817 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 818 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 819 clock-names = "refclk", "phy_en_refclk"; 820 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 821 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 822 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 823 assigned-clock-parents = <&k3_clks 162 1>, 824 <&k3_clks 162 1>, 825 <&k3_clks 162 1>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 #clock-cells = <1>; 829 }; 830 }; 831 832 pcie0_rc: pcie@f102000 { 833 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 834 reg = <0x00 0x0f102000 0x00 0x1000>, 835 <0x00 0x0f100000 0x00 0x400>, 836 <0x00 0x0d000000 0x00 0x00800000>, 837 <0x00 0x68000000 0x00 0x00001000>; 838 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 839 interrupt-names = "link_state"; 840 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 841 device_type = "pci"; 842 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 843 max-link-speed = <2>; 844 num-lanes = <1>; 845 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 846 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 847 clock-names = "fck", "pcie_refclk"; 848 #address-cells = <3>; 849 #size-cells = <2>; 850 bus-range = <0x0 0xff>; 851 cdns,no-bar-match-nbits = <64>; 852 vendor-id = <0x104c>; 853 device-id = <0xb010>; 854 msi-map = <0x0 &gic_its 0x0 0x10000>; 855 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 856 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 857 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 858 }; 859 860 pcie0_ep: pcie-ep@f102000 { 861 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 862 reg = <0x00 0x0f102000 0x00 0x1000>, 863 <0x00 0x0f100000 0x00 0x400>, 864 <0x00 0x0d000000 0x00 0x00800000>, 865 <0x00 0x68000000 0x00 0x08000000>; 866 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 867 interrupt-names = "link_state"; 868 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 869 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 870 max-link-speed = <2>; 871 num-lanes = <1>; 872 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 873 clocks = <&k3_clks 114 0>; 874 clock-names = "fck"; 875 max-functions = /bits/ 8 <1>; 876 }; 877 878 epwm0: pwm@23000000 { 879 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 880 #pwm-cells = <3>; 881 reg = <0x0 0x23000000 0x0 0x100>; 882 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 883 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 884 clock-names = "tbclk", "fck"; 885 }; 886 887 epwm1: pwm@23010000 { 888 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 889 #pwm-cells = <3>; 890 reg = <0x0 0x23010000 0x0 0x100>; 891 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 892 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 893 clock-names = "tbclk", "fck"; 894 }; 895 896 epwm2: pwm@23020000 { 897 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 898 #pwm-cells = <3>; 899 reg = <0x0 0x23020000 0x0 0x100>; 900 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 901 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 902 clock-names = "tbclk", "fck"; 903 }; 904 905 epwm3: pwm@23030000 { 906 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 907 #pwm-cells = <3>; 908 reg = <0x0 0x23030000 0x0 0x100>; 909 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 911 clock-names = "tbclk", "fck"; 912 }; 913 914 epwm4: pwm@23040000 { 915 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 916 #pwm-cells = <3>; 917 reg = <0x0 0x23040000 0x0 0x100>; 918 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 919 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 920 clock-names = "tbclk", "fck"; 921 }; 922 923 epwm5: pwm@23050000 { 924 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 925 #pwm-cells = <3>; 926 reg = <0x0 0x23050000 0x0 0x100>; 927 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 928 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 929 clock-names = "tbclk", "fck"; 930 }; 931 932 epwm6: pwm@23060000 { 933 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 934 #pwm-cells = <3>; 935 reg = <0x0 0x23060000 0x0 0x100>; 936 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 937 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 938 clock-names = "tbclk", "fck"; 939 }; 940 941 epwm7: pwm@23070000 { 942 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 943 #pwm-cells = <3>; 944 reg = <0x0 0x23070000 0x0 0x100>; 945 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 946 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 947 clock-names = "tbclk", "fck"; 948 }; 949 950 epwm8: pwm@23080000 { 951 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 952 #pwm-cells = <3>; 953 reg = <0x0 0x23080000 0x0 0x100>; 954 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 955 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 956 clock-names = "tbclk", "fck"; 957 }; 958 959 ecap0: pwm@23100000 { 960 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 961 #pwm-cells = <3>; 962 reg = <0x0 0x23100000 0x0 0x60>; 963 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 964 clocks = <&k3_clks 51 0>; 965 clock-names = "fck"; 966 }; 967 968 ecap1: pwm@23110000 { 969 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 970 #pwm-cells = <3>; 971 reg = <0x0 0x23110000 0x0 0x60>; 972 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 973 clocks = <&k3_clks 52 0>; 974 clock-names = "fck"; 975 }; 976 977 ecap2: pwm@23120000 { 978 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 979 #pwm-cells = <3>; 980 reg = <0x0 0x23120000 0x0 0x60>; 981 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 982 clocks = <&k3_clks 53 0>; 983 clock-names = "fck"; 984 }; 985 986 main_rti0: watchdog@e000000 { 987 compatible = "ti,j7-rti-wdt"; 988 reg = <0x00 0xe000000 0x00 0x100>; 989 clocks = <&k3_clks 125 0>; 990 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 991 assigned-clocks = <&k3_clks 125 0>; 992 assigned-clock-parents = <&k3_clks 125 2>; 993 }; 994 995 main_rti1: watchdog@e010000 { 996 compatible = "ti,j7-rti-wdt"; 997 reg = <0x00 0xe010000 0x00 0x100>; 998 clocks = <&k3_clks 126 0>; 999 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1000 assigned-clocks = <&k3_clks 126 0>; 1001 assigned-clock-parents = <&k3_clks 126 2>; 1002 }; 1003 1004 icssg0: icssg@30000000 { 1005 compatible = "ti,am642-icssg"; 1006 reg = <0x00 0x30000000 0x00 0x80000>; 1007 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 ranges = <0x0 0x00 0x30000000 0x80000>; 1011 1012 icssg0_mem: memories@0 { 1013 reg = <0x0 0x2000>, 1014 <0x2000 0x2000>, 1015 <0x10000 0x10000>; 1016 reg-names = "dram0", "dram1", "shrdram2"; 1017 }; 1018 1019 icssg0_cfg: cfg@26000 { 1020 compatible = "ti,pruss-cfg", "syscon"; 1021 reg = <0x26000 0x200>; 1022 #address-cells = <1>; 1023 #size-cells = <1>; 1024 ranges = <0x0 0x26000 0x2000>; 1025 1026 clocks { 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 1030 icssg0_coreclk_mux: coreclk-mux@3c { 1031 reg = <0x3c>; 1032 #clock-cells = <0>; 1033 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1034 <&k3_clks 81 20>; /* icssg0_iclk */ 1035 assigned-clocks = <&icssg0_coreclk_mux>; 1036 assigned-clock-parents = <&k3_clks 81 20>; 1037 }; 1038 1039 icssg0_iepclk_mux: iepclk-mux@30 { 1040 reg = <0x30>; 1041 #clock-cells = <0>; 1042 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1043 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1044 assigned-clocks = <&icssg0_iepclk_mux>; 1045 assigned-clock-parents = <&icssg0_coreclk_mux>; 1046 }; 1047 }; 1048 }; 1049 1050 icssg0_mii_rt: mii-rt@32000 { 1051 compatible = "ti,pruss-mii", "syscon"; 1052 reg = <0x32000 0x100>; 1053 }; 1054 1055 icssg0_mii_g_rt: mii-g-rt@33000 { 1056 compatible = "ti,pruss-mii-g", "syscon"; 1057 reg = <0x33000 0x1000>; 1058 }; 1059 1060 icssg0_intc: interrupt-controller@20000 { 1061 compatible = "ti,icssg-intc"; 1062 reg = <0x20000 0x2000>; 1063 interrupt-controller; 1064 #interrupt-cells = <3>; 1065 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "host_intr0", "host_intr1", 1074 "host_intr2", "host_intr3", 1075 "host_intr4", "host_intr5", 1076 "host_intr6", "host_intr7"; 1077 }; 1078 1079 pru0_0: pru@34000 { 1080 compatible = "ti,am642-pru"; 1081 reg = <0x34000 0x3000>, 1082 <0x22000 0x100>, 1083 <0x22400 0x100>; 1084 reg-names = "iram", "control", "debug"; 1085 firmware-name = "am64x-pru0_0-fw"; 1086 }; 1087 1088 rtu0_0: rtu@4000 { 1089 compatible = "ti,am642-rtu"; 1090 reg = <0x4000 0x2000>, 1091 <0x23000 0x100>, 1092 <0x23400 0x100>; 1093 reg-names = "iram", "control", "debug"; 1094 firmware-name = "am64x-rtu0_0-fw"; 1095 }; 1096 1097 tx_pru0_0: txpru@a000 { 1098 compatible = "ti,am642-tx-pru"; 1099 reg = <0xa000 0x1800>, 1100 <0x25000 0x100>, 1101 <0x25400 0x100>; 1102 reg-names = "iram", "control", "debug"; 1103 firmware-name = "am64x-txpru0_0-fw"; 1104 }; 1105 1106 pru0_1: pru@38000 { 1107 compatible = "ti,am642-pru"; 1108 reg = <0x38000 0x3000>, 1109 <0x24000 0x100>, 1110 <0x24400 0x100>; 1111 reg-names = "iram", "control", "debug"; 1112 firmware-name = "am64x-pru0_1-fw"; 1113 }; 1114 1115 rtu0_1: rtu@6000 { 1116 compatible = "ti,am642-rtu"; 1117 reg = <0x6000 0x2000>, 1118 <0x23800 0x100>, 1119 <0x23c00 0x100>; 1120 reg-names = "iram", "control", "debug"; 1121 firmware-name = "am64x-rtu0_1-fw"; 1122 }; 1123 1124 tx_pru0_1: txpru@c000 { 1125 compatible = "ti,am642-tx-pru"; 1126 reg = <0xc000 0x1800>, 1127 <0x25800 0x100>, 1128 <0x25c00 0x100>; 1129 reg-names = "iram", "control", "debug"; 1130 firmware-name = "am64x-txpru0_1-fw"; 1131 }; 1132 1133 icssg0_mdio: mdio@32400 { 1134 compatible = "ti,davinci_mdio"; 1135 reg = <0x32400 0x100>; 1136 clocks = <&k3_clks 62 3>; 1137 clock-names = "fck"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 bus_freq = <1000000>; 1141 }; 1142 }; 1143 1144 icssg1: icssg@30080000 { 1145 compatible = "ti,am642-icssg"; 1146 reg = <0x00 0x30080000 0x00 0x80000>; 1147 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1148 #address-cells = <1>; 1149 #size-cells = <1>; 1150 ranges = <0x0 0x00 0x30080000 0x80000>; 1151 1152 icssg1_mem: memories@0 { 1153 reg = <0x0 0x2000>, 1154 <0x2000 0x2000>, 1155 <0x10000 0x10000>; 1156 reg-names = "dram0", "dram1", "shrdram2"; 1157 }; 1158 1159 icssg1_cfg: cfg@26000 { 1160 compatible = "ti,pruss-cfg", "syscon"; 1161 reg = <0x26000 0x200>; 1162 #address-cells = <1>; 1163 #size-cells = <1>; 1164 ranges = <0x0 0x26000 0x2000>; 1165 1166 clocks { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 1170 icssg1_coreclk_mux: coreclk-mux@3c { 1171 reg = <0x3c>; 1172 #clock-cells = <0>; 1173 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1174 <&k3_clks 82 20>; /* icssg1_iclk */ 1175 assigned-clocks = <&icssg1_coreclk_mux>; 1176 assigned-clock-parents = <&k3_clks 82 20>; 1177 }; 1178 1179 icssg1_iepclk_mux: iepclk-mux@30 { 1180 reg = <0x30>; 1181 #clock-cells = <0>; 1182 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1183 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1184 assigned-clocks = <&icssg1_iepclk_mux>; 1185 assigned-clock-parents = <&icssg1_coreclk_mux>; 1186 }; 1187 }; 1188 }; 1189 1190 icssg1_mii_rt: mii-rt@32000 { 1191 compatible = "ti,pruss-mii", "syscon"; 1192 reg = <0x32000 0x100>; 1193 }; 1194 1195 icssg1_mii_g_rt: mii-g-rt@33000 { 1196 compatible = "ti,pruss-mii-g", "syscon"; 1197 reg = <0x33000 0x1000>; 1198 }; 1199 1200 icssg1_intc: interrupt-controller@20000 { 1201 compatible = "ti,icssg-intc"; 1202 reg = <0x20000 0x2000>; 1203 interrupt-controller; 1204 #interrupt-cells = <3>; 1205 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1213 interrupt-names = "host_intr0", "host_intr1", 1214 "host_intr2", "host_intr3", 1215 "host_intr4", "host_intr5", 1216 "host_intr6", "host_intr7"; 1217 }; 1218 1219 pru1_0: pru@34000 { 1220 compatible = "ti,am642-pru"; 1221 reg = <0x34000 0x4000>, 1222 <0x22000 0x100>, 1223 <0x22400 0x100>; 1224 reg-names = "iram", "control", "debug"; 1225 firmware-name = "am64x-pru1_0-fw"; 1226 }; 1227 1228 rtu1_0: rtu@4000 { 1229 compatible = "ti,am642-rtu"; 1230 reg = <0x4000 0x2000>, 1231 <0x23000 0x100>, 1232 <0x23400 0x100>; 1233 reg-names = "iram", "control", "debug"; 1234 firmware-name = "am64x-rtu1_0-fw"; 1235 }; 1236 1237 tx_pru1_0: txpru@a000 { 1238 compatible = "ti,am642-tx-pru"; 1239 reg = <0xa000 0x1800>, 1240 <0x25000 0x100>, 1241 <0x25400 0x100>; 1242 reg-names = "iram", "control", "debug"; 1243 firmware-name = "am64x-txpru1_0-fw"; 1244 }; 1245 1246 pru1_1: pru@38000 { 1247 compatible = "ti,am642-pru"; 1248 reg = <0x38000 0x4000>, 1249 <0x24000 0x100>, 1250 <0x24400 0x100>; 1251 reg-names = "iram", "control", "debug"; 1252 firmware-name = "am64x-pru1_1-fw"; 1253 }; 1254 1255 rtu1_1: rtu@6000 { 1256 compatible = "ti,am642-rtu"; 1257 reg = <0x6000 0x2000>, 1258 <0x23800 0x100>, 1259 <0x23c00 0x100>; 1260 reg-names = "iram", "control", "debug"; 1261 firmware-name = "am64x-rtu1_1-fw"; 1262 }; 1263 1264 tx_pru1_1: txpru@c000 { 1265 compatible = "ti,am642-tx-pru"; 1266 reg = <0xc000 0x1800>, 1267 <0x25800 0x100>, 1268 <0x25c00 0x100>; 1269 reg-names = "iram", "control", "debug"; 1270 firmware-name = "am64x-txpru1_1-fw"; 1271 }; 1272 1273 icssg1_mdio: mdio@32400 { 1274 compatible = "ti,davinci_mdio"; 1275 reg = <0x32400 0x100>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 clocks = <&k3_clks 82 0>; 1279 clock-names = "fck"; 1280 bus_freq = <1000000>; 1281 }; 1282 }; 1283 1284 main_mcan0: can@20701000 { 1285 compatible = "bosch,m_can"; 1286 reg = <0x00 0x20701000 0x00 0x200>, 1287 <0x00 0x20708000 0x00 0x8000>; 1288 reg-names = "m_can", "message_ram"; 1289 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1290 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1291 clock-names = "hclk", "cclk"; 1292 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1294 interrupt-names = "int0", "int1"; 1295 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1296 }; 1297 1298 main_mcan1: can@20711000 { 1299 compatible = "bosch,m_can"; 1300 reg = <0x00 0x20711000 0x00 0x200>, 1301 <0x00 0x20718000 0x00 0x8000>; 1302 reg-names = "m_can", "message_ram"; 1303 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1304 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1305 clock-names = "hclk", "cclk"; 1306 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1308 interrupt-names = "int0", "int1"; 1309 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1310 }; 1311 };
Cache object: 475625aaa8f4e058410bf51d0828b5fb
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