k3-am642-evm.dts

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
    4  */
    5 
    6 /dts-v1/;
    7 
    8 #include <dt-bindings/phy/phy.h>
    9 #include <dt-bindings/mux/ti-serdes.h>
   10 #include <dt-bindings/leds/common.h>
   11 #include <dt-bindings/gpio/gpio.h>
   12 #include <dt-bindings/net/ti-dp83867.h>
   13 #include "k3-am642.dtsi"
   14 
   15 / {
   16         compatible = "ti,am642-evm", "ti,am642";
   17         model = "Texas Instruments AM642 EVM";
   18 
   19         chosen {
   20                 stdout-path = "serial2:115200n8";
   21                 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
   22         };
   23 
   24         memory@80000000 {
   25                 device_type = "memory";
   26                 /* 2G RAM */
   27                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
   28 
   29         };
   30 
   31         reserved-memory {
   32                 #address-cells = <2>;
   33                 #size-cells = <2>;
   34                 ranges;
   35 
   36                 secure_ddr: optee@9e800000 {
   37                         reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
   38                         alignment = <0x1000>;
   39                         no-map;
   40                 };
   41 
   42                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
   43                         compatible = "shared-dma-pool";
   44                         reg = <0x00 0xa0000000 0x00 0x100000>;
   45                         no-map;
   46                 };
   47 
   48                 main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
   49                         compatible = "shared-dma-pool";
   50                         reg = <0x00 0xa0100000 0x00 0xf00000>;
   51                         no-map;
   52                 };
   53 
   54                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
   55                         compatible = "shared-dma-pool";
   56                         reg = <0x00 0xa1000000 0x00 0x100000>;
   57                         no-map;
   58                 };
   59 
   60                 main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
   61                         compatible = "shared-dma-pool";
   62                         reg = <0x00 0xa1100000 0x00 0xf00000>;
   63                         no-map;
   64                 };
   65 
   66                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
   67                         compatible = "shared-dma-pool";
   68                         reg = <0x00 0xa2000000 0x00 0x100000>;
   69                         no-map;
   70                 };
   71 
   72                 main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
   73                         compatible = "shared-dma-pool";
   74                         reg = <0x00 0xa2100000 0x00 0xf00000>;
   75                         no-map;
   76                 };
   77 
   78                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
   79                         compatible = "shared-dma-pool";
   80                         reg = <0x00 0xa3000000 0x00 0x100000>;
   81                         no-map;
   82                 };
   83 
   84                 main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
   85                         compatible = "shared-dma-pool";
   86                         reg = <0x00 0xa3100000 0x00 0xf00000>;
   87                         no-map;
   88                 };
   89 
   90                 rtos_ipc_memory_region: ipc-memories@a5000000 {
   91                         reg = <0x00 0xa5000000 0x00 0x00800000>;
   92                         alignment = <0x1000>;
   93                         no-map;
   94                 };
   95         };
   96 
   97         evm_12v0: fixedregulator-evm12v0 {
   98                 /* main DC jack */
   99                 compatible = "regulator-fixed";
  100                 regulator-name = "evm_12v0";
  101                 regulator-min-microvolt = <12000000>;
  102                 regulator-max-microvolt = <12000000>;
  103                 regulator-always-on;
  104                 regulator-boot-on;
  105         };
  106 
  107         vsys_5v0: fixedregulator-vsys5v0 {
  108                 /* output of LM5140 */
  109                 compatible = "regulator-fixed";
  110                 regulator-name = "vsys_5v0";
  111                 regulator-min-microvolt = <5000000>;
  112                 regulator-max-microvolt = <5000000>;
  113                 vin-supply = <&evm_12v0>;
  114                 regulator-always-on;
  115                 regulator-boot-on;
  116         };
  117 
  118         vsys_3v3: fixedregulator-vsys3v3 {
  119                 /* output of LM5140 */
  120                 compatible = "regulator-fixed";
  121                 regulator-name = "vsys_3v3";
  122                 regulator-min-microvolt = <3300000>;
  123                 regulator-max-microvolt = <3300000>;
  124                 vin-supply = <&evm_12v0>;
  125                 regulator-always-on;
  126                 regulator-boot-on;
  127         };
  128 
  129         vdd_mmc1: fixed-regulator-sd {
  130                 /* TPS2051BD */
  131                 compatible = "regulator-fixed";
  132                 regulator-name = "vdd_mmc1";
  133                 regulator-min-microvolt = <3300000>;
  134                 regulator-max-microvolt = <3300000>;
  135                 regulator-boot-on;
  136                 enable-active-high;
  137                 vin-supply = <&vsys_3v3>;
  138                 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
  139         };
  140 
  141         vddb: fixedregulator-vddb {
  142                 compatible = "regulator-fixed";
  143                 regulator-name = "vddb_3v3_display";
  144                 regulator-min-microvolt = <3300000>;
  145                 regulator-max-microvolt = <3300000>;
  146                 vin-supply = <&vsys_3v3>;
  147                 regulator-always-on;
  148                 regulator-boot-on;
  149         };
  150 
  151         leds {
  152                 compatible = "gpio-leds";
  153 
  154                 led-0 {
  155                         label = "am64-evm:red:heartbeat";
  156                         gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
  157                         linux,default-trigger = "heartbeat";
  158                         function = LED_FUNCTION_HEARTBEAT;
  159                         default-state = "off";
  160                 };
  161         };
  162 
  163         mdio_mux: mux-controller {
  164                 compatible = "gpio-mux";
  165                 #mux-control-cells = <0>;
  166 
  167                 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
  168         };
  169 
  170         mdio-mux-1 {
  171                 compatible = "mdio-mux-multiplexer";
  172                 mux-controls = <&mdio_mux>;
  173                 mdio-parent-bus = <&cpsw3g_mdio>;
  174                 #address-cells = <1>;
  175                 #size-cells = <0>;
  176 
  177                 mdio@1 {
  178                         reg = <0x1>;
  179                         #address-cells = <1>;
  180                         #size-cells = <0>;
  181 
  182                         cpsw3g_phy3: ethernet-phy@3 {
  183                                 reg = <3>;
  184                         };
  185                 };
  186         };
  187 
  188         transceiver1: can-phy0 {
  189                 compatible = "ti,tcan1042";
  190                 #phy-cells = <0>;
  191                 max-bitrate = <5000000>;
  192                 standby-gpios = <&exp1 8 GPIO_ACTIVE_HIGH>;
  193         };
  194 
  195         transceiver2: can-phy1 {
  196                 compatible = "ti,tcan1042";
  197                 #phy-cells = <0>;
  198                 max-bitrate = <5000000>;
  199                 standby-gpios = <&exp1 9 GPIO_ACTIVE_HIGH>;
  200         };
  201 };
  202 
  203 &main_pmx0 {
  204         main_mmc1_pins_default: main-mmc1-pins-default {
  205                 pinctrl-single,pins = <
  206                         AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
  207                         AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
  208                         AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
  209                         AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
  210                         AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
  211                         AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
  212                         AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
  213                         AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
  214                         AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
  215                 >;
  216         };
  217 
  218         main_uart0_pins_default: main-uart0-pins-default {
  219                 pinctrl-single,pins = <
  220                         AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
  221                         AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
  222                         AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
  223                         AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
  224                 >;
  225         };
  226 
  227         main_spi0_pins_default: main-spi0-pins-default {
  228                 pinctrl-single,pins = <
  229                         AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */
  230                         AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */
  231                         AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */
  232                         AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */
  233                 >;
  234         };
  235 
  236         main_i2c1_pins_default: main-i2c1-pins-default {
  237                 pinctrl-single,pins = <
  238                         AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
  239                         AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
  240                 >;
  241         };
  242 
  243         mdio1_pins_default: mdio1-pins-default {
  244                 pinctrl-single,pins = <
  245                         AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
  246                         AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
  247                 >;
  248         };
  249 
  250         rgmii1_pins_default: rgmii1-pins-default {
  251                 pinctrl-single,pins = <
  252                         AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
  253                         AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
  254                         AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
  255                         AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
  256                         AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
  257                         AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
  258                         AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
  259                         AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
  260                         AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
  261                         AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
  262                         AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
  263                         AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
  264                 >;
  265         };
  266 
  267        rgmii2_pins_default: rgmii2-pins-default {
  268                 pinctrl-single,pins = <
  269                         AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
  270                         AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
  271                         AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
  272                         AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
  273                         AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
  274                         AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
  275                         AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
  276                         AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
  277                         AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
  278                         AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
  279                         AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
  280                         AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
  281                 >;
  282         };
  283 
  284         main_usb0_pins_default: main-usb0-pins-default {
  285                 pinctrl-single,pins = <
  286                         AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
  287                 >;
  288         };
  289 
  290         ospi0_pins_default: ospi0-pins-default {
  291                 pinctrl-single,pins = <
  292                         AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
  293                         AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
  294                         AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
  295                         AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
  296                         AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
  297                         AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
  298                         AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
  299                         AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
  300                         AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
  301                         AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
  302                         AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
  303                 >;
  304         };
  305 
  306         main_ecap0_pins_default: main-ecap0-pins-default {
  307                 pinctrl-single,pins = <
  308                         AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
  309                 >;
  310         };
  311 
  312         main_mcan0_pins_default: main-mcan0-pins-default {
  313                 pinctrl-single,pins = <
  314                         AM64X_IOPAD(0x0254, PIN_INPUT, 0) /* (B17) MCAN0_RX */
  315                         AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) /* (A17) MCAN0_TX */
  316                 >;
  317         };
  318 
  319         main_mcan1_pins_default: main-mcan1-pins-default {
  320                 pinctrl-single,pins = <
  321                         AM64X_IOPAD(0x025c, PIN_INPUT, 0) /* (D17) MCAN1_RX */
  322                         AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */
  323                 >;
  324         };
  325 };
  326 
  327 &main_uart0 {
  328         pinctrl-names = "default";
  329         pinctrl-0 = <&main_uart0_pins_default>;
  330 };
  331 
  332 /* main_uart1 is reserved for firmware usage */
  333 &main_uart1 {
  334         status = "reserved";
  335 };
  336 
  337 &main_uart2 {
  338         status = "disabled";
  339 };
  340 
  341 &main_uart3 {
  342         status = "disabled";
  343 };
  344 
  345 &main_uart4 {
  346         status = "disabled";
  347 };
  348 
  349 &main_uart5 {
  350         status = "disabled";
  351 };
  352 
  353 &main_uart6 {
  354         status = "disabled";
  355 };
  356 
  357 &mcu_uart0 {
  358         status = "disabled";
  359 };
  360 
  361 &mcu_uart1 {
  362         status = "disabled";
  363 };
  364 
  365 &main_i2c1 {
  366         pinctrl-names = "default";
  367         pinctrl-0 = <&main_i2c1_pins_default>;
  368         clock-frequency = <400000>;
  369 
  370         exp1: gpio@22 {
  371                 compatible = "ti,tca6424";
  372                 reg = <0x22>;
  373                 gpio-controller;
  374                 #gpio-cells = <2>;
  375                 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
  376                                   "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
  377                                   "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
  378                                   "MMC1_SD_EN", "FSI_FET_SEL",
  379                                   "MCAN0_STB_3V3", "MCAN1_STB_3V3",
  380                                   "CPSW_FET_SEL", "CPSW_FET2_SEL",
  381                                   "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
  382                                   "GPIO_OLED_RESETn", "VPP_LDO_EN",
  383                                   "TEST_LED1", "TP92", "TP90", "TP88",
  384                                   "TP87", "TP86", "TP89", "TP91";
  385         };
  386 
  387         /* osd9616p0899-10 */
  388         display@3c {
  389                 compatible = "solomon,ssd1306fb-i2c";
  390                 reg = <0x3c>;
  391                 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
  392                 vbat-supply = <&vddb>;
  393                 solomon,height = <16>;
  394                 solomon,width = <96>;
  395                 solomon,com-seq;
  396                 solomon,com-invdir;
  397                 solomon,page-offset = <0>;
  398                 solomon,prechargep1 = <2>;
  399                 solomon,prechargep2 = <13>;
  400         };
  401 };
  402 
  403 /* mcu_gpio0 is reserved for mcu firmware usage */
  404 &mcu_gpio0 {
  405         status = "reserved";
  406 };
  407 
  408 &mcu_i2c0 {
  409         status = "disabled";
  410 };
  411 
  412 &mcu_i2c1 {
  413         status = "disabled";
  414 };
  415 
  416 &mcu_spi0 {
  417         status = "disabled";
  418 };
  419 
  420 &mcu_spi1 {
  421         status = "disabled";
  422 };
  423 
  424 &main_spi0 {
  425         pinctrl-names = "default";
  426         pinctrl-0 = <&main_spi0_pins_default>;
  427         ti,pindir-d0-out-d1-in;
  428         eeprom@0 {
  429                 compatible = "microchip,93lc46b";
  430                 reg = <0>;
  431                 spi-max-frequency = <1000000>;
  432                 spi-cs-high;
  433                 data-size = <16>;
  434         };
  435 };
  436 
  437 &sdhci0 {
  438         /* emmc */
  439         bus-width = <8>;
  440         non-removable;
  441         ti,driver-strength-ohm = <50>;
  442         disable-wp;
  443 };
  444 
  445 &sdhci1 {
  446         /* SD/MMC */
  447         vmmc-supply = <&vdd_mmc1>;
  448         pinctrl-names = "default";
  449         bus-width = <4>;
  450         pinctrl-0 = <&main_mmc1_pins_default>;
  451         ti,driver-strength-ohm = <50>;
  452         disable-wp;
  453 };
  454 
  455 &usbss0 {
  456         ti,vbus-divider;
  457         ti,usb2-only;
  458 };
  459 
  460 &usb0 {
  461         dr_mode = "otg";
  462         maximum-speed = "high-speed";
  463         pinctrl-names = "default";
  464         pinctrl-0 = <&main_usb0_pins_default>;
  465 };
  466 
  467 &cpsw3g {
  468         pinctrl-names = "default";
  469         pinctrl-0 = <&mdio1_pins_default
  470                      &rgmii1_pins_default
  471                      &rgmii2_pins_default>;
  472 };
  473 
  474 &cpsw_port1 {
  475         phy-mode = "rgmii-rxid";
  476         phy-handle = <&cpsw3g_phy0>;
  477 };
  478 
  479 &cpsw_port2 {
  480         phy-mode = "rgmii-rxid";
  481         phy-handle = <&cpsw3g_phy3>;
  482 };
  483 
  484 &cpsw3g_mdio {
  485         cpsw3g_phy0: ethernet-phy@0 {
  486                 reg = <0>;
  487                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  488                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  489         };
  490 };
  491 
  492 &tscadc0 {
  493         /* ADC is reserved for R5 usage */
  494         status = "reserved";
  495 };
  496 
  497 &ospi0 {
  498         pinctrl-names = "default";
  499         pinctrl-0 = <&ospi0_pins_default>;
  500 
  501         flash@0 {
  502                 compatible = "jedec,spi-nor";
  503                 reg = <0x0>;
  504                 spi-tx-bus-width = <8>;
  505                 spi-rx-bus-width = <8>;
  506                 spi-max-frequency = <25000000>;
  507                 cdns,tshsl-ns = <60>;
  508                 cdns,tsd2d-ns = <60>;
  509                 cdns,tchsh-ns = <60>;
  510                 cdns,tslch-ns = <60>;
  511                 cdns,read-delay = <4>;
  512         };
  513 };
  514 
  515 &mailbox0_cluster2 {
  516         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
  517                 ti,mbox-rx = <0 0 2>;
  518                 ti,mbox-tx = <1 0 2>;
  519         };
  520 
  521         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
  522                 ti,mbox-rx = <2 0 2>;
  523                 ti,mbox-tx = <3 0 2>;
  524         };
  525 };
  526 
  527 &mailbox0_cluster3 {
  528         status = "disabled";
  529 };
  530 
  531 &mailbox0_cluster4 {
  532         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
  533                 ti,mbox-rx = <0 0 2>;
  534                 ti,mbox-tx = <1 0 2>;
  535         };
  536 
  537         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
  538                 ti,mbox-rx = <2 0 2>;
  539                 ti,mbox-tx = <3 0 2>;
  540         };
  541 };
  542 
  543 &mailbox0_cluster5 {
  544         status = "disabled";
  545 };
  546 
  547 &mailbox0_cluster6 {
  548         mbox_m4_0: mbox-m4-0 {
  549                 ti,mbox-rx = <0 0 2>;
  550                 ti,mbox-tx = <1 0 2>;
  551         };
  552 };
  553 
  554 &mailbox0_cluster7 {
  555         status = "disabled";
  556 };
  557 
  558 &main_r5fss0_core0 {
  559         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
  560         memory-region = <&main_r5fss0_core0_dma_memory_region>,
  561                         <&main_r5fss0_core0_memory_region>;
  562 };
  563 
  564 &main_r5fss0_core1 {
  565         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
  566         memory-region = <&main_r5fss0_core1_dma_memory_region>,
  567                         <&main_r5fss0_core1_memory_region>;
  568 };
  569 
  570 &main_r5fss1_core0 {
  571         mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
  572         memory-region = <&main_r5fss1_core0_dma_memory_region>,
  573                         <&main_r5fss1_core0_memory_region>;
  574 };
  575 
  576 &main_r5fss1_core1 {
  577         mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
  578         memory-region = <&main_r5fss1_core1_dma_memory_region>,
  579                         <&main_r5fss1_core1_memory_region>;
  580 };
  581 
  582 &serdes_ln_ctrl {
  583         idle-states = <AM64_SERDES0_LANE0_PCIE0>;
  584 };
  585 
  586 &serdes0 {
  587         serdes0_pcie_link: phy@0 {
  588                 reg = <0>;
  589                 cdns,num-lanes = <1>;
  590                 #phy-cells = <0>;
  591                 cdns,phy-type = <PHY_TYPE_PCIE>;
  592                 resets = <&serdes_wiz0 1>;
  593         };
  594 };
  595 
  596 &pcie0_rc {
  597         reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
  598         phys = <&serdes0_pcie_link>;
  599         phy-names = "pcie-phy";
  600         num-lanes = <1>;
  601 };
  602 
  603 &pcie0_ep {
  604         phys = <&serdes0_pcie_link>;
  605         phy-names = "pcie-phy";
  606         num-lanes = <1>;
  607         status = "disabled";
  608 };
  609 
  610 &ecap0 {
  611         /* PWM is available on Pin 1 of header J12 */
  612         pinctrl-names = "default";
  613         pinctrl-0 = <&main_ecap0_pins_default>;
  614 };
  615 
  616 &ecap1 {
  617         status = "disabled";
  618 };
  619 
  620 &ecap2 {
  621         status = "disabled";
  622 };
  623 
  624 &epwm0 {
  625         status = "disabled";
  626 };
  627 
  628 &epwm1 {
  629         status = "disabled";
  630 };
  631 
  632 &epwm2 {
  633         status = "disabled";
  634 };
  635 
  636 &epwm3 {
  637         status = "disabled";
  638 };
  639 
  640 &epwm4 {
  641         status = "disabled";
  642 };
  643 
  644 &epwm5 {
  645         status = "disabled";
  646 };
  647 
  648 &epwm6 {
  649         status = "disabled";
  650 };
  651 
  652 &epwm7 {
  653         status = "disabled";
  654 };
  655 
  656 &epwm8 {
  657         status = "disabled";
  658 };
  659 
  660 &icssg0_mdio {
  661         status = "disabled";
  662 };
  663 
  664 &icssg1_mdio {
  665         status = "disabled";
  666 };
  667 
  668 &main_mcan0 {
  669         pinctrl-names = "default";
  670         pinctrl-0 = <&main_mcan0_pins_default>;
  671         phys = <&transceiver1>;
  672 };
  673 
  674 &main_mcan1 {
  675         pinctrl-names = "default";
  676         pinctrl-0 = <&main_mcan1_pins_default>;
  677         phys = <&transceiver2>;
  678 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/ti/k3-am642-evm.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/ti/k3-am642-evm.dts
