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1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 #include <dt-bindings/phy/phy-am654-serdes.h> 8 9 &cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <48000000>; 92 current-speed = <115200>; 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 }; 95 96 main_uart1: serial@2810000 { 97 compatible = "ti,am654-uart"; 98 reg = <0x00 0x02810000 0x00 0x100>; 99 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 100 clock-frequency = <48000000>; 101 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 102 }; 103 104 main_uart2: serial@2820000 { 105 compatible = "ti,am654-uart"; 106 reg = <0x00 0x02820000 0x00 0x100>; 107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 108 clock-frequency = <48000000>; 109 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 110 }; 111 112 crypto: crypto@4e00000 { 113 compatible = "ti,am654-sa2ul"; 114 reg = <0x0 0x4e00000 0x0 0x1200>; 115 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 119 120 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 121 <&main_udmap 0x4001>; 122 dma-names = "tx", "rx1", "rx2"; 123 dma-coherent; 124 125 rng: rng@4e10000 { 126 compatible = "inside-secure,safexcel-eip76"; 127 reg = <0x0 0x4e10000 0x0 0x7d>; 128 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&k3_clks 136 1>; 130 }; 131 }; 132 133 main_pmx0: pinctrl@11c000 { 134 compatible = "pinctrl-single"; 135 reg = <0x0 0x11c000 0x0 0x2e4>; 136 #pinctrl-cells = <1>; 137 pinctrl-single,register-width = <32>; 138 pinctrl-single,function-mask = <0xffffffff>; 139 }; 140 141 main_pmx1: pinctrl@11c2e8 { 142 compatible = "pinctrl-single"; 143 reg = <0x0 0x11c2e8 0x0 0x24>; 144 #pinctrl-cells = <1>; 145 pinctrl-single,register-width = <32>; 146 pinctrl-single,function-mask = <0xffffffff>; 147 }; 148 149 main_i2c0: i2c@2000000 { 150 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 151 reg = <0x0 0x2000000 0x0 0x100>; 152 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 clock-names = "fck"; 156 clocks = <&k3_clks 110 1>; 157 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 158 }; 159 160 main_i2c1: i2c@2010000 { 161 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 162 reg = <0x0 0x2010000 0x0 0x100>; 163 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 clock-names = "fck"; 167 clocks = <&k3_clks 111 1>; 168 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 169 }; 170 171 main_i2c2: i2c@2020000 { 172 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 173 reg = <0x0 0x2020000 0x0 0x100>; 174 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 clock-names = "fck"; 178 clocks = <&k3_clks 112 1>; 179 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 180 }; 181 182 main_i2c3: i2c@2030000 { 183 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 184 reg = <0x0 0x2030000 0x0 0x100>; 185 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 clock-names = "fck"; 189 clocks = <&k3_clks 113 1>; 190 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 191 }; 192 193 ecap0: pwm@3100000 { 194 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 195 #pwm-cells = <3>; 196 reg = <0x0 0x03100000 0x0 0x60>; 197 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 198 clocks = <&k3_clks 39 0>; 199 clock-names = "fck"; 200 }; 201 202 main_spi0: spi@2100000 { 203 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 204 reg = <0x0 0x2100000 0x0 0x400>; 205 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&k3_clks 137 1>; 207 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 211 dma-names = "tx0", "rx0"; 212 }; 213 214 main_spi1: spi@2110000 { 215 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 216 reg = <0x0 0x2110000 0x0 0x400>; 217 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&k3_clks 138 1>; 219 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 assigned-clocks = <&k3_clks 137 1>; 223 assigned-clock-rates = <48000000>; 224 }; 225 226 main_spi2: spi@2120000 { 227 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 228 reg = <0x0 0x2120000 0x0 0x400>; 229 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 230 clocks = <&k3_clks 139 1>; 231 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 }; 235 236 main_spi3: spi@2130000 { 237 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 238 reg = <0x0 0x2130000 0x0 0x400>; 239 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&k3_clks 140 1>; 241 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 }; 245 246 main_spi4: spi@2140000 { 247 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 248 reg = <0x0 0x2140000 0x0 0x400>; 249 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&k3_clks 141 1>; 251 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 }; 255 256 sdhci0: mmc@4f80000 { 257 compatible = "ti,am654-sdhci-5.1"; 258 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 259 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 260 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 261 clock-names = "clk_ahb", "clk_xin"; 262 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 263 mmc-ddr-1_8v; 264 mmc-hs200-1_8v; 265 ti,otap-del-sel-legacy = <0x0>; 266 ti,otap-del-sel-mmc-hs = <0x0>; 267 ti,otap-del-sel-sd-hs = <0x0>; 268 ti,otap-del-sel-sdr12 = <0x0>; 269 ti,otap-del-sel-sdr25 = <0x0>; 270 ti,otap-del-sel-sdr50 = <0x8>; 271 ti,otap-del-sel-sdr104 = <0x7>; 272 ti,otap-del-sel-ddr50 = <0x5>; 273 ti,otap-del-sel-ddr52 = <0x5>; 274 ti,otap-del-sel-hs200 = <0x5>; 275 ti,otap-del-sel-hs400 = <0x0>; 276 ti,trm-icp = <0x8>; 277 dma-coherent; 278 }; 279 280 sdhci1: mmc@4fa0000 { 281 compatible = "ti,am654-sdhci-5.1"; 282 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 283 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 284 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 285 clock-names = "clk_ahb", "clk_xin"; 286 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 287 ti,otap-del-sel-legacy = <0x0>; 288 ti,otap-del-sel-mmc-hs = <0x0>; 289 ti,otap-del-sel-sd-hs = <0x0>; 290 ti,otap-del-sel-sdr12 = <0x0>; 291 ti,otap-del-sel-sdr25 = <0x0>; 292 ti,otap-del-sel-sdr50 = <0x8>; 293 ti,otap-del-sel-sdr104 = <0x7>; 294 ti,otap-del-sel-ddr50 = <0x4>; 295 ti,otap-del-sel-ddr52 = <0x4>; 296 ti,otap-del-sel-hs200 = <0x7>; 297 ti,clkbuf-sel = <0x7>; 298 ti,otap-del-sel = <0x2>; 299 ti,trm-icp = <0x8>; 300 dma-coherent; 301 }; 302 303 scm_conf: scm-conf@100000 { 304 compatible = "syscon", "simple-mfd"; 305 reg = <0 0x00100000 0 0x1c000>; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 ranges = <0x0 0x0 0x00100000 0x1c000>; 309 310 pcie0_mode: pcie-mode@4060 { 311 compatible = "syscon"; 312 reg = <0x00004060 0x4>; 313 }; 314 315 pcie1_mode: pcie-mode@4070 { 316 compatible = "syscon"; 317 reg = <0x00004070 0x4>; 318 }; 319 320 pcie_devid: pcie-devid@210 { 321 compatible = "syscon"; 322 reg = <0x00000210 0x4>; 323 }; 324 325 serdes0_clk: clock@4080 { 326 compatible = "syscon"; 327 reg = <0x00004080 0x4>; 328 }; 329 330 serdes1_clk: clock@4090 { 331 compatible = "syscon"; 332 reg = <0x00004090 0x4>; 333 }; 334 335 serdes_mux: mux-controller { 336 compatible = "mmio-mux"; 337 #mux-control-cells = <1>; 338 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 339 <0x4090 0x3>; /* SERDES1 lane select */ 340 }; 341 342 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 343 compatible = "syscon"; 344 reg = <0x0000041e0 0x14>; 345 }; 346 347 ehrpwm_tbclk: clock@4140 { 348 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 349 reg = <0x4140 0x18>; 350 #clock-cells = <1>; 351 }; 352 }; 353 354 dwc3_0: dwc3@4000000 { 355 compatible = "ti,am654-dwc3"; 356 reg = <0x0 0x4000000 0x0 0x4000>; 357 #address-cells = <1>; 358 #size-cells = <1>; 359 ranges = <0x0 0x0 0x4000000 0x20000>; 360 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 361 dma-coherent; 362 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 364 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 365 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 366 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 367 368 usb0: usb@10000 { 369 compatible = "snps,dwc3"; 370 reg = <0x10000 0x10000>; 371 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-names = "peripheral", 375 "host", 376 "otg"; 377 maximum-speed = "high-speed"; 378 dr_mode = "otg"; 379 phys = <&usb0_phy>; 380 phy-names = "usb2-phy"; 381 snps,dis_u3_susphy_quirk; 382 }; 383 }; 384 385 usb0_phy: phy@4100000 { 386 compatible = "ti,am654-usb2", "ti,omap-usb2"; 387 reg = <0x0 0x4100000 0x0 0x54>; 388 syscon-phy-power = <&scm_conf 0x4000>; 389 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 390 clock-names = "wkupclk", "refclk"; 391 #phy-cells = <0>; 392 }; 393 394 dwc3_1: dwc3@4020000 { 395 compatible = "ti,am654-dwc3"; 396 reg = <0x0 0x4020000 0x0 0x4000>; 397 #address-cells = <1>; 398 #size-cells = <1>; 399 ranges = <0x0 0x0 0x4020000 0x20000>; 400 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 401 dma-coherent; 402 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 403 clocks = <&k3_clks 152 2>; 404 assigned-clocks = <&k3_clks 152 2>; 405 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 406 407 usb1: usb@10000 { 408 compatible = "snps,dwc3"; 409 reg = <0x10000 0x10000>; 410 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 413 interrupt-names = "peripheral", 414 "host", 415 "otg"; 416 maximum-speed = "high-speed"; 417 dr_mode = "otg"; 418 phys = <&usb1_phy>; 419 phy-names = "usb2-phy"; 420 }; 421 }; 422 423 usb1_phy: phy@4110000 { 424 compatible = "ti,am654-usb2", "ti,omap-usb2"; 425 reg = <0x0 0x4110000 0x0 0x54>; 426 syscon-phy-power = <&scm_conf 0x4020>; 427 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 428 clock-names = "wkupclk", "refclk"; 429 #phy-cells = <0>; 430 }; 431 432 intr_main_gpio: interrupt-controller@a00000 { 433 compatible = "ti,sci-intr"; 434 reg = <0x0 0x00a00000 0x0 0x400>; 435 ti,intr-trigger-type = <1>; 436 interrupt-controller; 437 interrupt-parent = <&gic500>; 438 #interrupt-cells = <1>; 439 ti,sci = <&dmsc>; 440 ti,sci-dev-id = <100>; 441 ti,interrupt-ranges = <0 392 32>; 442 }; 443 444 main_navss: bus@30800000 { 445 compatible = "simple-mfd"; 446 #address-cells = <2>; 447 #size-cells = <2>; 448 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 449 dma-coherent; 450 dma-ranges; 451 452 ti,sci-dev-id = <118>; 453 454 intr_main_navss: interrupt-controller@310e0000 { 455 compatible = "ti,sci-intr"; 456 reg = <0x0 0x310e0000 0x0 0x2000>; 457 ti,intr-trigger-type = <4>; 458 interrupt-controller; 459 interrupt-parent = <&gic500>; 460 #interrupt-cells = <1>; 461 ti,sci = <&dmsc>; 462 ti,sci-dev-id = <182>; 463 ti,interrupt-ranges = <0 64 64>, 464 <64 448 64>; 465 }; 466 467 inta_main_udmass: interrupt-controller@33d00000 { 468 compatible = "ti,sci-inta"; 469 reg = <0x0 0x33d00000 0x0 0x100000>; 470 interrupt-controller; 471 interrupt-parent = <&intr_main_navss>; 472 msi-controller; 473 #interrupt-cells = <0>; 474 ti,sci = <&dmsc>; 475 ti,sci-dev-id = <179>; 476 ti,interrupt-ranges = <0 0 256>; 477 }; 478 479 secure_proxy_main: mailbox@32c00000 { 480 compatible = "ti,am654-secure-proxy"; 481 #mbox-cells = <1>; 482 reg-names = "target_data", "rt", "scfg"; 483 reg = <0x00 0x32c00000 0x00 0x100000>, 484 <0x00 0x32400000 0x00 0x100000>, 485 <0x00 0x32800000 0x00 0x100000>; 486 interrupt-names = "rx_011"; 487 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 488 }; 489 490 hwspinlock: spinlock@30e00000 { 491 compatible = "ti,am654-hwspinlock"; 492 reg = <0x00 0x30e00000 0x00 0x1000>; 493 #hwlock-cells = <1>; 494 }; 495 496 mailbox0_cluster0: mailbox@31f80000 { 497 compatible = "ti,am654-mailbox"; 498 reg = <0x00 0x31f80000 0x00 0x200>; 499 #mbox-cells = <1>; 500 ti,mbox-num-users = <4>; 501 ti,mbox-num-fifos = <16>; 502 interrupt-parent = <&intr_main_navss>; 503 }; 504 505 mailbox0_cluster1: mailbox@31f81000 { 506 compatible = "ti,am654-mailbox"; 507 reg = <0x00 0x31f81000 0x00 0x200>; 508 #mbox-cells = <1>; 509 ti,mbox-num-users = <4>; 510 ti,mbox-num-fifos = <16>; 511 interrupt-parent = <&intr_main_navss>; 512 }; 513 514 mailbox0_cluster2: mailbox@31f82000 { 515 compatible = "ti,am654-mailbox"; 516 reg = <0x00 0x31f82000 0x00 0x200>; 517 #mbox-cells = <1>; 518 ti,mbox-num-users = <4>; 519 ti,mbox-num-fifos = <16>; 520 interrupt-parent = <&intr_main_navss>; 521 }; 522 523 mailbox0_cluster3: mailbox@31f83000 { 524 compatible = "ti,am654-mailbox"; 525 reg = <0x00 0x31f83000 0x00 0x200>; 526 #mbox-cells = <1>; 527 ti,mbox-num-users = <4>; 528 ti,mbox-num-fifos = <16>; 529 interrupt-parent = <&intr_main_navss>; 530 }; 531 532 mailbox0_cluster4: mailbox@31f84000 { 533 compatible = "ti,am654-mailbox"; 534 reg = <0x00 0x31f84000 0x00 0x200>; 535 #mbox-cells = <1>; 536 ti,mbox-num-users = <4>; 537 ti,mbox-num-fifos = <16>; 538 interrupt-parent = <&intr_main_navss>; 539 }; 540 541 mailbox0_cluster5: mailbox@31f85000 { 542 compatible = "ti,am654-mailbox"; 543 reg = <0x00 0x31f85000 0x00 0x200>; 544 #mbox-cells = <1>; 545 ti,mbox-num-users = <4>; 546 ti,mbox-num-fifos = <16>; 547 interrupt-parent = <&intr_main_navss>; 548 }; 549 550 mailbox0_cluster6: mailbox@31f86000 { 551 compatible = "ti,am654-mailbox"; 552 reg = <0x00 0x31f86000 0x00 0x200>; 553 #mbox-cells = <1>; 554 ti,mbox-num-users = <4>; 555 ti,mbox-num-fifos = <16>; 556 interrupt-parent = <&intr_main_navss>; 557 }; 558 559 mailbox0_cluster7: mailbox@31f87000 { 560 compatible = "ti,am654-mailbox"; 561 reg = <0x00 0x31f87000 0x00 0x200>; 562 #mbox-cells = <1>; 563 ti,mbox-num-users = <4>; 564 ti,mbox-num-fifos = <16>; 565 interrupt-parent = <&intr_main_navss>; 566 }; 567 568 mailbox0_cluster8: mailbox@31f88000 { 569 compatible = "ti,am654-mailbox"; 570 reg = <0x00 0x31f88000 0x00 0x200>; 571 #mbox-cells = <1>; 572 ti,mbox-num-users = <4>; 573 ti,mbox-num-fifos = <16>; 574 interrupt-parent = <&intr_main_navss>; 575 }; 576 577 mailbox0_cluster9: mailbox@31f89000 { 578 compatible = "ti,am654-mailbox"; 579 reg = <0x00 0x31f89000 0x00 0x200>; 580 #mbox-cells = <1>; 581 ti,mbox-num-users = <4>; 582 ti,mbox-num-fifos = <16>; 583 interrupt-parent = <&intr_main_navss>; 584 }; 585 586 mailbox0_cluster10: mailbox@31f8a000 { 587 compatible = "ti,am654-mailbox"; 588 reg = <0x00 0x31f8a000 0x00 0x200>; 589 #mbox-cells = <1>; 590 ti,mbox-num-users = <4>; 591 ti,mbox-num-fifos = <16>; 592 interrupt-parent = <&intr_main_navss>; 593 }; 594 595 mailbox0_cluster11: mailbox@31f8b000 { 596 compatible = "ti,am654-mailbox"; 597 reg = <0x00 0x31f8b000 0x00 0x200>; 598 #mbox-cells = <1>; 599 ti,mbox-num-users = <4>; 600 ti,mbox-num-fifos = <16>; 601 interrupt-parent = <&intr_main_navss>; 602 }; 603 604 ringacc: ringacc@3c000000 { 605 compatible = "ti,am654-navss-ringacc"; 606 reg = <0x0 0x3c000000 0x0 0x400000>, 607 <0x0 0x38000000 0x0 0x400000>, 608 <0x0 0x31120000 0x0 0x100>, 609 <0x0 0x33000000 0x0 0x40000>; 610 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 611 ti,num-rings = <818>; 612 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 613 ti,sci = <&dmsc>; 614 ti,sci-dev-id = <187>; 615 msi-parent = <&inta_main_udmass>; 616 }; 617 618 main_udmap: dma-controller@31150000 { 619 compatible = "ti,am654-navss-main-udmap"; 620 reg = <0x0 0x31150000 0x0 0x100>, 621 <0x0 0x34000000 0x0 0x100000>, 622 <0x0 0x35000000 0x0 0x100000>; 623 reg-names = "gcfg", "rchanrt", "tchanrt"; 624 msi-parent = <&inta_main_udmass>; 625 #dma-cells = <1>; 626 627 ti,sci = <&dmsc>; 628 ti,sci-dev-id = <188>; 629 ti,ringacc = <&ringacc>; 630 631 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 632 <0xd>; /* TX_CHAN */ 633 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 634 <0xa>; /* RX_CHAN */ 635 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 636 }; 637 638 cpts@310d0000 { 639 compatible = "ti,am65-cpts"; 640 reg = <0x0 0x310d0000 0x0 0x400>; 641 reg-names = "cpts"; 642 clocks = <&main_cpts_mux>; 643 clock-names = "cpts"; 644 interrupts-extended = <&intr_main_navss 391>; 645 interrupt-names = "cpts"; 646 ti,cpts-periodic-outputs = <6>; 647 ti,cpts-ext-ts-inputs = <8>; 648 649 main_cpts_mux: refclk-mux { 650 #clock-cells = <0>; 651 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 652 <&k3_clks 118 6>, <&k3_clks 118 3>, 653 <&k3_clks 118 8>, <&k3_clks 118 14>, 654 <&k3_clks 120 3>, <&k3_clks 121 3>; 655 assigned-clocks = <&main_cpts_mux>; 656 assigned-clock-parents = <&k3_clks 118 5>; 657 }; 658 }; 659 }; 660 661 main_gpio0: gpio@600000 { 662 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 663 reg = <0x0 0x600000 0x0 0x100>; 664 gpio-controller; 665 #gpio-cells = <2>; 666 interrupt-parent = <&intr_main_gpio>; 667 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 668 interrupt-controller; 669 #interrupt-cells = <2>; 670 ti,ngpio = <96>; 671 ti,davinci-gpio-unbanked = <0>; 672 clocks = <&k3_clks 57 0>; 673 clock-names = "gpio"; 674 }; 675 676 main_gpio1: gpio@601000 { 677 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 678 reg = <0x0 0x601000 0x0 0x100>; 679 gpio-controller; 680 #gpio-cells = <2>; 681 interrupt-parent = <&intr_main_gpio>; 682 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 683 interrupt-controller; 684 #interrupt-cells = <2>; 685 ti,ngpio = <90>; 686 ti,davinci-gpio-unbanked = <0>; 687 clocks = <&k3_clks 58 0>; 688 clock-names = "gpio"; 689 }; 690 691 pcie0_rc: pcie@5500000 { 692 compatible = "ti,am654-pcie-rc"; 693 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 694 reg-names = "app", "dbics", "config", "atu"; 695 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 696 #address-cells = <3>; 697 #size-cells = <2>; 698 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, 699 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 700 ti,syscon-pcie-id = <&pcie_devid>; 701 ti,syscon-pcie-mode = <&pcie0_mode>; 702 bus-range = <0x0 0xff>; 703 num-viewport = <16>; 704 max-link-speed = <2>; 705 dma-coherent; 706 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 707 msi-map = <0x0 &gic_its 0x0 0x10000>; 708 device_type = "pci"; 709 }; 710 711 pcie0_ep: pcie-ep@5500000 { 712 compatible = "ti,am654-pcie-ep"; 713 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 714 reg-names = "app", "dbics", "addr_space", "atu"; 715 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 716 ti,syscon-pcie-mode = <&pcie0_mode>; 717 num-ib-windows = <16>; 718 num-ob-windows = <16>; 719 max-link-speed = <2>; 720 dma-coherent; 721 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 722 }; 723 724 pcie1_rc: pcie@5600000 { 725 compatible = "ti,am654-pcie-rc"; 726 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 727 reg-names = "app", "dbics", "config", "atu"; 728 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 729 #address-cells = <3>; 730 #size-cells = <2>; 731 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, 732 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 733 ti,syscon-pcie-id = <&pcie_devid>; 734 ti,syscon-pcie-mode = <&pcie1_mode>; 735 bus-range = <0x0 0xff>; 736 num-viewport = <16>; 737 max-link-speed = <2>; 738 dma-coherent; 739 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 740 msi-map = <0x0 &gic_its 0x10000 0x10000>; 741 device_type = "pci"; 742 }; 743 744 pcie1_ep: pcie-ep@5600000 { 745 compatible = "ti,am654-pcie-ep"; 746 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 747 reg-names = "app", "dbics", "addr_space", "atu"; 748 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 749 ti,syscon-pcie-mode = <&pcie1_mode>; 750 num-ib-windows = <16>; 751 num-ob-windows = <16>; 752 max-link-speed = <2>; 753 dma-coherent; 754 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 755 }; 756 757 mcasp0: mcasp@2b00000 { 758 compatible = "ti,am33xx-mcasp-audio"; 759 reg = <0x0 0x02b00000 0x0 0x2000>, 760 <0x0 0x02b08000 0x0 0x1000>; 761 reg-names = "mpu","dat"; 762 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 764 interrupt-names = "tx", "rx"; 765 766 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 767 dma-names = "tx", "rx"; 768 769 clocks = <&k3_clks 104 0>; 770 clock-names = "fck"; 771 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 772 }; 773 774 mcasp1: mcasp@2b10000 { 775 compatible = "ti,am33xx-mcasp-audio"; 776 reg = <0x0 0x02b10000 0x0 0x2000>, 777 <0x0 0x02b18000 0x0 0x1000>; 778 reg-names = "mpu","dat"; 779 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "tx", "rx"; 782 783 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 784 dma-names = "tx", "rx"; 785 786 clocks = <&k3_clks 105 0>; 787 clock-names = "fck"; 788 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 789 }; 790 791 mcasp2: mcasp@2b20000 { 792 compatible = "ti,am33xx-mcasp-audio"; 793 reg = <0x0 0x02b20000 0x0 0x2000>, 794 <0x0 0x02b28000 0x0 0x1000>; 795 reg-names = "mpu","dat"; 796 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 798 interrupt-names = "tx", "rx"; 799 800 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 801 dma-names = "tx", "rx"; 802 803 clocks = <&k3_clks 106 0>; 804 clock-names = "fck"; 805 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 806 }; 807 808 cal: cal@6f03000 { 809 compatible = "ti,am654-cal"; 810 reg = <0x0 0x06f03000 0x0 0x400>, 811 <0x0 0x06f03800 0x0 0x40>; 812 reg-names = "cal_top", 813 "cal_rx_core0"; 814 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 815 ti,camerrx-control = <&scm_conf 0x40c0>; 816 clock-names = "fck"; 817 clocks = <&k3_clks 2 0>; 818 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 819 820 ports { 821 #address-cells = <1>; 822 #size-cells = <0>; 823 824 csi2_0: port@0 { 825 reg = <0>; 826 }; 827 }; 828 }; 829 830 dss: dss@4a00000 { 831 compatible = "ti,am65x-dss"; 832 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 833 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 834 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 835 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 836 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 837 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 838 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 839 reg-names = "common", "vidl1", "vid", 840 "ovr1", "ovr2", "vp1", "vp2"; 841 842 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 843 844 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 845 846 clocks = <&k3_clks 67 1>, 847 <&k3_clks 216 1>, 848 <&k3_clks 67 2>; 849 clock-names = "fck", "vp1", "vp2"; 850 851 /* 852 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 853 * DIV1. See "Figure 12-3365. DSS Integration" 854 * in AM65x TRM for details. 855 */ 856 assigned-clocks = <&k3_clks 67 2>; 857 assigned-clock-parents = <&k3_clks 67 5>; 858 859 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 860 861 dma-coherent; 862 863 dss_ports: ports { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 }; 867 }; 868 869 ehrpwm0: pwm@3000000 { 870 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 871 #pwm-cells = <3>; 872 reg = <0x0 0x3000000 0x0 0x100>; 873 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 874 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 875 clock-names = "tbclk", "fck"; 876 }; 877 878 ehrpwm1: pwm@3010000 { 879 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 880 #pwm-cells = <3>; 881 reg = <0x0 0x3010000 0x0 0x100>; 882 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 883 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 884 clock-names = "tbclk", "fck"; 885 }; 886 887 ehrpwm2: pwm@3020000 { 888 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 889 #pwm-cells = <3>; 890 reg = <0x0 0x3020000 0x0 0x100>; 891 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 892 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 893 clock-names = "tbclk", "fck"; 894 }; 895 896 ehrpwm3: pwm@3030000 { 897 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 898 #pwm-cells = <3>; 899 reg = <0x0 0x3030000 0x0 0x100>; 900 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 901 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 902 clock-names = "tbclk", "fck"; 903 }; 904 905 ehrpwm4: pwm@3040000 { 906 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 907 #pwm-cells = <3>; 908 reg = <0x0 0x3040000 0x0 0x100>; 909 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 910 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 911 clock-names = "tbclk", "fck"; 912 }; 913 914 ehrpwm5: pwm@3050000 { 915 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 916 #pwm-cells = <3>; 917 reg = <0x0 0x3050000 0x0 0x100>; 918 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 919 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 920 clock-names = "tbclk", "fck"; 921 }; 922 923 icssg0: icssg@b000000 { 924 compatible = "ti,am654-icssg"; 925 reg = <0x00 0xb000000 0x00 0x80000>; 926 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 927 #address-cells = <1>; 928 #size-cells = <1>; 929 ranges = <0x0 0x00 0xb000000 0x80000>; 930 931 icssg0_mem: memories@0 { 932 reg = <0x0 0x2000>, 933 <0x2000 0x2000>, 934 <0x10000 0x10000>; 935 reg-names = "dram0", "dram1", 936 "shrdram2"; 937 }; 938 939 icssg0_cfg: cfg@26000 { 940 compatible = "ti,pruss-cfg", "syscon"; 941 reg = <0x26000 0x200>; 942 #address-cells = <1>; 943 #size-cells = <1>; 944 ranges = <0x0 0x26000 0x2000>; 945 946 clocks { 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 icssg0_coreclk_mux: coreclk-mux@3c { 951 reg = <0x3c>; 952 #clock-cells = <0>; 953 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 954 <&k3_clks 62 3>; /* icssg0_iclk */ 955 assigned-clocks = <&icssg0_coreclk_mux>; 956 assigned-clock-parents = <&k3_clks 62 3>; 957 }; 958 959 icssg0_iepclk_mux: iepclk-mux@30 { 960 reg = <0x30>; 961 #clock-cells = <0>; 962 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 963 <&icssg0_coreclk_mux>; /* core_clk */ 964 assigned-clocks = <&icssg0_iepclk_mux>; 965 assigned-clock-parents = <&icssg0_coreclk_mux>; 966 }; 967 }; 968 }; 969 970 icssg0_mii_rt: mii-rt@32000 { 971 compatible = "ti,pruss-mii", "syscon"; 972 reg = <0x32000 0x100>; 973 }; 974 975 icssg0_mii_g_rt: mii-g-rt@33000 { 976 compatible = "ti,pruss-mii-g", "syscon"; 977 reg = <0x33000 0x1000>; 978 }; 979 980 icssg0_intc: interrupt-controller@20000 { 981 compatible = "ti,icssg-intc"; 982 reg = <0x20000 0x2000>; 983 interrupt-controller; 984 #interrupt-cells = <3>; 985 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "host_intr0", "host_intr1", 994 "host_intr2", "host_intr3", 995 "host_intr4", "host_intr5", 996 "host_intr6", "host_intr7"; 997 }; 998 999 pru0_0: pru@34000 { 1000 compatible = "ti,am654-pru"; 1001 reg = <0x34000 0x4000>, 1002 <0x22000 0x100>, 1003 <0x22400 0x100>; 1004 reg-names = "iram", "control", "debug"; 1005 firmware-name = "am65x-pru0_0-fw"; 1006 }; 1007 1008 rtu0_0: rtu@4000 { 1009 compatible = "ti,am654-rtu"; 1010 reg = <0x4000 0x2000>, 1011 <0x23000 0x100>, 1012 <0x23400 0x100>; 1013 reg-names = "iram", "control", "debug"; 1014 firmware-name = "am65x-rtu0_0-fw"; 1015 }; 1016 1017 tx_pru0_0: txpru@a000 { 1018 compatible = "ti,am654-tx-pru"; 1019 reg = <0xa000 0x1800>, 1020 <0x25000 0x100>, 1021 <0x25400 0x100>; 1022 reg-names = "iram", "control", "debug"; 1023 firmware-name = "am65x-txpru0_0-fw"; 1024 }; 1025 1026 pru0_1: pru@38000 { 1027 compatible = "ti,am654-pru"; 1028 reg = <0x38000 0x4000>, 1029 <0x24000 0x100>, 1030 <0x24400 0x100>; 1031 reg-names = "iram", "control", "debug"; 1032 firmware-name = "am65x-pru0_1-fw"; 1033 }; 1034 1035 rtu0_1: rtu@6000 { 1036 compatible = "ti,am654-rtu"; 1037 reg = <0x6000 0x2000>, 1038 <0x23800 0x100>, 1039 <0x23c00 0x100>; 1040 reg-names = "iram", "control", "debug"; 1041 firmware-name = "am65x-rtu0_1-fw"; 1042 }; 1043 1044 tx_pru0_1: txpru@c000 { 1045 compatible = "ti,am654-tx-pru"; 1046 reg = <0xc000 0x1800>, 1047 <0x25800 0x100>, 1048 <0x25c00 0x100>; 1049 reg-names = "iram", "control", "debug"; 1050 firmware-name = "am65x-txpru0_1-fw"; 1051 }; 1052 1053 icssg0_mdio: mdio@32400 { 1054 compatible = "ti,davinci_mdio"; 1055 reg = <0x32400 0x100>; 1056 clocks = <&k3_clks 62 3>; 1057 clock-names = "fck"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 bus_freq = <1000000>; 1061 }; 1062 }; 1063 1064 icssg1: icssg@b100000 { 1065 compatible = "ti,am654-icssg"; 1066 reg = <0x00 0xb100000 0x00 0x80000>; 1067 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1068 #address-cells = <1>; 1069 #size-cells = <1>; 1070 ranges = <0x0 0x00 0xb100000 0x80000>; 1071 1072 icssg1_mem: memories@0 { 1073 reg = <0x0 0x2000>, 1074 <0x2000 0x2000>, 1075 <0x10000 0x10000>; 1076 reg-names = "dram0", "dram1", 1077 "shrdram2"; 1078 }; 1079 1080 icssg1_cfg: cfg@26000 { 1081 compatible = "ti,pruss-cfg", "syscon"; 1082 reg = <0x26000 0x200>; 1083 #address-cells = <1>; 1084 #size-cells = <1>; 1085 ranges = <0x0 0x26000 0x2000>; 1086 1087 clocks { 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 icssg1_coreclk_mux: coreclk-mux@3c { 1092 reg = <0x3c>; 1093 #clock-cells = <0>; 1094 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1095 <&k3_clks 63 3>; /* icssg1_iclk */ 1096 assigned-clocks = <&icssg1_coreclk_mux>; 1097 assigned-clock-parents = <&k3_clks 63 3>; 1098 }; 1099 1100 icssg1_iepclk_mux: iepclk-mux@30 { 1101 reg = <0x30>; 1102 #clock-cells = <0>; 1103 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1104 <&icssg1_coreclk_mux>; /* core_clk */ 1105 assigned-clocks = <&icssg1_iepclk_mux>; 1106 assigned-clock-parents = <&icssg1_coreclk_mux>; 1107 }; 1108 }; 1109 }; 1110 1111 icssg1_mii_rt: mii-rt@32000 { 1112 compatible = "ti,pruss-mii", "syscon"; 1113 reg = <0x32000 0x100>; 1114 }; 1115 1116 icssg1_mii_g_rt: mii-g-rt@33000 { 1117 compatible = "ti,pruss-mii-g", "syscon"; 1118 reg = <0x33000 0x1000>; 1119 }; 1120 1121 icssg1_intc: interrupt-controller@20000 { 1122 compatible = "ti,icssg-intc"; 1123 reg = <0x20000 0x2000>; 1124 interrupt-controller; 1125 #interrupt-cells = <3>; 1126 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1134 interrupt-names = "host_intr0", "host_intr1", 1135 "host_intr2", "host_intr3", 1136 "host_intr4", "host_intr5", 1137 "host_intr6", "host_intr7"; 1138 }; 1139 1140 pru1_0: pru@34000 { 1141 compatible = "ti,am654-pru"; 1142 reg = <0x34000 0x4000>, 1143 <0x22000 0x100>, 1144 <0x22400 0x100>; 1145 reg-names = "iram", "control", "debug"; 1146 firmware-name = "am65x-pru1_0-fw"; 1147 }; 1148 1149 rtu1_0: rtu@4000 { 1150 compatible = "ti,am654-rtu"; 1151 reg = <0x4000 0x2000>, 1152 <0x23000 0x100>, 1153 <0x23400 0x100>; 1154 reg-names = "iram", "control", "debug"; 1155 firmware-name = "am65x-rtu1_0-fw"; 1156 }; 1157 1158 tx_pru1_0: txpru@a000 { 1159 compatible = "ti,am654-tx-pru"; 1160 reg = <0xa000 0x1800>, 1161 <0x25000 0x100>, 1162 <0x25400 0x100>; 1163 reg-names = "iram", "control", "debug"; 1164 firmware-name = "am65x-txpru1_0-fw"; 1165 }; 1166 1167 pru1_1: pru@38000 { 1168 compatible = "ti,am654-pru"; 1169 reg = <0x38000 0x4000>, 1170 <0x24000 0x100>, 1171 <0x24400 0x100>; 1172 reg-names = "iram", "control", "debug"; 1173 firmware-name = "am65x-pru1_1-fw"; 1174 }; 1175 1176 rtu1_1: rtu@6000 { 1177 compatible = "ti,am654-rtu"; 1178 reg = <0x6000 0x2000>, 1179 <0x23800 0x100>, 1180 <0x23c00 0x100>; 1181 reg-names = "iram", "control", "debug"; 1182 firmware-name = "am65x-rtu1_1-fw"; 1183 }; 1184 1185 tx_pru1_1: txpru@c000 { 1186 compatible = "ti,am654-tx-pru"; 1187 reg = <0xc000 0x1800>, 1188 <0x25800 0x100>, 1189 <0x25c00 0x100>; 1190 reg-names = "iram", "control", "debug"; 1191 firmware-name = "am65x-txpru1_1-fw"; 1192 }; 1193 1194 icssg1_mdio: mdio@32400 { 1195 compatible = "ti,davinci_mdio"; 1196 reg = <0x32400 0x100>; 1197 clocks = <&k3_clks 63 3>; 1198 clock-names = "fck"; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 bus_freq = <1000000>; 1202 }; 1203 }; 1204 1205 icssg2: icssg@b200000 { 1206 compatible = "ti,am654-icssg"; 1207 reg = <0x00 0xb200000 0x00 0x80000>; 1208 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1209 #address-cells = <1>; 1210 #size-cells = <1>; 1211 ranges = <0x0 0x00 0xb200000 0x80000>; 1212 1213 icssg2_mem: memories@0 { 1214 reg = <0x0 0x2000>, 1215 <0x2000 0x2000>, 1216 <0x10000 0x10000>; 1217 reg-names = "dram0", "dram1", 1218 "shrdram2"; 1219 }; 1220 1221 icssg2_cfg: cfg@26000 { 1222 compatible = "ti,pruss-cfg", "syscon"; 1223 reg = <0x26000 0x200>; 1224 #address-cells = <1>; 1225 #size-cells = <1>; 1226 ranges = <0x0 0x26000 0x2000>; 1227 1228 clocks { 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 1232 icssg2_coreclk_mux: coreclk-mux@3c { 1233 reg = <0x3c>; 1234 #clock-cells = <0>; 1235 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1236 <&k3_clks 64 3>; /* icssg1_iclk */ 1237 assigned-clocks = <&icssg2_coreclk_mux>; 1238 assigned-clock-parents = <&k3_clks 64 3>; 1239 }; 1240 1241 icssg2_iepclk_mux: iepclk-mux@30 { 1242 reg = <0x30>; 1243 #clock-cells = <0>; 1244 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1245 <&icssg2_coreclk_mux>; /* core_clk */ 1246 assigned-clocks = <&icssg2_iepclk_mux>; 1247 assigned-clock-parents = <&icssg2_coreclk_mux>; 1248 }; 1249 }; 1250 }; 1251 1252 icssg2_mii_rt: mii-rt@32000 { 1253 compatible = "ti,pruss-mii", "syscon"; 1254 reg = <0x32000 0x100>; 1255 }; 1256 1257 icssg2_mii_g_rt: mii-g-rt@33000 { 1258 compatible = "ti,pruss-mii-g", "syscon"; 1259 reg = <0x33000 0x1000>; 1260 }; 1261 1262 icssg2_intc: interrupt-controller@20000 { 1263 compatible = "ti,icssg-intc"; 1264 reg = <0x20000 0x2000>; 1265 interrupt-controller; 1266 #interrupt-cells = <3>; 1267 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1275 interrupt-names = "host_intr0", "host_intr1", 1276 "host_intr2", "host_intr3", 1277 "host_intr4", "host_intr5", 1278 "host_intr6", "host_intr7"; 1279 }; 1280 1281 pru2_0: pru@34000 { 1282 compatible = "ti,am654-pru"; 1283 reg = <0x34000 0x4000>, 1284 <0x22000 0x100>, 1285 <0x22400 0x100>; 1286 reg-names = "iram", "control", "debug"; 1287 firmware-name = "am65x-pru2_0-fw"; 1288 }; 1289 1290 rtu2_0: rtu@4000 { 1291 compatible = "ti,am654-rtu"; 1292 reg = <0x4000 0x2000>, 1293 <0x23000 0x100>, 1294 <0x23400 0x100>; 1295 reg-names = "iram", "control", "debug"; 1296 firmware-name = "am65x-rtu2_0-fw"; 1297 }; 1298 1299 tx_pru2_0: txpru@a000 { 1300 compatible = "ti,am654-tx-pru"; 1301 reg = <0xa000 0x1800>, 1302 <0x25000 0x100>, 1303 <0x25400 0x100>; 1304 reg-names = "iram", "control", "debug"; 1305 firmware-name = "am65x-txpru2_0-fw"; 1306 }; 1307 1308 pru2_1: pru@38000 { 1309 compatible = "ti,am654-pru"; 1310 reg = <0x38000 0x4000>, 1311 <0x24000 0x100>, 1312 <0x24400 0x100>; 1313 reg-names = "iram", "control", "debug"; 1314 firmware-name = "am65x-pru2_1-fw"; 1315 }; 1316 1317 rtu2_1: rtu@6000 { 1318 compatible = "ti,am654-rtu"; 1319 reg = <0x6000 0x2000>, 1320 <0x23800 0x100>, 1321 <0x23c00 0x100>; 1322 reg-names = "iram", "control", "debug"; 1323 firmware-name = "am65x-rtu2_1-fw"; 1324 }; 1325 1326 tx_pru2_1: txpru@c000 { 1327 compatible = "ti,am654-tx-pru"; 1328 reg = <0xc000 0x1800>, 1329 <0x25800 0x100>, 1330 <0x25c00 0x100>; 1331 reg-names = "iram", "control", "debug"; 1332 firmware-name = "am65x-txpru2_1-fw"; 1333 }; 1334 1335 icssg2_mdio: mdio@32400 { 1336 compatible = "ti,davinci_mdio"; 1337 reg = <0x32400 0x100>; 1338 clocks = <&k3_clks 64 3>; 1339 clock-names = "fck"; 1340 #address-cells = <1>; 1341 #size-cells = <0>; 1342 bus_freq = <1000000>; 1343 }; 1344 }; 1345 };
Cache object: b31c2c39e2e3efbd2b344c1691083d17
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