k3-am65.dtsi

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10

    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Device Tree Source for AM6 SoC Family
    4  *
    5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
    6  */
    7 
    8 #include <dt-bindings/gpio/gpio.h>
    9 #include <dt-bindings/interrupt-controller/irq.h>
   10 #include <dt-bindings/interrupt-controller/arm-gic.h>
   11 #include <dt-bindings/pinctrl/k3.h>
   12 #include <dt-bindings/soc/ti,sci_pm_domain.h>
   13 
   14 / {
   15         model = "Texas Instruments K3 AM654 SoC";
   16         compatible = "ti,am654";
   17         interrupt-parent = <&gic500>;
   18         #address-cells = <2>;
   19         #size-cells = <2>;
   20 
   21         aliases {
   22                 serial0 = &wkup_uart0;
   23                 serial1 = &mcu_uart0;
   24                 serial2 = &main_uart0;
   25                 serial3 = &main_uart1;
   26                 serial4 = &main_uart2;
   27                 i2c0 = &wkup_i2c0;
   28                 i2c1 = &mcu_i2c0;
   29                 i2c2 = &main_i2c0;
   30                 i2c3 = &main_i2c1;
   31                 i2c4 = &main_i2c2;
   32                 i2c5 = &main_i2c3;
   33                 ethernet0 = &cpsw_port1;
   34                 mmc0 = &sdhci0;
   35                 mmc1 = &sdhci1;
   36         };
   37 
   38         chosen { };
   39 
   40         firmware {
   41                 optee {
   42                         compatible = "linaro,optee-tz";
   43                         method = "smc";
   44                 };
   45 
   46                 psci: psci {
   47                         compatible = "arm,psci-1.0";
   48                         method = "smc";
   49                 };
   50         };
   51 
   52         a53_timer0: timer-cl0-cpu0 {
   53                 compatible = "arm,armv8-timer";
   54                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
   55                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
   56                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
   57                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
   58         };
   59 
   60         pmu: pmu {
   61                 compatible = "arm,cortex-a53-pmu";
   62                 /* Recommendation from GIC500 TRM Table A.3 */
   63                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
   64         };
   65 
   66         cbass_main: bus@100000 {
   67                 compatible = "simple-bus";
   68                 #address-cells = <2>;
   69                 #size-cells = <2>;
   70                 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
   71                          <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
   72                          <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
   73                          <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
   74                          <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
   75                          <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
   76                          <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
   77                          /* MCUSS Range */
   78                          <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
   79                          <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
   80                          <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
   81                          <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
   82                          <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
   83                          <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>,
   84                          <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
   85                          <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
   86                          <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
   87                          <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
   88                          <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>,
   89                          <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A53 PERIPHBASE */
   90                          <0x00 0x70000000 0x00 0x70000000 0x00 0x200000>,
   91                          <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>,
   92                          <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>;
   93 
   94                 cbass_mcu: bus@28380000 {
   95                         compatible = "simple-bus";
   96                         #address-cells = <2>;
   97                         #size-cells = <2>;
   98                         ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
   99                                  <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */
  100                                  <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
  101                                  <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
  102                                  <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
  103                                  <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */
  104                                  <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */
  105                                  <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
  106                                  <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
  107                                  <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */
  108                                  <0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /*  FSS OSPI0 data region 1 */
  109                                  <0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/
  110                                  <0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/
  111 
  112                         cbass_wakeup: bus@42040000 {
  113                                 compatible = "simple-bus";
  114                                 #address-cells = <1>;
  115                                 #size-cells = <1>;
  116                                 /* WKUP  Basic peripherals */
  117                                 ranges = <0x42040000 0x00 0x42040000 0x03ac2400>;
  118                         };
  119                 };
  120         };
  121 };
  122 
  123 /* Now include the peripherals for each bus segments */
  124 #include "k3-am65-main.dtsi"
  125 #include "k3-am65-mcu.dtsi"
  126 #include "k3-am65-wakeup.dtsi"

Cache object: 33583ce916fb008bc28500eb3bd61ba0

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.

FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/ti/k3-am65.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/ti/k3-am65.dtsi