k3-j721e-common-proc-board.dts

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
    4  */
    5 
    6 /dts-v1/;
    7 
    8 #include "k3-j721e-som-p0.dtsi"
    9 #include <dt-bindings/gpio/gpio.h>
   10 #include <dt-bindings/input/input.h>
   11 #include <dt-bindings/net/ti-dp83867.h>
   12 #include <dt-bindings/phy/phy-cadence.h>
   13 
   14 / {
   15         compatible = "ti,j721e-evm", "ti,j721e";
   16         model = "Texas Instruments J721e EVM";
   17 
   18         chosen {
   19                 stdout-path = "serial2:115200n8";
   20                 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
   21         };
   22 
   23         gpio_keys: gpio-keys {
   24                 compatible = "gpio-keys";
   25                 autorepeat;
   26                 pinctrl-names = "default";
   27                 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
   28 
   29                 sw10: switch-10 {
   30                         label = "GPIO Key USER1";
   31                         linux,code = <BTN_0>;
   32                         gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
   33                 };
   34 
   35                 sw11: switch-11 {
   36                         label = "GPIO Key USER2";
   37                         linux,code = <BTN_1>;
   38                         gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
   39                 };
   40         };
   41 
   42         evm_12v0: fixedregulator-evm12v0 {
   43                 /* main supply */
   44                 compatible = "regulator-fixed";
   45                 regulator-name = "evm_12v0";
   46                 regulator-min-microvolt = <12000000>;
   47                 regulator-max-microvolt = <12000000>;
   48                 regulator-always-on;
   49                 regulator-boot-on;
   50         };
   51 
   52         vsys_3v3: fixedregulator-vsys3v3 {
   53                 /* Output of LMS140 */
   54                 compatible = "regulator-fixed";
   55                 regulator-name = "vsys_3v3";
   56                 regulator-min-microvolt = <3300000>;
   57                 regulator-max-microvolt = <3300000>;
   58                 vin-supply = <&evm_12v0>;
   59                 regulator-always-on;
   60                 regulator-boot-on;
   61         };
   62 
   63         vsys_5v0: fixedregulator-vsys5v0 {
   64                 /* Output of LM5140 */
   65                 compatible = "regulator-fixed";
   66                 regulator-name = "vsys_5v0";
   67                 regulator-min-microvolt = <5000000>;
   68                 regulator-max-microvolt = <5000000>;
   69                 vin-supply = <&evm_12v0>;
   70                 regulator-always-on;
   71                 regulator-boot-on;
   72         };
   73 
   74         vdd_mmc1: fixedregulator-sd {
   75                 compatible = "regulator-fixed";
   76                 regulator-name = "vdd_mmc1";
   77                 regulator-min-microvolt = <3300000>;
   78                 regulator-max-microvolt = <3300000>;
   79                 regulator-boot-on;
   80                 enable-active-high;
   81                 vin-supply = <&vsys_3v3>;
   82                 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
   83         };
   84 
   85         vdd_sd_dv_alt: gpio-regulator-TLV71033 {
   86                 compatible = "regulator-gpio";
   87                 pinctrl-names = "default";
   88                 pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
   89                 regulator-name = "tlv71033";
   90                 regulator-min-microvolt = <1800000>;
   91                 regulator-max-microvolt = <3300000>;
   92                 regulator-boot-on;
   93                 vin-supply = <&vsys_5v0>;
   94                 gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
   95                 states = <1800000 0x0>,
   96                          <3300000 0x1>;
   97         };
   98 
   99         sound0: sound@0 {
  100                 compatible = "ti,j721e-cpb-audio";
  101                 model = "j721e-cpb";
  102 
  103                 ti,cpb-mcasp = <&mcasp10>;
  104                 ti,cpb-codec = <&pcm3168a_1>;
  105 
  106                 clocks = <&k3_clks 184 1>,
  107                          <&k3_clks 184 2>, <&k3_clks 184 4>,
  108                          <&k3_clks 157 371>,
  109                          <&k3_clks 157 400>, <&k3_clks 157 401>;
  110                 clock-names = "cpb-mcasp-auxclk",
  111                               "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
  112                               "cpb-codec-scki",
  113                               "cpb-codec-scki-48000", "cpb-codec-scki-44100";
  114         };
  115 
  116         transceiver1: can-phy0 {
  117                 compatible = "ti,tcan1043";
  118                 #phy-cells = <0>;
  119                 max-bitrate = <5000000>;
  120                 pinctrl-names = "default";
  121                 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
  122                 standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
  123                 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
  124         };
  125 
  126         transceiver2: can-phy1 {
  127                 compatible = "ti,tcan1042";
  128                 #phy-cells = <0>;
  129                 max-bitrate = <5000000>;
  130                 pinctrl-names = "default";
  131                 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
  132                 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
  133         };
  134 
  135         transceiver3: can-phy2 {
  136                 compatible = "ti,tcan1043";
  137                 #phy-cells = <0>;
  138                 max-bitrate = <5000000>;
  139                 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
  140                 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
  141         };
  142 
  143         transceiver4: can-phy3 {
  144                 compatible = "ti,tcan1042";
  145                 #phy-cells = <0>;
  146                 max-bitrate = <5000000>;
  147                 pinctrl-names = "default";
  148                 pinctrl-0 = <&main_mcan2_gpio_pins_default>;
  149                 standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
  150         };
  151 
  152         dp_pwr_3v3: regulator-dp-pwr {
  153                 compatible = "regulator-fixed";
  154                 regulator-name = "dp-pwr";
  155                 regulator-min-microvolt = <3300000>;
  156                 regulator-max-microvolt = <3300000>;
  157                 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
  158                 enable-active-high;
  159         };
  160 
  161         dp0: connector {
  162                 compatible = "dp-connector";
  163                 label = "DP0";
  164                 type = "full-size";
  165                 dp-pwr-supply = <&dp_pwr_3v3>;
  166 
  167                 port {
  168                         dp_connector_in: endpoint {
  169                                 remote-endpoint = <&dp0_out>;
  170                         };
  171                 };
  172         };
  173 };
  174 
  175 &main_pmx0 {
  176         sw10_button_pins_default: sw10-button-pins-default {
  177                 pinctrl-single,pins = <
  178                         J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
  179                 >;
  180         };
  181 
  182         main_mmc1_pins_default: main-mmc1-pins-default {
  183                 pinctrl-single,pins = <
  184                         J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
  185                         J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
  186                         J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
  187                         J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
  188                         J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
  189                         J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
  190                         J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
  191                         J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
  192                         J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
  193                 >;
  194         };
  195 
  196         vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
  197                 pinctrl-single,pins = <
  198                         J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
  199                 >;
  200         };
  201 
  202         main_usbss0_pins_default: main-usbss0-pins-default {
  203                 pinctrl-single,pins = <
  204                         J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
  205                         J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
  206                 >;
  207         };
  208 
  209         main_usbss1_pins_default: main-usbss1-pins-default {
  210                 pinctrl-single,pins = <
  211                         J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
  212                 >;
  213         };
  214 
  215         dp0_pins_default: dp0-pins-default {
  216                 pinctrl-single,pins = <
  217                         J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
  218                 >;
  219         };
  220 
  221         main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
  222                 pinctrl-single,pins = <
  223                         J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
  224                 >;
  225         };
  226 
  227         main_i2c0_pins_default: main-i2c0-pins-default {
  228                 pinctrl-single,pins = <
  229                         J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
  230                         J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
  231                 >;
  232         };
  233 
  234         main_i2c1_pins_default: main-i2c1-pins-default {
  235                 pinctrl-single,pins = <
  236                         J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
  237                         J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
  238                 >;
  239         };
  240 
  241         main_i2c3_pins_default: main-i2c3-pins-default {
  242                 pinctrl-single,pins = <
  243                         J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
  244                         J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
  245                 >;
  246         };
  247 
  248         main_i2c6_pins_default: main-i2c6-pins-default {
  249                 pinctrl-single,pins = <
  250                         J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
  251                         J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
  252                 >;
  253         };
  254 
  255         mcasp10_pins_default: mcasp10-pins-default {
  256                 pinctrl-single,pins = <
  257                         J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
  258                         J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
  259                         J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
  260                         J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
  261                         J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
  262                         J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
  263                         J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
  264                         J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
  265                         J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
  266                 >;
  267         };
  268 
  269         audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
  270                 pinctrl-single,pins = <
  271                         J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
  272                 >;
  273         };
  274 
  275         main_mcan0_pins_default: main-mcan0-pins-default {
  276                 pinctrl-single,pins = <
  277                         J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
  278                         J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
  279                 >;
  280         };
  281 
  282         main_mcan2_pins_default: main-mcan2-pins-default {
  283                 pinctrl-single,pins = <
  284                         J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
  285                         J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
  286                 >;
  287         };
  288 
  289         main_mcan2_gpio_pins_default: main-mcan2-gpio-pins-default {
  290                 pinctrl-single,pins = <
  291                         J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
  292                 >;
  293         };
  294 };
  295 
  296 &wkup_pmx0 {
  297         sw11_button_pins_default: sw11-button-pins-default {
  298                 pinctrl-single,pins = <
  299                         J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
  300                 >;
  301         };
  302 
  303         mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
  304                 pinctrl-single,pins = <
  305                         J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
  306                         J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
  307                         J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
  308                         J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
  309                         J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
  310                         J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
  311                         J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
  312                         J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
  313                 >;
  314         };
  315 
  316         mcu_cpsw_pins_default: mcu-cpsw-pins-default {
  317                 pinctrl-single,pins = <
  318                         J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
  319                         J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
  320                         J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
  321                         J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
  322                         J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
  323                         J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
  324                         J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
  325                         J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
  326                         J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
  327                         J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
  328                         J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
  329                         J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
  330                 >;
  331         };
  332 
  333         mcu_mdio_pins_default: mcu-mdio1-pins-default {
  334                 pinctrl-single,pins = <
  335                         J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
  336                         J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
  337                 >;
  338         };
  339 
  340         mcu_mcan0_pins_default: mcu-mcan0-pins-default {
  341                 pinctrl-single,pins = <
  342                         J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
  343                         J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
  344                 >;
  345         };
  346 
  347         mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-pins-default {
  348                 pinctrl-single,pins = <
  349                         J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
  350                         J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
  351                 >;
  352         };
  353 
  354         mcu_mcan1_pins_default: mcu-mcan1-pins-default {
  355                 pinctrl-single,pins = <
  356                         J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
  357                         J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
  358                 >;
  359         };
  360 
  361         mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-pins-default {
  362                 pinctrl-single,pins = <
  363                         J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
  364                 >;
  365         };
  366 };
  367 
  368 &wkup_uart0 {
  369         /* Wakeup UART is used by System firmware */
  370         status = "reserved";
  371 };
  372 
  373 &main_uart0 {
  374         power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
  375 };
  376 
  377 &main_uart3 {
  378         /* UART not brought out */
  379         status = "disabled";
  380 };
  381 
  382 &main_uart5 {
  383         /* UART not brought out */
  384         status = "disabled";
  385 };
  386 
  387 &main_uart6 {
  388         /* UART not brought out */
  389         status = "disabled";
  390 };
  391 
  392 &main_uart7 {
  393         /* UART not brought out */
  394         status = "disabled";
  395 };
  396 
  397 &main_uart8 {
  398         /* UART not brought out */
  399         status = "disabled";
  400 };
  401 
  402 &main_uart9 {
  403         /* UART not brought out */
  404         status = "disabled";
  405 };
  406 
  407 &main_gpio2 {
  408         status = "disabled";
  409 };
  410 
  411 &main_gpio3 {
  412         status = "disabled";
  413 };
  414 
  415 &main_gpio4 {
  416         status = "disabled";
  417 };
  418 
  419 &main_gpio5 {
  420         status = "disabled";
  421 };
  422 
  423 &main_gpio6 {
  424         status = "disabled";
  425 };
  426 
  427 &main_gpio7 {
  428         status = "disabled";
  429 };
  430 
  431 &wkup_gpio1 {
  432         status = "disabled";
  433 };
  434 
  435 &main_sdhci0 {
  436         /* eMMC */
  437         non-removable;
  438         ti,driver-strength-ohm = <50>;
  439         disable-wp;
  440 };
  441 
  442 &main_sdhci1 {
  443         /* SD/MMC */
  444         vmmc-supply = <&vdd_mmc1>;
  445         vqmmc-supply = <&vdd_sd_dv_alt>;
  446         pinctrl-names = "default";
  447         pinctrl-0 = <&main_mmc1_pins_default>;
  448         ti,driver-strength-ohm = <50>;
  449         disable-wp;
  450 };
  451 
  452 &main_sdhci2 {
  453         /* Unused */
  454         status = "disabled";
  455 };
  456 
  457 &usb_serdes_mux {
  458         idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
  459 };
  460 
  461 &serdes_ln_ctrl {
  462         idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
  463                       <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
  464                       <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
  465                       <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
  466                       <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
  467                       <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
  468 };
  469 
  470 &serdes_wiz3 {
  471         typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
  472         typec-dir-debounce-ms = <700>;  /* TUSB321, tCCB_DEFAULT 133 ms */
  473 };
  474 
  475 &serdes3 {
  476         serdes3_usb_link: phy@0 {
  477                 reg = <0>;
  478                 cdns,num-lanes = <2>;
  479                 #phy-cells = <0>;
  480                 cdns,phy-type = <PHY_TYPE_USB3>;
  481                 resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
  482         };
  483 };
  484 
  485 &usbss0 {
  486         pinctrl-names = "default";
  487         pinctrl-0 = <&main_usbss0_pins_default>;
  488         ti,vbus-divider;
  489 };
  490 
  491 &usb0 {
  492         dr_mode = "otg";
  493         maximum-speed = "super-speed";
  494         phys = <&serdes3_usb_link>;
  495         phy-names = "cdns3,usb3-phy";
  496 };
  497 
  498 &usbss1 {
  499         pinctrl-names = "default";
  500         pinctrl-0 = <&main_usbss1_pins_default>;
  501         ti,usb2-only;
  502 };
  503 
  504 &usb1 {
  505         dr_mode = "host";
  506         maximum-speed = "high-speed";
  507 };
  508 
  509 &ospi1 {
  510         pinctrl-names = "default";
  511         pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
  512 
  513         flash@0 {
  514                 compatible = "jedec,spi-nor";
  515                 reg = <0x0>;
  516                 spi-tx-bus-width = <1>;
  517                 spi-rx-bus-width = <4>;
  518                 spi-max-frequency = <40000000>;
  519                 cdns,tshsl-ns = <60>;
  520                 cdns,tsd2d-ns = <60>;
  521                 cdns,tchsh-ns = <60>;
  522                 cdns,tslch-ns = <60>;
  523                 cdns,read-delay = <2>;
  524         };
  525 };
  526 
  527 &tscadc0 {
  528         adc {
  529                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
  530         };
  531 };
  532 
  533 &tscadc1 {
  534         adc {
  535                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
  536         };
  537 };
  538 
  539 &main_i2c0 {
  540         pinctrl-names = "default";
  541         pinctrl-0 = <&main_i2c0_pins_default>;
  542         clock-frequency = <400000>;
  543 
  544         exp1: gpio@20 {
  545                 compatible = "ti,tca6416";
  546                 reg = <0x20>;
  547                 gpio-controller;
  548                 #gpio-cells = <2>;
  549         };
  550 
  551         exp2: gpio@22 {
  552                 compatible = "ti,tca6424";
  553                 reg = <0x22>;
  554                 gpio-controller;
  555                 #gpio-cells = <2>;
  556 
  557                 p09-hog {
  558                         /* P11 - MCASP/TRACE_MUX_S0 */
  559                         gpio-hog;
  560                         gpios = <9 GPIO_ACTIVE_HIGH>;
  561                         output-low;
  562                         line-name = "MCASP/TRACE_MUX_S0";
  563                 };
  564 
  565                 p10-hog {
  566                         /* P12 - MCASP/TRACE_MUX_S1 */
  567                         gpio-hog;
  568                         gpios = <10 GPIO_ACTIVE_HIGH>;
  569                         output-high;
  570                         line-name = "MCASP/TRACE_MUX_S1";
  571                 };
  572         };
  573 };
  574 
  575 &main_i2c1 {
  576         pinctrl-names = "default";
  577         pinctrl-0 = <&main_i2c1_pins_default>;
  578         clock-frequency = <400000>;
  579 
  580         exp4: gpio@20 {
  581                 compatible = "ti,tca6408";
  582                 reg = <0x20>;
  583                 gpio-controller;
  584                 #gpio-cells = <2>;
  585                 pinctrl-names = "default";
  586                 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
  587                 interrupt-parent = <&main_gpio1>;
  588                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
  589                 interrupt-controller;
  590                 #interrupt-cells = <2>;
  591         };
  592 };
  593 
  594 &k3_clks {
  595         /* Confiure AUDIO_EXT_REFCLK2 pin as output */
  596         pinctrl-names = "default";
  597         pinctrl-0 = <&audi_ext_refclk2_pins_default>;
  598 };
  599 
  600 &main_i2c3 {
  601         pinctrl-names = "default";
  602         pinctrl-0 = <&main_i2c3_pins_default>;
  603         clock-frequency = <400000>;
  604 
  605         exp3: gpio@20 {
  606                 compatible = "ti,tca6408";
  607                 reg = <0x20>;
  608                 gpio-controller;
  609                 #gpio-cells = <2>;
  610         };
  611 
  612         pcm3168a_1: audio-codec@44 {
  613                 compatible = "ti,pcm3168a";
  614                 reg = <0x44>;
  615 
  616                 #sound-dai-cells = <1>;
  617 
  618                 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
  619 
  620                 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
  621                 clocks = <&k3_clks 157 371>;
  622                 clock-names = "scki";
  623 
  624                 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
  625                 assigned-clocks = <&k3_clks 157 371>;
  626                 assigned-clock-parents = <&k3_clks 157 400>;
  627                 assigned-clock-rates = <24576000>; /* for 48KHz */
  628 
  629                 VDD1-supply = <&vsys_3v3>;
  630                 VDD2-supply = <&vsys_3v3>;
  631                 VCCAD1-supply = <&vsys_5v0>;
  632                 VCCAD2-supply = <&vsys_5v0>;
  633                 VCCDA1-supply = <&vsys_5v0>;
  634                 VCCDA2-supply = <&vsys_5v0>;
  635         };
  636 };
  637 
  638 &main_i2c6 {
  639         pinctrl-names = "default";
  640         pinctrl-0 = <&main_i2c6_pins_default>;
  641         clock-frequency = <400000>;
  642 
  643         exp5: gpio@20 {
  644                 compatible = "ti,tca6408";
  645                 reg = <0x20>;
  646                 gpio-controller;
  647                 #gpio-cells = <2>;
  648         };
  649 };
  650 
  651 &mcu_cpsw {
  652         pinctrl-names = "default";
  653         pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
  654 };
  655 
  656 &davinci_mdio {
  657         phy0: ethernet-phy@0 {
  658                 reg = <0>;
  659                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
  660                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  661         };
  662 };
  663 
  664 &cpsw_port1 {
  665         phy-mode = "rgmii-rxid";
  666         phy-handle = <&phy0>;
  667 };
  668 
  669 &dss {
  670         /*
  671          * These clock assignments are chosen to enable the following outputs:
  672          *
  673          * VP0 - DisplayPort SST
  674          * VP1 - DPI0
  675          * VP2 - DSI
  676          * VP3 - DPI1
  677          */
  678 
  679         assigned-clocks = <&k3_clks 152 1>,
  680                           <&k3_clks 152 4>,
  681                           <&k3_clks 152 9>,
  682                           <&k3_clks 152 13>;
  683         assigned-clock-parents = <&k3_clks 152 2>,      /* PLL16_HSDIV0 */
  684                                  <&k3_clks 152 6>,      /* PLL19_HSDIV0 */
  685                                  <&k3_clks 152 11>,     /* PLL18_HSDIV0 */
  686                                  <&k3_clks 152 18>;     /* PLL23_HSDIV0 */
  687 };
  688 
  689 &dss_ports {
  690         port {
  691                 dpi0_out: endpoint {
  692                         remote-endpoint = <&dp0_in>;
  693                 };
  694         };
  695 };
  696 
  697 &dp0_ports {
  698         #address-cells = <1>;
  699         #size-cells = <0>;
  700 
  701         port@0 {
  702                 reg = <0>;
  703                 dp0_in: endpoint {
  704                         remote-endpoint = <&dpi0_out>;
  705                 };
  706         };
  707 
  708         port@4 {
  709                 reg = <4>;
  710                 dp0_out: endpoint {
  711                         remote-endpoint = <&dp_connector_in>;
  712                 };
  713         };
  714 };
  715 
  716 &mcasp0 {
  717         status = "disabled";
  718 };
  719 
  720 &mcasp1 {
  721         status = "disabled";
  722 };
  723 
  724 &mcasp2 {
  725         status = "disabled";
  726 };
  727 
  728 &mcasp3 {
  729         status = "disabled";
  730 };
  731 
  732 &mcasp4 {
  733         status = "disabled";
  734 };
  735 
  736 &mcasp5 {
  737         status = "disabled";
  738 };
  739 
  740 &mcasp6 {
  741         status = "disabled";
  742 };
  743 
  744 &mcasp7 {
  745         status = "disabled";
  746 };
  747 
  748 &mcasp8 {
  749         status = "disabled";
  750 };
  751 
  752 &mcasp9 {
  753         status = "disabled";
  754 };
  755 
  756 &mcasp10 {
  757         #sound-dai-cells = <0>;
  758 
  759         pinctrl-names = "default";
  760         pinctrl-0 = <&mcasp10_pins_default>;
  761 
  762         op-mode = <0>;          /* MCASP_IIS_MODE */
  763         tdm-slots = <2>;
  764         auxclk-fs-ratio = <256>;
  765 
  766         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
  767                 1 1 1 1
  768                 2 2 2 0
  769         >;
  770         tx-num-evt = <0>;
  771         rx-num-evt = <0>;
  772 };
  773 
  774 &mcasp11 {
  775         status = "disabled";
  776 };
  777 
  778 &cmn_refclk1 {
  779         clock-frequency = <100000000>;
  780 };
  781 
  782 &wiz0_pll1_refclk {
  783         assigned-clocks = <&wiz0_pll1_refclk>;
  784         assigned-clock-parents = <&cmn_refclk1>;
  785 };
  786 
  787 &wiz0_refclk_dig {
  788         assigned-clocks = <&wiz0_refclk_dig>;
  789         assigned-clock-parents = <&cmn_refclk1>;
  790 };
  791 
  792 &wiz1_pll1_refclk {
  793         assigned-clocks = <&wiz1_pll1_refclk>;
  794         assigned-clock-parents = <&cmn_refclk1>;
  795 };
  796 
  797 &wiz1_refclk_dig {
  798         assigned-clocks = <&wiz1_refclk_dig>;
  799         assigned-clock-parents = <&cmn_refclk1>;
  800 };
  801 
  802 &wiz2_pll1_refclk {
  803         assigned-clocks = <&wiz2_pll1_refclk>;
  804         assigned-clock-parents = <&cmn_refclk1>;
  805 };
  806 
  807 &wiz2_refclk_dig {
  808         assigned-clocks = <&wiz2_refclk_dig>;
  809         assigned-clock-parents = <&cmn_refclk1>;
  810 };
  811 
  812 &serdes0 {
  813         assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
  814         assigned-clock-parents = <&wiz0_pll1_refclk>;
  815 
  816         serdes0_pcie_link: phy@0 {
  817                 reg = <0>;
  818                 cdns,num-lanes = <1>;
  819                 #phy-cells = <0>;
  820                 cdns,phy-type = <PHY_TYPE_PCIE>;
  821                 resets = <&serdes_wiz0 1>;
  822         };
  823 };
  824 
  825 &serdes1 {
  826         assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
  827         assigned-clock-parents = <&wiz1_pll1_refclk>;
  828 
  829         serdes1_pcie_link: phy@0 {
  830                 reg = <0>;
  831                 cdns,num-lanes = <2>;
  832                 #phy-cells = <0>;
  833                 cdns,phy-type = <PHY_TYPE_PCIE>;
  834                 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
  835         };
  836 };
  837 
  838 &serdes2 {
  839         assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
  840         assigned-clock-parents = <&wiz2_pll1_refclk>;
  841 
  842         serdes2_pcie_link: phy@0 {
  843                 reg = <0>;
  844                 cdns,num-lanes = <2>;
  845                 #phy-cells = <0>;
  846                 cdns,phy-type = <PHY_TYPE_PCIE>;
  847                 resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
  848         };
  849 };
  850 
  851 &serdes4 {
  852         torrent_phy_dp: phy@0 {
  853                 reg = <0>;
  854                 resets = <&serdes_wiz4 1>;
  855                 cdns,phy-type = <PHY_TYPE_DP>;
  856                 cdns,num-lanes = <4>;
  857                 cdns,max-bit-rate = <5400>;
  858                 #phy-cells = <0>;
  859         };
  860 };
  861 
  862 &mhdp {
  863         phys = <&torrent_phy_dp>;
  864         phy-names = "dpphy";
  865         pinctrl-names = "default";
  866         pinctrl-0 = <&dp0_pins_default>;
  867 };
  868 
  869 &pcie0_rc {
  870         reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
  871         phys = <&serdes0_pcie_link>;
  872         phy-names = "pcie-phy";
  873         num-lanes = <1>;
  874 };
  875 
  876 &pcie1_rc {
  877         reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
  878         phys = <&serdes1_pcie_link>;
  879         phy-names = "pcie-phy";
  880         num-lanes = <2>;
  881 };
  882 
  883 &pcie2_rc {
  884         reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
  885         phys = <&serdes2_pcie_link>;
  886         phy-names = "pcie-phy";
  887         num-lanes = <2>;
  888 };
  889 
  890 &pcie0_ep {
  891         phys = <&serdes0_pcie_link>;
  892         phy-names = "pcie-phy";
  893         num-lanes = <1>;
  894         status = "disabled";
  895 };
  896 
  897 &pcie1_ep {
  898         phys = <&serdes1_pcie_link>;
  899         phy-names = "pcie-phy";
  900         num-lanes = <2>;
  901         status = "disabled";
  902 };
  903 
  904 &pcie2_ep {
  905         phys = <&serdes2_pcie_link>;
  906         phy-names = "pcie-phy";
  907         num-lanes = <2>;
  908         status = "disabled";
  909 };
  910 
  911 &pcie3_rc {
  912         status = "disabled";
  913 };
  914 
  915 &pcie3_ep {
  916         status = "disabled";
  917 };
  918 
  919 &icssg0_mdio {
  920         status = "disabled";
  921 };
  922 
  923 &icssg1_mdio {
  924         status = "disabled";
  925 };
  926 
  927 &mcu_mcan0 {
  928         pinctrl-names = "default";
  929         pinctrl-0 = <&mcu_mcan0_pins_default>;
  930         phys = <&transceiver1>;
  931 };
  932 
  933 &mcu_mcan1 {
  934         pinctrl-names = "default";
  935         pinctrl-0 = <&mcu_mcan1_pins_default>;
  936         phys = <&transceiver2>;
  937 };
  938 
  939 &main_mcan0 {
  940         pinctrl-names = "default";
  941         pinctrl-0 = <&main_mcan0_pins_default>;
  942         phys = <&transceiver3>;
  943 };
  944 
  945 &main_mcan1 {
  946         status = "disabled";
  947 };
  948 
  949 &main_mcan2 {
  950         pinctrl-names = "default";
  951         pinctrl-0 = <&main_mcan2_pins_default>;
  952         phys = <&transceiver4>;
  953 };
  954 
  955 &main_mcan3 {
  956         status = "disabled";
  957 };
  958 
  959 &main_mcan4 {
  960         status = "disabled";
  961 };
  962 
  963 &main_mcan5 {
  964         status = "disabled";
  965 };
  966 
  967 &main_mcan6 {
  968         status = "disabled";
  969 };
  970 
  971 &main_mcan7 {
  972         status = "disabled";
  973 };
  974 
  975 &main_mcan8 {
  976         status = "disabled";
  977 };
  978 
  979 &main_mcan9 {
  980         status = "disabled";
  981 };
  982 
  983 &main_mcan10 {
  984         status = "disabled";
  985 };
  986 
  987 &main_mcan11 {
  988         status = "disabled";
  989 };
  990 
  991 &main_mcan12 {
  992         status = "disabled";
  993 };
  994 
  995 &main_mcan13 {
  996         status = "disabled";
  997 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/ti/k3-j721e-common-proc-board.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/ti/k3-j721e-common-proc-board.dts
