k3-j721e-som-p0.dtsi

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/
    4  */
    5 
    6 /dts-v1/;
    7 
    8 #include "k3-j721e.dtsi"
    9 
   10 / {
   11         memory@80000000 {
   12                 device_type = "memory";
   13                 /* 4G RAM */
   14                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
   15                       <0x00000008 0x80000000 0x00000000 0x80000000>;
   16         };
   17 
   18         reserved_memory: reserved-memory {
   19                 #address-cells = <2>;
   20                 #size-cells = <2>;
   21                 ranges;
   22 
   23                 secure_ddr: optee@9e800000 {
   24                         reg = <0x00 0x9e800000 0x00 0x01800000>;
   25                         alignment = <0x1000>;
   26                         no-map;
   27                 };
   28 
   29                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
   30                         compatible = "shared-dma-pool";
   31                         reg = <0x00 0xa0000000 0x00 0x100000>;
   32                         no-map;
   33                 };
   34 
   35                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
   36                         compatible = "shared-dma-pool";
   37                         reg = <0x00 0xa0100000 0x00 0xf00000>;
   38                         no-map;
   39                 };
   40 
   41                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
   42                         compatible = "shared-dma-pool";
   43                         reg = <0x00 0xa1000000 0x00 0x100000>;
   44                         no-map;
   45                 };
   46 
   47                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
   48                         compatible = "shared-dma-pool";
   49                         reg = <0x00 0xa1100000 0x00 0xf00000>;
   50                         no-map;
   51                 };
   52 
   53                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
   54                         compatible = "shared-dma-pool";
   55                         reg = <0x00 0xa2000000 0x00 0x100000>;
   56                         no-map;
   57                 };
   58 
   59                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
   60                         compatible = "shared-dma-pool";
   61                         reg = <0x00 0xa2100000 0x00 0xf00000>;
   62                         no-map;
   63                 };
   64 
   65                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
   66                         compatible = "shared-dma-pool";
   67                         reg = <0x00 0xa3000000 0x00 0x100000>;
   68                         no-map;
   69                 };
   70 
   71                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
   72                         compatible = "shared-dma-pool";
   73                         reg = <0x00 0xa3100000 0x00 0xf00000>;
   74                         no-map;
   75                 };
   76 
   77                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
   78                         compatible = "shared-dma-pool";
   79                         reg = <0x00 0xa4000000 0x00 0x100000>;
   80                         no-map;
   81                 };
   82 
   83                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
   84                         compatible = "shared-dma-pool";
   85                         reg = <0x00 0xa4100000 0x00 0xf00000>;
   86                         no-map;
   87                 };
   88 
   89                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
   90                         compatible = "shared-dma-pool";
   91                         reg = <0x00 0xa5000000 0x00 0x100000>;
   92                         no-map;
   93                 };
   94 
   95                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
   96                         compatible = "shared-dma-pool";
   97                         reg = <0x00 0xa5100000 0x00 0xf00000>;
   98                         no-map;
   99                 };
  100 
  101                 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
  102                         compatible = "shared-dma-pool";
  103                         reg = <0x00 0xa6000000 0x00 0x100000>;
  104                         no-map;
  105                 };
  106 
  107                 c66_0_memory_region: c66-memory@a6100000 {
  108                         compatible = "shared-dma-pool";
  109                         reg = <0x00 0xa6100000 0x00 0xf00000>;
  110                         no-map;
  111                 };
  112 
  113                 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
  114                         compatible = "shared-dma-pool";
  115                         reg = <0x00 0xa7000000 0x00 0x100000>;
  116                         no-map;
  117                 };
  118 
  119                 c66_1_memory_region: c66-memory@a7100000 {
  120                         compatible = "shared-dma-pool";
  121                         reg = <0x00 0xa7100000 0x00 0xf00000>;
  122                         no-map;
  123                 };
  124 
  125                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
  126                         compatible = "shared-dma-pool";
  127                         reg = <0x00 0xa8000000 0x00 0x100000>;
  128                         no-map;
  129                 };
  130 
  131                 c71_0_memory_region: c71-memory@a8100000 {
  132                         compatible = "shared-dma-pool";
  133                         reg = <0x00 0xa8100000 0x00 0xf00000>;
  134                         no-map;
  135                 };
  136 
  137                 rtos_ipc_memory_region: ipc-memories@aa000000 {
  138                         reg = <0x00 0xaa000000 0x00 0x01c00000>;
  139                         alignment = <0x1000>;
  140                         no-map;
  141                 };
  142         };
  143 };
  144 
  145 &wkup_pmx0 {
  146         wkup_i2c0_pins_default: wkup-i2c0-pins-default {
  147                 pinctrl-single,pins = <
  148                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
  149                         J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
  150                 >;
  151         };
  152 
  153         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
  154                 pinctrl-single,pins = <
  155                         J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
  156                         J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
  157                         J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
  158                         J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
  159                         J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
  160                         J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
  161                         J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
  162                         J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
  163                         J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
  164                         J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
  165                         J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
  166                 >;
  167         };
  168 };
  169 
  170 &ospi0 {
  171         pinctrl-names = "default";
  172         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
  173 
  174         flash@0 {
  175                 compatible = "jedec,spi-nor";
  176                 reg = <0x0>;
  177                 spi-tx-bus-width = <8>;
  178                 spi-rx-bus-width = <8>;
  179                 spi-max-frequency = <25000000>;
  180                 cdns,tshsl-ns = <60>;
  181                 cdns,tsd2d-ns = <60>;
  182                 cdns,tchsh-ns = <60>;
  183                 cdns,tslch-ns = <60>;
  184                 cdns,read-delay = <0>;
  185         };
  186 };
  187 
  188 &mailbox0_cluster0 {
  189         interrupts = <436>;
  190 
  191         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
  192                 ti,mbox-rx = <0 0 0>;
  193                 ti,mbox-tx = <1 0 0>;
  194         };
  195 
  196         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
  197                 ti,mbox-rx = <2 0 0>;
  198                 ti,mbox-tx = <3 0 0>;
  199         };
  200 };
  201 
  202 &mailbox0_cluster1 {
  203         interrupts = <432>;
  204 
  205         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
  206                 ti,mbox-rx = <0 0 0>;
  207                 ti,mbox-tx = <1 0 0>;
  208         };
  209 
  210         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
  211                 ti,mbox-rx = <2 0 0>;
  212                 ti,mbox-tx = <3 0 0>;
  213         };
  214 };
  215 
  216 &mailbox0_cluster2 {
  217         interrupts = <428>;
  218 
  219         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
  220                 ti,mbox-rx = <0 0 0>;
  221                 ti,mbox-tx = <1 0 0>;
  222         };
  223 
  224         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
  225                 ti,mbox-rx = <2 0 0>;
  226                 ti,mbox-tx = <3 0 0>;
  227         };
  228 };
  229 
  230 &mailbox0_cluster3 {
  231         interrupts = <424>;
  232 
  233         mbox_c66_0: mbox-c66-0 {
  234                 ti,mbox-rx = <0 0 0>;
  235                 ti,mbox-tx = <1 0 0>;
  236         };
  237 
  238         mbox_c66_1: mbox-c66-1 {
  239                 ti,mbox-rx = <2 0 0>;
  240                 ti,mbox-tx = <3 0 0>;
  241         };
  242 };
  243 
  244 &mailbox0_cluster4 {
  245         interrupts = <420>;
  246 
  247         mbox_c71_0: mbox-c71-0 {
  248                 ti,mbox-rx = <0 0 0>;
  249                 ti,mbox-tx = <1 0 0>;
  250         };
  251 };
  252 
  253 &mailbox0_cluster5 {
  254         status = "disabled";
  255 };
  256 
  257 &mailbox0_cluster6 {
  258         status = "disabled";
  259 };
  260 
  261 &mailbox0_cluster7 {
  262         status = "disabled";
  263 };
  264 
  265 &mailbox0_cluster8 {
  266         status = "disabled";
  267 };
  268 
  269 &mailbox0_cluster9 {
  270         status = "disabled";
  271 };
  272 
  273 &mailbox0_cluster10 {
  274         status = "disabled";
  275 };
  276 
  277 &mailbox0_cluster11 {
  278         status = "disabled";
  279 };
  280 
  281 &mcu_r5fss0_core0 {
  282         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
  283         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
  284                         <&mcu_r5fss0_core0_memory_region>;
  285 };
  286 
  287 &mcu_r5fss0_core1 {
  288         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
  289         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
  290                         <&mcu_r5fss0_core1_memory_region>;
  291 };
  292 
  293 &main_r5fss0_core0 {
  294         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
  295         memory-region = <&main_r5fss0_core0_dma_memory_region>,
  296                         <&main_r5fss0_core0_memory_region>;
  297 };
  298 
  299 &main_r5fss0_core1 {
  300         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
  301         memory-region = <&main_r5fss0_core1_dma_memory_region>,
  302                         <&main_r5fss0_core1_memory_region>;
  303 };
  304 
  305 &main_r5fss1_core0 {
  306         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
  307         memory-region = <&main_r5fss1_core0_dma_memory_region>,
  308                         <&main_r5fss1_core0_memory_region>;
  309 };
  310 
  311 &main_r5fss1_core1 {
  312         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
  313         memory-region = <&main_r5fss1_core1_dma_memory_region>,
  314                         <&main_r5fss1_core1_memory_region>;
  315 };
  316 
  317 &c66_0 {
  318         mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
  319         memory-region = <&c66_0_dma_memory_region>,
  320                         <&c66_0_memory_region>;
  321 };
  322 
  323 &c66_1 {
  324         mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
  325         memory-region = <&c66_1_dma_memory_region>,
  326                         <&c66_1_memory_region>;
  327 };
  328 
  329 &c71_0 {
  330         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
  331         memory-region = <&c71_0_dma_memory_region>,
  332                         <&c71_0_memory_region>;
  333 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/ti/k3-j721e-som-p0.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/ti/k3-j721e-som-p0.dtsi
