zynqmp-sck-kv-g-revA.dts

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    1 // SPDX-License-Identifier: GPL-2.0
    2 /*
    3  * dts file for KV260 revA Carrier Card
    4  *
    5  * (C) Copyright 2020 - 2021, Xilinx, Inc.
    6  *
    7  * SD level shifter:
    8  * "A" – A01 board un-modified (NXP)
    9  * "Y" – A01 board modified with legacy interposer (Nexperia)
   10  * "Z" – A01 board modified with Diode interposer
   11  *
   12  * Michal Simek <michal.simek@xilinx.com>
   13  */
   14 
   15 #include <dt-bindings/gpio/gpio.h>
   16 #include <dt-bindings/net/ti-dp83867.h>
   17 #include <dt-bindings/phy/phy.h>
   18 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
   19 
   20 /dts-v1/;
   21 /plugin/;
   22 
   23 &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
   24         #address-cells = <1>;
   25         #size-cells = <0>;
   26         pinctrl-names = "default", "gpio";
   27         pinctrl-0 = <&pinctrl_i2c1_default>;
   28         pinctrl-1 = <&pinctrl_i2c1_gpio>;
   29         scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
   30         sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
   31 
   32         /* u14 - 0x40 - ina260 */
   33         /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
   34 };
   35 
   36 &amba {
   37         si5332_0: si5332_0 { /* u17 */
   38                 compatible = "fixed-clock";
   39                 #clock-cells = <0>;
   40                 clock-frequency = <125000000>;
   41         };
   42 
   43         si5332_1: si5332_1 { /* u17 */
   44                 compatible = "fixed-clock";
   45                 #clock-cells = <0>;
   46                 clock-frequency = <25000000>;
   47         };
   48 
   49         si5332_2: si5332_2 { /* u17 */
   50                 compatible = "fixed-clock";
   51                 #clock-cells = <0>;
   52                 clock-frequency = <48000000>;
   53         };
   54 
   55         si5332_3: si5332_3 { /* u17 */
   56                 compatible = "fixed-clock";
   57                 #clock-cells = <0>;
   58                 clock-frequency = <24000000>;
   59         };
   60 
   61         si5332_4: si5332_4 { /* u17 */
   62                 compatible = "fixed-clock";
   63                 #clock-cells = <0>;
   64                 clock-frequency = <26000000>;
   65         };
   66 
   67         si5332_5: si5332_5 { /* u17 */
   68                 compatible = "fixed-clock";
   69                 #clock-cells = <0>;
   70                 clock-frequency = <27000000>;
   71         };
   72 };
   73 
   74 /* DP/USB 3.0 and SATA */
   75 &psgtr {
   76         status = "okay";
   77         /* pcie, usb3, sata */
   78         clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
   79         clock-names = "ref0", "ref1", "ref2";
   80 };
   81 
   82 &sata {
   83         status = "okay";
   84         /* SATA OOB timing settings */
   85         ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
   86         ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
   87         ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
   88         ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
   89         ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
   90         ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
   91         ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
   92         ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
   93         phy-names = "sata-phy";
   94         phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
   95 };
   96 
   97 &zynqmp_dpsub {
   98         status = "disabled";
   99         phy-names = "dp-phy0", "dp-phy1";
  100         phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
  101 };
  102 
  103 &zynqmp_dpdma {
  104         status = "okay";
  105 };
  106 
  107 &usb0 {
  108         status = "okay";
  109         pinctrl-names = "default";
  110         pinctrl-0 = <&pinctrl_usb0_default>;
  111         phy-names = "usb3-phy";
  112         phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
  113         /* missing usb5744 - u43 */
  114 };
  115 
  116 &dwc3_0 {
  117         status = "okay";
  118         dr_mode = "host";
  119         snps,usb3_lpm_capable;
  120         maximum-speed = "super-speed";
  121 };
  122 
  123 &sdhci1 { /* on CC with tuned parameters */
  124         status = "okay";
  125         pinctrl-names = "default";
  126         pinctrl-0 = <&pinctrl_sdhci1_default>;
  127         /*
  128          * SD 3.0 requires level shifter and this property
  129          * should be removed if the board has level shifter and
  130          * need to work in UHS mode
  131          */
  132         no-1-8-v;
  133         disable-wp;
  134         xlnx,mio-bank = <1>;
  135 };
  136 
  137 &gem3 { /* required by spec */
  138         status = "okay";
  139         pinctrl-names = "default";
  140         pinctrl-0 = <&pinctrl_gem3_default>;
  141         phy-handle = <&phy0>;
  142         phy-mode = "rgmii-id";
  143 
  144         mdio: mdio {
  145                 #address-cells = <1>;
  146                 #size-cells = <0>;
  147                 reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
  148                 reset-delay-us = <2>;
  149 
  150                 phy0: ethernet-phy@1 {
  151                         #phy-cells = <1>;
  152                         reg = <1>;
  153                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
  154                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
  155                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
  156                         ti,dp83867-rxctrl-strap-quirk;
  157                 };
  158         };
  159 };
  160 
  161 &pinctrl0 { /* required by spec */
  162         status = "okay";
  163 
  164         pinctrl_uart1_default: uart1-default {
  165                 conf {
  166                         groups = "uart1_9_grp";
  167                         slew-rate = <SLEW_RATE_SLOW>;
  168                         power-source = <IO_STANDARD_LVCMOS18>;
  169                         drive-strength = <12>;
  170                 };
  171 
  172                 conf-rx {
  173                         pins = "MIO37";
  174                         bias-high-impedance;
  175                 };
  176 
  177                 conf-tx {
  178                         pins = "MIO36";
  179                         bias-disable;
  180                 };
  181 
  182                 mux {
  183                         groups = "uart1_9_grp";
  184                         function = "uart1";
  185                 };
  186         };
  187 
  188         pinctrl_i2c1_default: i2c1-default {
  189                 conf {
  190                         groups = "i2c1_6_grp";
  191                         bias-pull-up;
  192                         slew-rate = <SLEW_RATE_SLOW>;
  193                         power-source = <IO_STANDARD_LVCMOS18>;
  194                 };
  195 
  196                 mux {
  197                         groups = "i2c1_6_grp";
  198                         function = "i2c1";
  199                 };
  200         };
  201 
  202         pinctrl_i2c1_gpio: i2c1-gpio {
  203                 conf {
  204                         groups = "gpio0_24_grp", "gpio0_25_grp";
  205                         slew-rate = <SLEW_RATE_SLOW>;
  206                         power-source = <IO_STANDARD_LVCMOS18>;
  207                 };
  208 
  209                 mux {
  210                         groups = "gpio0_24_grp", "gpio0_25_grp";
  211                         function = "gpio0";
  212                 };
  213         };
  214 
  215         pinctrl_gem3_default: gem3-default {
  216                 conf {
  217                         groups = "ethernet3_0_grp";
  218                         slew-rate = <SLEW_RATE_SLOW>;
  219                         power-source = <IO_STANDARD_LVCMOS18>;
  220                 };
  221 
  222                 conf-rx {
  223                         pins = "MIO70", "MIO72", "MIO74";
  224                         bias-high-impedance;
  225                         low-power-disable;
  226                 };
  227 
  228                 conf-bootstrap {
  229                         pins = "MIO71", "MIO73", "MIO75";
  230                         bias-disable;
  231                         low-power-disable;
  232                 };
  233 
  234                 conf-tx {
  235                         pins = "MIO64", "MIO65", "MIO66",
  236                                 "MIO67", "MIO68", "MIO69";
  237                         bias-disable;
  238                         low-power-enable;
  239                 };
  240 
  241                 conf-mdio {
  242                         groups = "mdio3_0_grp";
  243                         slew-rate = <SLEW_RATE_SLOW>;
  244                         power-source = <IO_STANDARD_LVCMOS18>;
  245                         bias-disable;
  246                 };
  247 
  248                 mux-mdio {
  249                         function = "mdio3";
  250                         groups = "mdio3_0_grp";
  251                 };
  252 
  253                 mux {
  254                         function = "ethernet3";
  255                         groups = "ethernet3_0_grp";
  256                 };
  257         };
  258 
  259         pinctrl_usb0_default: usb0-default {
  260                 conf {
  261                         groups = "usb0_0_grp";
  262                         slew-rate = <SLEW_RATE_SLOW>;
  263                         power-source = <IO_STANDARD_LVCMOS18>;
  264                 };
  265 
  266                 conf-rx {
  267                         pins = "MIO52", "MIO53", "MIO55";
  268                         bias-high-impedance;
  269                 };
  270 
  271                 conf-tx {
  272                         pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
  273                         "MIO60", "MIO61", "MIO62", "MIO63";
  274                         bias-disable;
  275                 };
  276 
  277                 mux {
  278                         groups = "usb0_0_grp";
  279                         function = "usb0";
  280                 };
  281         };
  282 
  283         pinctrl_sdhci1_default: sdhci1-default {
  284                 conf {
  285                         groups = "sdio1_0_grp";
  286                         slew-rate = <SLEW_RATE_SLOW>;
  287                         power-source = <IO_STANDARD_LVCMOS18>;
  288                         bias-disable;
  289                 };
  290 
  291                 conf-cd {
  292                         groups = "sdio1_cd_0_grp";
  293                         bias-high-impedance;
  294                         bias-pull-up;
  295                         slew-rate = <SLEW_RATE_SLOW>;
  296                         power-source = <IO_STANDARD_LVCMOS18>;
  297                 };
  298 
  299                 mux-cd {
  300                         groups = "sdio1_cd_0_grp";
  301                         function = "sdio1_cd";
  302                 };
  303 
  304                 mux {
  305                         groups = "sdio1_0_grp";
  306                         function = "sdio1";
  307                 };
  308         };
  309 };
  310 
  311 &uart1 {
  312         status = "okay";
  313         pinctrl-names = "default";
  314         pinctrl-0 = <&pinctrl_uart1_default>;
  315 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/xilinx/zynqmp-sck-kv-g-revA.dts