zynqmp-zc1751-xm019-dc5.dts

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    1 // SPDX-License-Identifier: GPL-2.0+
    2 /*
    3  * dts file for Xilinx ZynqMP zc1751-xm019-dc5
    4  *
    5  * (C) Copyright 2015 - 2021, Xilinx, Inc.
    6  *
    7  * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
    8  * Michal Simek <michal.simek@xilinx.com>
    9  */
   10 
   11 /dts-v1/;
   12 
   13 #include "zynqmp.dtsi"
   14 #include "zynqmp-clk-ccf.dtsi"
   15 #include <dt-bindings/gpio/gpio.h>
   16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
   17 
   18 / {
   19         model = "ZynqMP zc1751-xm019-dc5 RevA";
   20         compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
   21 
   22         aliases {
   23                 ethernet0 = &gem1;
   24                 i2c0 = &i2c0;
   25                 i2c1 = &i2c1;
   26                 mmc0 = &sdhci0;
   27                 serial0 = &uart0;
   28                 serial1 = &uart1;
   29         };
   30 
   31         chosen {
   32                 bootargs = "earlycon";
   33                 stdout-path = "serial0:115200n8";
   34         };
   35 
   36         memory@0 {
   37                 device_type = "memory";
   38                 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
   39         };
   40 };
   41 
   42 &fpd_dma_chan1 {
   43         status = "okay";
   44 };
   45 
   46 &fpd_dma_chan2 {
   47         status = "okay";
   48 };
   49 
   50 &fpd_dma_chan3 {
   51         status = "okay";
   52 };
   53 
   54 &fpd_dma_chan4 {
   55         status = "okay";
   56 };
   57 
   58 &fpd_dma_chan5 {
   59         status = "okay";
   60 };
   61 
   62 &fpd_dma_chan6 {
   63         status = "okay";
   64 };
   65 
   66 &fpd_dma_chan7 {
   67         status = "okay";
   68 };
   69 
   70 &fpd_dma_chan8 {
   71         status = "okay";
   72 };
   73 
   74 &gem1 {
   75         status = "okay";
   76         phy-handle = <&phy0>;
   77         phy-mode = "rgmii-id";
   78         pinctrl-names = "default";
   79         pinctrl-0 = <&pinctrl_gem1_default>;
   80         phy0: ethernet-phy@0 {
   81                 reg = <0>;
   82         };
   83 };
   84 
   85 &gpio {
   86         status = "okay";
   87 };
   88 
   89 &i2c0 {
   90         status = "okay";
   91         pinctrl-names = "default", "gpio";
   92         pinctrl-0 = <&pinctrl_i2c0_default>;
   93         pinctrl-1 = <&pinctrl_i2c0_gpio>;
   94         scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
   95         sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
   96 };
   97 
   98 &i2c1 {
   99         status = "okay";
  100         pinctrl-names = "default", "gpio";
  101         pinctrl-0 = <&pinctrl_i2c1_default>;
  102         pinctrl-1 = <&pinctrl_i2c1_gpio>;
  103         scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
  104         sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
  105 
  106 };
  107 
  108 &pinctrl0 {
  109         status = "okay";
  110         pinctrl_i2c0_default: i2c0-default {
  111                 mux {
  112                         groups = "i2c0_18_grp";
  113                         function = "i2c0";
  114                 };
  115 
  116                 conf {
  117                         groups = "i2c0_18_grp";
  118                         bias-pull-up;
  119                         slew-rate = <SLEW_RATE_SLOW>;
  120                         power-source = <IO_STANDARD_LVCMOS18>;
  121                 };
  122         };
  123 
  124         pinctrl_i2c0_gpio: i2c0-gpio {
  125                 mux {
  126                         groups = "gpio0_74_grp", "gpio0_75_grp";
  127                         function = "gpio0";
  128                 };
  129 
  130                 conf {
  131                         groups = "gpio0_74_grp", "gpio0_75_grp";
  132                         slew-rate = <SLEW_RATE_SLOW>;
  133                         power-source = <IO_STANDARD_LVCMOS18>;
  134                 };
  135         };
  136 
  137         pinctrl_i2c1_default: i2c1-default {
  138                 mux {
  139                         groups = "i2c1_19_grp";
  140                         function = "i2c1";
  141                 };
  142 
  143                 conf {
  144                         groups = "i2c1_19_grp";
  145                         bias-pull-up;
  146                         slew-rate = <SLEW_RATE_SLOW>;
  147                         power-source = <IO_STANDARD_LVCMOS18>;
  148                 };
  149         };
  150 
  151         pinctrl_i2c1_gpio: i2c1-gpio {
  152                 mux {
  153                         groups = "gpio0_76_grp", "gpio0_77_grp";
  154                         function = "gpio0";
  155                 };
  156 
  157                 conf {
  158                         groups = "gpio0_76_grp", "gpio0_77_grp";
  159                         slew-rate = <SLEW_RATE_SLOW>;
  160                         power-source = <IO_STANDARD_LVCMOS18>;
  161                 };
  162         };
  163 
  164         pinctrl_uart0_default: uart0-default {
  165                 mux {
  166                         groups = "uart0_17_grp";
  167                         function = "uart0";
  168                 };
  169 
  170                 conf {
  171                         groups = "uart0_17_grp";
  172                         slew-rate = <SLEW_RATE_SLOW>;
  173                         power-source = <IO_STANDARD_LVCMOS18>;
  174                 };
  175 
  176                 conf-rx {
  177                         pins = "MIO70";
  178                         bias-high-impedance;
  179                 };
  180 
  181                 conf-tx {
  182                         pins = "MIO71";
  183                         bias-disable;
  184                 };
  185         };
  186 
  187         pinctrl_uart1_default: uart1-default {
  188                 mux {
  189                         groups = "uart1_18_grp";
  190                         function = "uart1";
  191                 };
  192 
  193                 conf {
  194                         groups = "uart1_18_grp";
  195                         slew-rate = <SLEW_RATE_SLOW>;
  196                         power-source = <IO_STANDARD_LVCMOS18>;
  197                 };
  198 
  199                 conf-rx {
  200                         pins = "MIO73";
  201                         bias-high-impedance;
  202                 };
  203 
  204                 conf-tx {
  205                         pins = "MIO72";
  206                         bias-disable;
  207                 };
  208         };
  209 
  210         pinctrl_gem1_default: gem1-default {
  211                 mux {
  212                         function = "ethernet1";
  213                         groups = "ethernet1_0_grp";
  214                 };
  215 
  216                 conf {
  217                         groups = "ethernet1_0_grp";
  218                         slew-rate = <SLEW_RATE_SLOW>;
  219                         power-source = <IO_STANDARD_LVCMOS18>;
  220                 };
  221 
  222                 conf-rx {
  223                         pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
  224                                                                         "MIO49";
  225                         bias-high-impedance;
  226                         low-power-disable;
  227                 };
  228 
  229                 conf-tx {
  230                         pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
  231                                                                         "MIO43";
  232                         bias-disable;
  233                         low-power-enable;
  234                 };
  235 
  236                 mux-mdio {
  237                         function = "mdio1";
  238                         groups = "mdio1_0_grp";
  239                 };
  240 
  241                 conf-mdio {
  242                         groups = "mdio1_0_grp";
  243                         slew-rate = <SLEW_RATE_SLOW>;
  244                         power-source = <IO_STANDARD_LVCMOS18>;
  245                         bias-disable;
  246                 };
  247         };
  248 
  249         pinctrl_sdhci0_default: sdhci0-default {
  250                 mux {
  251                         groups = "sdio0_0_grp";
  252                         function = "sdio0";
  253                 };
  254 
  255                 conf {
  256                         groups = "sdio0_0_grp";
  257                         slew-rate = <SLEW_RATE_SLOW>;
  258                         power-source = <IO_STANDARD_LVCMOS18>;
  259                         bias-disable;
  260                 };
  261 
  262                 mux-cd {
  263                         groups = "sdio0_cd_0_grp";
  264                         function = "sdio0_cd";
  265                 };
  266 
  267                 conf-cd {
  268                         groups = "sdio0_cd_0_grp";
  269                         bias-high-impedance;
  270                         bias-pull-up;
  271                         slew-rate = <SLEW_RATE_SLOW>;
  272                         power-source = <IO_STANDARD_LVCMOS18>;
  273                 };
  274 
  275                 mux-wp {
  276                         groups = "sdio0_wp_0_grp";
  277                         function = "sdio0_wp";
  278                 };
  279 
  280                 conf-wp {
  281                         groups = "sdio0_wp_0_grp";
  282                         bias-high-impedance;
  283                         bias-pull-up;
  284                         slew-rate = <SLEW_RATE_SLOW>;
  285                         power-source = <IO_STANDARD_LVCMOS18>;
  286                 };
  287         };
  288 
  289         pinctrl_watchdog0_default: watchdog0-default {
  290                 mux-clk {
  291                         groups = "swdt0_clk_1_grp";
  292                         function = "swdt0_clk";
  293                 };
  294 
  295                 conf-clk {
  296                         groups = "swdt0_clk_1_grp";
  297                         bias-pull-up;
  298                 };
  299 
  300                 mux-rst {
  301                         groups = "swdt0_rst_1_grp";
  302                         function = "swdt0_rst";
  303                 };
  304 
  305                 conf-rst {
  306                         groups = "swdt0_rst_1_grp";
  307                         bias-disable;
  308                         slew-rate = <SLEW_RATE_SLOW>;
  309                 };
  310         };
  311 
  312         pinctrl_ttc0_default: ttc0-default {
  313                 mux-clk {
  314                         groups = "ttc0_clk_0_grp";
  315                         function = "ttc0_clk";
  316                 };
  317 
  318                 conf-clk {
  319                         groups = "ttc0_clk_0_grp";
  320                         bias-pull-up;
  321                 };
  322 
  323                 mux-wav {
  324                         groups = "ttc0_wav_0_grp";
  325                         function = "ttc0_wav";
  326                 };
  327 
  328                 conf-wav {
  329                         groups = "ttc0_wav_0_grp";
  330                         bias-disable;
  331                         slew-rate = <SLEW_RATE_SLOW>;
  332                 };
  333         };
  334 
  335         pinctrl_ttc1_default: ttc1-default {
  336                 mux-clk {
  337                         groups = "ttc1_clk_0_grp";
  338                         function = "ttc1_clk";
  339                 };
  340 
  341                 conf-clk {
  342                         groups = "ttc1_clk_0_grp";
  343                         bias-pull-up;
  344                 };
  345 
  346                 mux-wav {
  347                         groups = "ttc1_wav_0_grp";
  348                         function = "ttc1_wav";
  349                 };
  350 
  351                 conf-wav {
  352                         groups = "ttc1_wav_0_grp";
  353                         bias-disable;
  354                         slew-rate = <SLEW_RATE_SLOW>;
  355                 };
  356         };
  357 
  358         pinctrl_ttc2_default: ttc2-default {
  359                 mux-clk {
  360                         groups = "ttc2_clk_0_grp";
  361                         function = "ttc2_clk";
  362                 };
  363 
  364                 conf-clk {
  365                         groups = "ttc2_clk_0_grp";
  366                         bias-pull-up;
  367                 };
  368 
  369                 mux-wav {
  370                         groups = "ttc2_wav_0_grp";
  371                         function = "ttc2_wav";
  372                 };
  373 
  374                 conf-wav {
  375                         groups = "ttc2_wav_0_grp";
  376                         bias-disable;
  377                         slew-rate = <SLEW_RATE_SLOW>;
  378                 };
  379         };
  380 
  381         pinctrl_ttc3_default: ttc3-default {
  382                 mux-clk {
  383                         groups = "ttc3_clk_0_grp";
  384                         function = "ttc3_clk";
  385                 };
  386 
  387                 conf-clk {
  388                         groups = "ttc3_clk_0_grp";
  389                         bias-pull-up;
  390                 };
  391 
  392                 mux-wav {
  393                         groups = "ttc3_wav_0_grp";
  394                         function = "ttc3_wav";
  395                 };
  396 
  397                 conf-wav {
  398                         groups = "ttc3_wav_0_grp";
  399                         bias-disable;
  400                         slew-rate = <SLEW_RATE_SLOW>;
  401                 };
  402         };
  403 };
  404 
  405 &sdhci0 {
  406         status = "okay";
  407         pinctrl-names = "default";
  408         pinctrl-0 = <&pinctrl_sdhci0_default>;
  409         no-1-8-v;
  410         xlnx,mio-bank = <0>;
  411 };
  412 
  413 &ttc0 {
  414         status = "okay";
  415         pinctrl-names = "default";
  416         pinctrl-0 = <&pinctrl_ttc0_default>;
  417 };
  418 
  419 &ttc1 {
  420         status = "okay";
  421         pinctrl-names = "default";
  422         pinctrl-0 = <&pinctrl_ttc1_default>;
  423 };
  424 
  425 &ttc2 {
  426         status = "okay";
  427         pinctrl-names = "default";
  428         pinctrl-0 = <&pinctrl_ttc2_default>;
  429 };
  430 
  431 &ttc3 {
  432         status = "okay";
  433         pinctrl-names = "default";
  434         pinctrl-0 = <&pinctrl_ttc3_default>;
  435 };
  436 
  437 &uart0 {
  438         status = "okay";
  439         pinctrl-names = "default";
  440         pinctrl-0 = <&pinctrl_uart0_default>;
  441 };
  442 
  443 &uart1 {
  444         status = "okay";
  445         pinctrl-names = "default";
  446         pinctrl-0 = <&pinctrl_uart1_default>;
  447 };
  448 
  449 &watchdog0 {
  450         status = "okay";
  451         pinctrl-names = "default";
  452         pinctrl-0 = <&pinctrl_watchdog0_default>;
  453 };
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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/arm64/xilinx/zynqmp-zc1751-xm019-dc5.dts
