The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/h8300/h8300h_sim.dts

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 / {
    4         compatible = "gnu,gdbsim";
    5         #address-cells = <1>;
    6         #size-cells = <1>;
    7         interrupt-parent = <&h8intc>;
    8 
    9         chosen {
   10                 bootargs = "earlyprintk=h8300-sim";
   11                 stdout-path = <&sci0>;
   12         };
   13         aliases {
   14                 serial0 = &sci0;
   15                 serial1 = &sci1;
   16         };
   17 
   18         xclk: oscillator {
   19                 #clock-cells = <0>;
   20                 compatible = "fixed-clock";
   21                 clock-frequency = <20000000>;
   22                 clock-output-names = "xtal";
   23         };
   24         core_clk: core_clk {
   25                 compatible = "renesas,h8300-div-clock";
   26                 clocks = <&xclk>;
   27                 #clock-cells = <0>;
   28                 reg = <0xfee01b 2>;
   29                 renesas,width = <2>;
   30         };
   31         fclk: fclk {
   32                 compatible = "fixed-factor-clock";
   33                 clocks = <&core_clk>;
   34                 #clock-cells = <0>;
   35                 clock-div = <1>;
   36                 clock-mult = <1>;
   37         };
   38 
   39         memory@400000 {
   40                 device_type = "memory";
   41                 reg = <0x400000 0x400000>;
   42         };
   43 
   44         cpus {
   45                 #address-cells = <1>;
   46                 #size-cells = <0>;
   47                 cpu@0 {
   48                         compatible = "renesas,h8300";
   49                         clock-frequency = <20000000>;
   50                 };
   51         };
   52 
   53         h8intc: interrupt-controller@fee012 {
   54                 compatible = "renesas,h8300h-intc", "renesas,h8300-intc";
   55                 #interrupt-cells = <2>;
   56                 interrupt-controller;
   57                 reg = <0xfee012 7>;
   58         };
   59 
   60         bsc: memory-controller@fee01e {
   61                 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
   62                 reg = <0xfee01e 8>;
   63         };
   64 
   65         timer8: timer@ffff80 {
   66                 compatible = "renesas,8bit-timer";
   67                 reg = <0xffff80 10>;
   68                 interrupts = <36 0>;
   69                 clocks = <&fclk>;
   70                 clock-names = "fck";
   71         };
   72 
   73         timer16: timer@ffff68 {
   74                 compatible = "renesas,16bit-timer";
   75                 reg = <0xffff68 8>, <0xffff60 8>;
   76                 interrupts = <26 0>;
   77                 renesas,channel = <0>;
   78                 clocks = <&fclk>;
   79                 clock-names = "fck";
   80         };
   81 
   82         sci0: serial@ffffb0 {
   83                 compatible = "renesas,sci";
   84                 reg = <0xffffb0 8>;
   85                 interrupts = <52 0>, <53 0>, <54 0>, <55 0>;
   86                 clocks = <&fclk>;
   87                 clock-names = "fck";
   88         };
   89 
   90         sci1: serial@ffffb8 {
   91                 compatible = "renesas,sci";
   92                 reg = <0xffffb8 8>;
   93                 interrupts = <56 0>, <57 0>, <58 0>, <59 0>;
   94                 clocks = <&fclk>;
   95                 clock-names = "fck";
   96         };
   97 };

Cache object: 4c80c19f1c2978727d17b66a270a0d20


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.